WO2018177195A1 - Charge pump, charge pump-based processing method and phase-locked loop circuit, and storage medium - Google Patents
Charge pump, charge pump-based processing method and phase-locked loop circuit, and storage medium Download PDFInfo
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- WO2018177195A1 WO2018177195A1 PCT/CN2018/080067 CN2018080067W WO2018177195A1 WO 2018177195 A1 WO2018177195 A1 WO 2018177195A1 CN 2018080067 W CN2018080067 W CN 2018080067W WO 2018177195 A1 WO2018177195 A1 WO 2018177195A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
- H03L7/0893—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
Definitions
- the present application relates to integrated circuit technology, and in particular, to a charge pump, a charge pump based processing method, a phase locked loop circuit, and a storage medium.
- phase-locked loop using a charge pump structure
- existing phase-locked loops using a charge pump structure generally include a Frequency Phase Detector (FPD), a Charge Pump (CP), a Low Pass Filter (LPF), and a Voltage Controlled Oscillator. (VCO, Voltage Control Oscillator) and other components.
- FPD Frequency Phase Detector
- CP Charge Pump
- LPF Low Pass Filter
- VCO Voltage Controlled Oscillator
- the role of the charge pump is to amplify the signal output by the FPD and charge and discharge the capacitance of the LPF.
- a charge pump also known as a switched-capacitor voltage converter, is a DC-DC converter that uses so-called “flying” or “pumping” capacitors (rather than inductors or transformers) to store energy.
- the charge pump uses an internal FET transistor switch array to control the transfer of charge on the capacitor in a certain way.
- the charge and discharge of the capacitor in the charge pump is controlled by a clock signal, so that the input voltage is raised or lowered in a certain manner to achieve The required output voltage.
- phase-locked loop circuits existing charge pumps are difficult to meet the requirements of the phase-locked loop circuit.
- the existing charge pump does not have high stability and matching due to the differential output voltage generated in a low voltage environment, which cannot meet the requirements of the inductor-capacitor voltage-controlled oscillator. The performance of the inductor-capacitor phase-locked loop circuit is degraded.
- the embodiments of the present application provide a charge pump, a charge pump-based processing method, a phase-locked loop circuit, and a storage medium, which are capable of generating a differential output voltage with high stability and matching in a low voltage environment.
- the embodiment of the present application provides a charge pump, the charge pump includes: a charge pump main circuit, a common mode feedback circuit, and a voltage bias circuit; wherein
- the charge pump main circuit is configured to generate a differential output voltage of the charge pump by using the input differential control signal
- the common mode feedback circuit is configured to generate a feedback voltage signal based on the differential output voltage and a common mode bias voltage provided by the voltage bias circuit, and output the feedback voltage signal to the charge pump main circuit And adjusting a common mode voltage of the differential output voltage generated by the charge pump main circuit based on the feedback voltage signal.
- the charge pump further includes: a zero point compensation circuit configured to compensate a phase of the common mode feedback circuit.
- the charge pump main circuit includes a first branch, a second branch connected to the first branch, and a third branch connected to the second branch;
- the first branch as a discharge current source, is configured to provide a discharge current for the second branch;
- the third branch as a charging current source, is configured to provide a charging current for the second branch; and receive a feedback voltage signal output by the common mode feedback circuit to adjust the charging current;
- the second branch is configured to determine a differential output voltage of the charge pump based on the input differential control signal, the charging current, and the discharging current.
- the common mode feedback circuit includes a fourth branch and a fifth branch;
- the fourth branch is configured to acquire a voltage to be detected by means of a resistor divider according to the differential output voltage; the voltage to be detected is greater than a half of a sum of the differential output voltages;
- the fifth branch is configured to compare the to-be-detected voltage and a common mode bias voltage provided by the voltage bias circuit, generate a feedback voltage signal according to the comparison result, and output the feedback voltage signal to the charge Pump main circuit.
- the first branch includes a first NMOS transistor and a second NMOS transistor
- the second branch includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor.
- the third branch includes a fifth PMOS transistor and a sixth PMOS transistor;
- the gate of the first NMOS transistor is connected to the gate of the second NMOS transistor, and the gate of the first NMOS transistor and the gate of the second NMOS transistor are connected to the first voltage source, the source of the first NMOS transistor, and the second NMOS.
- the source of the tube is grounded; the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor and the drain of the third PMOS transistor; the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor and the fourth PMOS transistor.
- the drain of the first PMOS transistor is connected to the first control signal, the source of the first PMOS transistor is connected to the source of the second PMOS transistor, and the source of the first PMOS transistor and the source of the second PMOS transistor Connected to the drain of the fifth PMOS transistor; the gate of the second PMOS transistor is connected to the second control signal; the gate of the third PMOS transistor is connected to the third control signal, and the source of the third PMOS transistor is connected to the fourth PMOS transistor.
- the source, the source of the third PMOS transistor and the source of the fourth PMOS transistor are both connected to the drain of the sixth PMOS transistor; the gate of the fourth PMOS transistor is connected to the fourth control signal; the source of the fifth PMOS transistor a source of the sixth PMOS transistor is connected
- the fourth branch includes a first resistor, a second resistor, and a third resistor
- the fifth branch includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a seventh PMOS transistor.
- One end of the first resistor is connected to the drain of the first NMOS transistor, the drain of the first PMOS transistor and the drain of the third PMOS transistor, and the other end is connected to the second resistor; one end of the second resistor is connected to the drain of the second NMOS transistor, a drain of the second PMOS transistor and a drain of the fourth PMOS transistor, and the other end is connected to the first resistor; one end of the third resistor is connected to the gate of the fourth NMOS transistor, the first resistor and the second resistor, and the other end is connected to the third a voltage source; a drain of the third NMOS transistor is connected to a source of the fourth NMOS transistor and a source of the fifth NMOS transistor, a gate of the third NMOS transistor is connected to the first voltage source, and a source of the third NMOS transistor is grounded; The gate of the seventh PMOS transistor is connected to the gate of the eighth PMOS transistor, and the drain of the seventh PMOS transistor is connected to the gate of the seventh PMOS transistor,
- the drain of the tube; the gate of the tenth PMOS transistor is connected to the gate of the ninth PMOS transistor, and the drain of the tenth PMOS transistor is connected to the gate of the tenth PMOS transistor, the gate of the ninth PMOS transistor, and the eighth PMOS transistor a drain, a drain of the fifth NMOS transistor, a gate of the fifth PMOS transistor, a gate of the sixth PMOS transistor, a source of the seventh PMOS transistor, a source of the eighth PMOS transistor, and a ninth
- the source of the PMOS transistor and the source of the tenth PMOS transistor are all connected to the second voltage source.
- the voltage bias circuit includes a fourth resistor and a fifth resistor
- One end of the fourth resistor is connected to the gate of the fifth NMOS transistor and the fifth resistor, and the other end is connected to the fourth voltage source; one end of the fifth resistor is connected to the gate of the fifth NMOS transistor and the fourth resistor, and the other end is grounded.
- the zero point compensation circuit includes a sixth resistor and a capacitor
- One end of the sixth resistor is connected to the gate of the fourth NMOS transistor, the first resistor, the second resistor, and the third resistor, and the other end is connected to the capacitor; one end of the capacitor is connected to the sixth resistor, and the other end is grounded.
- the resistance of the first resistor is equal to the resistance of the second resistor.
- the aspect ratio of the first NMOS transistor is equal to the aspect ratio of the second NMOS transistor;
- the width to length ratio of the third NMOS transistor is equal to the aspect ratio of the first NMOS transistor;
- the width to length ratio of the fourth NMOS transistor is equal to the width to length ratio of the fifth NMOS transistor;
- the aspect ratio of the first PMOS transistor is equal to the aspect ratio of the second PMOS transistor, the aspect ratio of the third PMOS transistor, and the width to length ratio of the fourth PMOS transistor;
- the width to length ratio of the fifth PMOS transistor is equal to a width to length ratio of the sixth PMOS transistor;
- a width to length ratio of the seventh PMOS transistor is equal to a width to length ratio of the eighth PMOS transistor, a width to length ratio of the ninth PMOS transistor, and a width to length ratio of the tenth PMOS transistor.
- the embodiment of the present application further provides a charge pump based processing method, the method comprising:
- the method further includes:
- a zero point is introduced in the feedback function to perform phase compensation.
- the differential output voltage of the charge pump is generated by using the input differential control signal, including:
- the charging current includes: adjusting the charging current generated by the charging current source according to the feedback voltage signal Current.
- Generating a feedback voltage signal based on the differential output voltage and the common mode bias voltage including:
- the differential output voltage a voltage to be detected by using a voltage division method; the voltage to be detected is greater than a half of a sum of the differential output voltages;
- the voltage to be detected and the common mode bias voltage are compared, and a feedback voltage signal is generated according to the comparison result.
- the embodiment of the present application further provides a phase locked loop circuit, the phase locked loop circuit includes: a frequency discrimination phase detector, a charge pump connected to the phase frequency detector, and a low pass filter connected to the charge pump And a voltage controlled oscillator connected to the low pass filter; wherein
- the charge pump includes a charge pump main circuit, a common mode feedback circuit, and a voltage bias circuit;
- the charge pump main circuit is configured to generate a differential output voltage of the charge pump by using the input differential control signal
- the common mode feedback circuit is configured to generate a feedback voltage signal based on the differential output voltage and a common mode bias voltage provided by the voltage bias circuit, and output the feedback voltage signal to the charge pump main circuit And adjusting a common mode voltage of the differential output generated by the charge pump main circuit based on the feedback voltage signal.
- the charge pump is specifically any one of the charge pumps described above.
- the embodiment of the present application further provides a storage medium storing computer executable instructions, and when the computer executable instructions are executed, implementing the charge pump based processing method according to any one of the foregoing aspects.
- the charge pump, the charge pump-based processing method and the phase-locked loop circuit provided by the embodiment of the present application include: a charge pump main circuit, a common mode feedback circuit, and a voltage bias circuit; and the charge pump main circuit is used for Generating a differential output voltage of the charge pump using the input differential control signal; the common mode feedback circuit for generating a feedback voltage signal based on the differential output voltage and a common mode bias voltage provided by the voltage bias circuit, And outputting the feedback voltage signal to the charge pump main circuit to adjust a common mode voltage of the differential output voltage generated by the charge pump main circuit based on the feedback voltage signal.
- the charge pump provided by the embodiment of the present application can convert the differential output voltage into a feedback voltage signal to adjust the output differential output voltage based on the feedback voltage signal, thereby ensuring that the charge pump is generated in a low voltage environment. Differential output voltage for stability and matching.
- FIG. 1 is a schematic structural diagram of a charge pump provided in Embodiment 1 of the present application.
- FIG. 2 is a schematic diagram showing an implementation flow of a charge pump-based processing method according to Embodiment 1 of the present application;
- FIG. 3 is a schematic structural diagram of a specific structure of a charge pump according to Embodiment 1 of the present application;
- FIG. 4 is a schematic structural diagram of a phase locked loop circuit according to Embodiment 2 of the present application.
- the charge pump 1 is a schematic structural diagram of a charge pump according to Embodiment 1 of the present application.
- the charge pump 1 includes a charge pump main circuit 11, a common mode feedback circuit 12, and a voltage bias circuit 13;
- the charge pump main circuit 11 is configured to generate a differential output voltage of the charge pump by using the input differential control signal;
- the common mode feedback circuit 12 is configured to generate a feedback voltage signal based on the differential output voltage and a common mode bias voltage provided by the voltage bias circuit 13, and output the feedback voltage signal to the charge pump a main circuit to adjust a common mode voltage of a differential output voltage generated by the charge pump main circuit based on the feedback voltage signal.
- the charge pump main circuit 11 includes a first branch 111, a second branch 112 connected to the first branch 111, and a third branch 113 connected to the second branch 112;
- the first branch 111 as a discharge current source, is configured to provide a discharge current for the second branch 112;
- the third branch 113 as a charging current source, is configured to provide a charging current for the second branch 112; and receive a feedback voltage signal output by the common mode feedback circuit 12 to adjust the charging current;
- the second branch 112 is configured to determine a differential output voltage of the charge pump based on the input differential control signal, the charging current, and the discharging current.
- the second branch 112 is specifically configured to determine a differential output voltage of the charge pump according to the input differential control signal, the charging current provided by the third branch 113, and the discharge current provided by the first branch 111.
- the differential output voltage is adjusted based on the input differential control signal, the adjusted charging current provided by the third branch 113, and the discharge current provided by the first branch 111.
- the second branch 112 adjusts the differential output voltage according to the input differential control signal, the adjusted charging current and the discharging current, in order to realize the charge pump by adjusting the differential output voltage of the charge pump.
- the differential output voltage is adjusted for the common mode voltage.
- the common mode feedback circuit 12 includes a fourth branch 121 and a fifth branch 122;
- the fourth branch 121 is configured to acquire a voltage to be detected by means of a resistor divider according to the differential output voltage; the voltage to be detected is greater than a half of a sum of the differential output voltages;
- the fifth branch 122 is configured to compare the voltage to be detected and the common mode bias voltage provided by the voltage bias circuit 13, generate a feedback voltage signal according to the comparison result, and output the feedback voltage signal to the The charge pump main circuit 11 is described.
- the common mode feedback circuit 12 generates a feedback voltage signal by using the common mode bias voltage supplied from the voltage bias circuit 13 as a reference, so that the charge pump main circuit 11 adjusts the differential output voltage according to the feedback voltage signal. To ensure the stability and matching of the differential output voltage.
- the charge pump 1 further includes a zero point compensation circuit 14 configured to compensate a phase of the common mode feedback circuit 13.
- the zero point compensation circuit 14 compensates the phase of the common mode feedback circuit 13 by introducing a zero point, which can further improve the stability of the charge pump, that is, further improve the stability of the differential output voltage.
- FIG. 2 is a schematic flowchart of an implementation process of a charge pump-based processing method according to Embodiment 1 of the present application, where the method includes:
- Step 101 Generate a differential output voltage of the charge pump by using the input differential control signal
- Step 102 Generate a feedback voltage signal based on the differential output voltage and the common mode bias voltage.
- a voltage to be detected is obtained by using a voltage division method; the voltage to be detected is greater than a half of a sum of the differential output voltages; and the voltage to be detected and the common mode offset are compared.
- the voltage is set, and a feedback voltage signal is generated according to the comparison result.
- Step 103 Adjust a common mode voltage of the differential output voltage according to the feedback voltage signal.
- the method further includes:
- a zero point is introduced in the feedback function to perform phase compensation.
- charge pump based processing method provided by the embodiment of the present application can be implemented by the above charge pump.
- the charge pump includes: a first NMOS transistor M1, a second NMOS transistor M2, a first PMOS transistor M3, a second PMOS transistor M4, and a third PMOS.
- the NMOS transistor M1 and the second NMOS transistor M2 form a first branch
- the first PMOS transistor M3, the second PMOS transistor M4, the third PMOS transistor M5, and the fourth PMOS transistor M6 form a second branch
- the sixth PMOS transistor M8 constitutes a third branch, that is, the first NMOS transistor M1, the second NMOS transistor M2, the first PMOS transistor M3, the second PMOS transistor M4, the third PMOS transistor M5, the fourth PM
- the OS tube M12, the eighth PMOS tube M13, the ninth PMOS tube M14, and the tenth PMOS tube M15 form a fifth branch, that is, the first resistor R1, the second resistor R2, the third resistor R3, and the third NMOS transistor M9
- the four NMOS transistors M10, the fifth NMOS transistor M11, the seventh PMOS transistor M12, the eighth PMOS transistor M13, the ninth PMOS transistor M14, and the tenth PMOS transistor M15 form a common mode feedback circuit;
- the fourth resistor R4 and the fifth resistor R5 constitute a voltage bias circuit;
- a sixth resistor R6 and a capacitor C constitute a zero point compensation circuit;
- connection relationship in the charge pump shown in Figure 3 is:
- the gate of the first NMOS transistor M1 is connected to the gate of the second NMOS transistor M2, and the gate of the first NMOS transistor M1 and the gate of the second NMOS transistor M2 are connected to the first voltage source VDD1.
- the source of the first NMOS transistor M1 and the source of the second NMOS transistor M2 are grounded; the drain of the first NMOS transistor M1 is connected to the drain of the first PMOS transistor M3 and the drain of the third PMOS transistor M5; the second NMOS The drain of the tube M2 is connected to the drain of the second PMOS transistor M4 and the drain of the fourth PMOS transistor M6; the gate of the first PMOS transistor M3 is connected to the first control signal UP, and the source of the first PMOS transistor M3 is connected.
- the source of the second PMOS transistor M4, and the source of the first PMOS transistor M3 and the source of the second PMOS transistor M4 are connected to the drain of the fifth PMOS transistor M7; the gate of the second PMOS transistor M4 is connected to the second control The signal UPB; the gate of the third PMOS transistor M5 is connected to the third control signal DNB, the source of the third PMOS transistor M5 is connected to the source of the fourth PMOS transistor M6, and the source of the third PMOS transistor M5 and the fourth PMOS
- the source of the tube M6 is connected to the drain of the sixth PMOS transistor M8; the gate of the fourth PMOS transistor M6 is connected to the fourth control signal DN; the source of the fifth PMOS transistor M7 and the source of the sixth PMOS transistor M8 are connected.
- Second voltage source VDD2, fifth PMOS transistor M7 The gate is connected to the gate of the sixth PMOS transistor M8; the first control signal UP, the second control signal UPB, the third control signal DNB and the fourth control signal DN are the input differential control signals;
- the second control signal UPB is a differential signal of the first control signal UP;
- the fourth control signal DN is a differential signal of the third control signal DNB.
- one end of the first resistor R1 is connected to the drain of the first NMOS transistor M1, the drain of the first PMOS transistor M3 and the drain of the third PMOS transistor M5, and the other end is connected to the second resistor R2;
- One end of the two resistor R2 is connected to the drain of the second NMOS transistor M2, the drain of the second PMOS transistor M4 and the drain of the fourth PMOS transistor M6, and the other end is connected to the first resistor R1;
- one end of the third resistor R3 is connected to the fourth NMOS
- the gate of the tube M6, the first resistor R1 and the second resistor R2, and the other end is connected to the third voltage source VDD3;
- the drain of the third NMOS transistor M5 is connected to the source of the fourth NMOS transistor M10 and the source of the fifth NMOS transistor M11
- the gate of the third NMOS transistor M9 is connected to the first voltage source VDD1, the source of the third NMOS transistor M9 is grounded; the gate of the
- the gate of the nine PMOS transistor M14, the drain of the tenth PMOS transistor M15 is connected to the gate of the tenth PMOS transistor M15, the gate of the ninth PMOS transistor M14, the drain of the eighth PMOS transistor M13, and the fifth NMOS transistor M11.
- the source of the PMOS transistor M15 is connected to the second voltage source VDD2.
- one end of the fourth resistor R4 is connected to the gate of the fifth NMOS transistor M11 and the fifth resistor R5, and the other end is connected to the fourth voltage source VDD4; one end of the fifth resistor R5 is connected to the gate of the fifth NMOS transistor M11.
- the pole and the fourth resistor R4 are grounded at the other end.
- one end of the sixth resistor R6 is connected to the gate of the fourth NMOS transistor M10, the first resistor R1, the second resistor R2, and the third resistor R3, and the other end is connected to the capacitor C; one end of the capacitor C is connected to the sixth resistor. R6, the other end is grounded.
- the main circuit of the charge pump composed of M8 is a completely symmetrical structure.
- the charge pump main circuit converts the charge and discharge signals outputted by the PFD into a charge and discharge current to the charge pump output capacitor, and then converts it into a voltage signal through the LPF, thereby performing LCVCO on the LCVCO.
- the first branch formed by the first NMOS transistor M1 and the second NMOS transistor M2 acts as a discharge current source under the action of the first voltage source VDD1 Providing a pull-down current for the charge pump, that is, providing a discharge current by the second branch formed by the first PMOS transistor M3, the second PMOS transistor M4, the third PMOS transistor M5, and the fourth PMOS transistor M6; the first PMOS transistor M3, The second PMOS transistor M4, the third PMOS transistor M5, and the fourth PMOS transistor M6 serve as input terminals of the charge pump, and are connected to the charge and discharge control signals of the PFD output; however, it should be noted that the width to length ratio of the first NMOS transistor M1 should be Equal to the aspect ratio of the second NMOS transistor M2, the aspect ratio of the first PMOS transistor M3 and the second P The width-to-length ratio of the MOS transistor is equal to the width-to-length ratio of the third PMOS transistor
- the differential signals UPB and DNB of the UP and DN respectively control the second PMOS transistor M4 and the third PMOS transistor M5, and the drains of the second PMOS transistor M4 and the third PMOS transistor M5 are cross-connected to the output nodes of VOUTP and VOUTN.
- the charging and discharging speed is fully accelerated during charging and discharging.
- the first control signal UP is the charging control signal
- the fourth control signal DN is the discharging control signal
- the second control signal UPB is the differential signal of the first control signal UP
- the third control signal DNB is the first
- the differential signal of the four control signals DN is taken as an example for description.
- the common mode feedback circuit formed by the PMOS transistor M14 and the tenth PMOS transistor M15 provides a stable common mode operating point for the charge pump, ensuring the stability of the charge pump operation.
- the resistance of the first resistor R1 should be equal to the resistance of the second resistor R2; the magnitude of the third voltage source VDD3 may need to be based on actual conditions such as the resistance of the first resistor R1 and the charge pump output common mode voltage VCMOUT.
- the width to length ratio of the third NMOS transistor M9 is equal to the width to length ratio of the first NMOS transistor M1; the aspect ratio of the seventh PMOS transistor M12 to the width to length ratio of the eighth PMOS transistor, and the ninth PMOS
- the width to length ratio of the tube and the width to length ratio of the tenth PMOS transistor are equal;
- the width to length ratio of the fourth NMOS transistor M10 is equal to the width to length ratio of the fifth NMOS transistor M11;
- the third NMOS transistor M9 forms a mirror image relationship with the first NMOS transistor M1.
- the width and length ratios of the two are equal, and N times mirroring is achieved by finger or M.
- the resistance of the fourth resistor R4 and the resistance of the fifth resistor R5 may be equal or not equal; the third voltage source VDD3 and the fourth voltage source VDD4 may be the same voltage source or different voltages.
- the source that is, the voltages provided by the third voltage source VDD3 and the fourth voltage source VDD4 may be the same or different; in practical applications, the third voltage source VDD3 and the appropriate size may be selected according to actual needs.
- the charge pump output common mode voltage VCMOUT remains stable, so that the input voltage VCM of the gate of the fourth NMOS transistor M10 is equal to the fifth NMOS transistor M11.
- the input voltage VB of the gate is the common mode bias voltage provided by the voltage bias circuit.
- the feedback voltage signal VFB generated by the common mode feedback circuit does not adjust the output of the fifth PMOS transistor M7 and the sixth PMOS transistor M8.
- the charging current that is, maintains the balance between the differential output voltages VOUTP and VOUTN; when the differential output voltages VOUTP and VOUTN change due to changes in UP and DN, the fourth NMOS transistor is caused by the differential output voltages VOUTP and VOUTN.
- the input voltage VCM of the gate of M10 changes, and the input voltage VB of the gate of the fifth NMOS transistor M11 is stable, which will cause the input voltage VCM of the gate of the fourth NMOS transistor M10 and the fifth NMOS transistor.
- the imbalance between the input voltage VB of the gate of M11 causes the common mode feedback circuit to output the VCM change to the charge pump main circuit through the feedback voltage signal VFB, so that the charge pump main circuit adjusts the fifth PMOS transistor M7, sixth.
- PMOS M8 charging current changing the differential output voltage VOUTP, VOUTN, to re-enable gate input of the fourth NMOS transistor M10 is equal to the gate voltage VCM fifth NMOS transistor M11 of the input voltage VB
- the first NMOS transistor M1, the second NMOS transistor M2, the first PMOS transistor M3, the second PMOS transistor M4, the third PMOS transistor M5, the fourth PMOS transistor M6, the fifth PMOS transistor M7, and the sixth PMOS transistor The charge pump main circuit composed of M8 converts the differential input control signal pair UP and UPB, DN and DNB into differential output signals VOUTP and VOUTN, and the first resistor R1, the second resistor R2, the third resistor R3, and the third NMOS transistor M9.
- the common mode feedback circuit formed by the fourth NMOS transistor M10, the fifth NMOS transistor M11, the seventh PMOS transistor M12, the eighth PMOS transistor M13, the ninth PMOS transistor M14, and the tenth PMOS transistor M15 is obtained according to the differential output signals VOUTP and VOUTN.
- the detection voltage is the input voltage VCM of the gate of the fourth NMOS transistor M10, and the change of the VCM is converted into the feedback voltage signal VFB and fed back to the main circuit of the charge pump for common mode adjustment, so that the differential output signal has high stability. It also has a good match.
- the charge pump provided in this embodiment can be applied to an integrated circuit such as a phase locked loop circuit, a clock data recovery circuit, a memory circuit read/write circuit, or the like.
- phase-locked loop circuit includes: a charge pump 1, a phase frequency detector, a low-pass filter 3, and a voltage-controlled oscillator 4; ,
- the phase frequency detector 2 is configured to compare the input reference signal with the output signal of the voltage controlled oscillator 4 to generate a comparison result
- the charge pump 1 is configured to adjust an output voltage according to a comparison result of the phase frequency detector 2;
- the low pass filter 3 is configured to filter an output voltage of the charge pump 1;
- the voltage controlled oscillator 4 is configured to adjust the frequency of the output signal in accordance with the output voltage filtered by the low pass filter 3.
- the phase-locked loop circuit shown in FIG. 4 operates on the principle that when the phase frequency detector 2 detects that the frequency of the output signal of the voltage-controlled oscillator 4 is less than the frequency of the reference signal, The charge pump 1 raises an output voltage of the charge pump 1, and the output voltage is filtered by the low-pass filter 3 to output a DC voltage portion, and the frequency of the output signal of the voltage controlled oscillator 4 is at the rise The frequency of the output signal is increased under the control of the high voltage.
- the charge pump 1 lowers the output voltage of the charge pump 1, after After filtering, the voltage controlled oscillator 4 reduces the frequency of the output signal according to the reduced voltage; after repeated adjustments until the frequency of the output signal of the voltage controlled oscillator 4 is equal to the frequency of the reference signal, the voltage control The output signal of the oscillator 4 is locked.
- the output signal of the voltage controlled oscillator 4 may be a signal obtained by dividing a signal output by the voltage controlled oscillator 4
- the charge pump 1 may be any one of the above-described first embodiment.
- a storage medium provided by an embodiment of the present application stores a computer executable instruction, and when the computer executable instruction is executed, the charge pump based processing method according to any one of the above embodiments is implemented.
- the charge pump can ensure the high stability of the charge pump in a low voltage environment by converting the differential output voltage into a feedback voltage signal to adjust the output differential output voltage based on the feedback voltage signal. And matching differential output voltage.
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Abstract
A charge pump (1), a charge pump-based processing method and phase-locked loop circuit, and a storage medium. The charge pump comprises a charge pump main circuit (11), a common-mode feedback circuit (12), and a voltage bias circuit (13). The charge pump main circuit generates a differential output voltage of the charge pump by means of an input differential control signal. The common-mode feedback circuit generates a feedback voltage signal on the basis of the differential output voltage and a common-mode bias voltage provided by the voltage bias circuit, and outputs the feedback voltage signal to the charge pump main circuit, so as to adjust the common-mode voltage of the differential output voltage generated by the charge pump main circuit on the basis of the feedback voltage signal. The charge pump can generate a differential output voltage having high stability and a high matching property in a low-voltage environment.
Description
相关申请的交叉引用Cross-reference to related applications
本申请基于申请号为201710194256.4、申请日为2017年03月28日的中国专利申请提出,并要求该中国专利申请的优先权,该中国专利申请的全部内容在此引入本申请作为参考。The present application is based on a Chinese patent application filed on Jan. 28, 2017, the entire disclosure of which is hereby incorporated by reference.
本申请涉及集成电路技术,尤其涉及一种电荷泵、基于电荷泵的处理方法及锁相环电路、存储介质。The present application relates to integrated circuit technology, and in particular, to a charge pump, a charge pump based processing method, a phase locked loop circuit, and a storage medium.
近年来,采用电荷泵结构的锁相环(PLL,Phase-Locked Loop)由于能够提供准确、低抖动的时钟信号,被广泛的应用于各种电子装置中。现有采用电荷泵结构的锁相环一般包括鉴频鉴相器(FPD,Frequency Phase Detector)、电荷泵(CP,Charge Pump)、低通滤波器(LPF,Low Pass Filter)和压控振荡器(VCO,Voltage Control Oscillator)等部件。其中,电荷泵的作用是将FPD输出的信号放大,给LPF的电容进行充放电。电荷泵也称为开关电容式电压变换器,是一种利用所谓的“快速”(flying)或“泵送”电容(而非电感或变压器)来储能的直流-直流变换器。电荷泵利用内部的场效应晶体管开关阵列以一定的方式控制电容上电荷的传输,通常是以时钟信号控制电荷泵中电容的充放电,从而使输入电压以一定的方式升高或降低,以达到所需要的输出电压。In recent years, a phase-locked loop (PLL) using a charge pump structure has been widely used in various electronic devices because it can provide an accurate and low-jitter clock signal. Existing phase-locked loops using a charge pump structure generally include a Frequency Phase Detector (FPD), a Charge Pump (CP), a Low Pass Filter (LPF), and a Voltage Controlled Oscillator. (VCO, Voltage Control Oscillator) and other components. Among them, the role of the charge pump is to amplify the signal output by the FPD and charge and discharge the capacitance of the LPF. A charge pump, also known as a switched-capacitor voltage converter, is a DC-DC converter that uses so-called "flying" or "pumping" capacitors (rather than inductors or transformers) to store energy. The charge pump uses an internal FET transistor switch array to control the transfer of charge on the capacitor in a certain way. Usually, the charge and discharge of the capacitor in the charge pump is controlled by a clock signal, so that the input voltage is raised or lowered in a certain manner to achieve The required output voltage.
然而,在一些锁相环电路中,现有的电荷泵难以满足该锁相环电路的要求。例如,在电感电容锁相环电路中,现有的电荷泵由于在低电压环境下所产生的差分输出电压不具有较高的稳定性和匹配性,导致无法满足电感电容压控振荡器的要求,致使电感电容锁相环电路的性能下降。However, in some phase-locked loop circuits, existing charge pumps are difficult to meet the requirements of the phase-locked loop circuit. For example, in an inductor-capacitor phase-locked loop circuit, the existing charge pump does not have high stability and matching due to the differential output voltage generated in a low voltage environment, which cannot meet the requirements of the inductor-capacitor voltage-controlled oscillator. The performance of the inductor-capacitor phase-locked loop circuit is degraded.
发明内容Summary of the invention
有鉴于此,本申请实施例提供了一种电荷泵、基于电荷泵的处理方法及锁相环电路、存储介质,能够在低电压环境下产生具有较高稳定性和匹配性的差分输出电压。In view of this, the embodiments of the present application provide a charge pump, a charge pump-based processing method, a phase-locked loop circuit, and a storage medium, which are capable of generating a differential output voltage with high stability and matching in a low voltage environment.
为达到上述目的,本申请的技术方案是这样实现的:In order to achieve the above object, the technical solution of the present application is implemented as follows:
本申请实施例提供一种电荷泵,所述电荷泵包括:电荷泵主电路、共模反馈电路、电压偏置电路;其中,The embodiment of the present application provides a charge pump, the charge pump includes: a charge pump main circuit, a common mode feedback circuit, and a voltage bias circuit; wherein
所述电荷泵主电路,配置为利用输入的差分控制信号,产生电荷泵的差分输出电压;The charge pump main circuit is configured to generate a differential output voltage of the charge pump by using the input differential control signal;
所述共模反馈电路,配置为基于所述差分输出电压和所述电压偏置电路提供的共模偏置电压,生成反馈电压信号,并将所述反馈电压信号输出至所述电荷泵主电路,以基于所述反馈电压信号调整所述电荷泵主电路产生的差分输出电压的共模电压。The common mode feedback circuit is configured to generate a feedback voltage signal based on the differential output voltage and a common mode bias voltage provided by the voltage bias circuit, and output the feedback voltage signal to the charge pump main circuit And adjusting a common mode voltage of the differential output voltage generated by the charge pump main circuit based on the feedback voltage signal.
上述方案中,所述电荷泵还包括:零点补偿电路,配置为对所述共模反馈电路的相位进行补偿。In the above solution, the charge pump further includes: a zero point compensation circuit configured to compensate a phase of the common mode feedback circuit.
上述方案中,所述电荷泵主电路包括第一支路、与所述第一支路连接的第二支路、与所述第二支路连接的第三支路;其中,In the above solution, the charge pump main circuit includes a first branch, a second branch connected to the first branch, and a third branch connected to the second branch; wherein
所述第一支路,作为放电电流源,配置为为所述第二支路提供放电电流;The first branch, as a discharge current source, is configured to provide a discharge current for the second branch;
所述第三支路,作为充电电流源,配置为为所述第二支路提供充电电流;以及,接收所述共模反馈电路输出的反馈电压信号,调整所述充电电流;The third branch, as a charging current source, is configured to provide a charging current for the second branch; and receive a feedback voltage signal output by the common mode feedback circuit to adjust the charging current;
所述第二支路,配置为根据输入的差分控制信号、充电电流和放电电流,确定电荷泵的差分输出电压。The second branch is configured to determine a differential output voltage of the charge pump based on the input differential control signal, the charging current, and the discharging current.
上述方案中,所述共模反馈电路包括第四支路、第五支路;其中,In the above solution, the common mode feedback circuit includes a fourth branch and a fifth branch; wherein
所述第四支路,配置为基于所述差分输出电压,利用电阻分压的方式,获取待检测电压;所述待检测电压大于所述差分输出电压之和的一半;The fourth branch is configured to acquire a voltage to be detected by means of a resistor divider according to the differential output voltage; the voltage to be detected is greater than a half of a sum of the differential output voltages;
所述第五支路,配置为比较所述待检测电压和所述电压偏置电路提供的共模偏置电压,根据比较结果产生反馈电压信号,并将所述反馈电压信号输出给所述电荷泵主电路。The fifth branch is configured to compare the to-be-detected voltage and a common mode bias voltage provided by the voltage bias circuit, generate a feedback voltage signal according to the comparison result, and output the feedback voltage signal to the charge Pump main circuit.
上述方案中,所述第一支路包括第一NMOS管、第二NMOS管,所述第二支路包括第一PMOS管、第二PMOS管、第三PMOS管、第四PMOS管,所述第三支路包括第五PMOS管、第六PMOS管;In the above solution, the first branch includes a first NMOS transistor and a second NMOS transistor, and the second branch includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor. The third branch includes a fifth PMOS transistor and a sixth PMOS transistor;
第一NMOS管的栅极连接第二NMOS管的栅极、且第一NMOS管的栅极和第二NMOS管的栅极都连接第一电压源,第一NMOS管的源极、第二NMOS管的源极接地;第一NMOS管的漏极连接第一PMOS管的漏极和第三PMOS管的漏极;第二NMOS管的漏极连接第二PMOS管的漏极和第四PMOS管的漏极;第一PMOS管的栅极接入第一控制信号,第一PMOS管的源极连接第二PMOS管的源极、且第一PMOS管的源极和第二PMOS管的源极都连接第五PMOS管的漏极;第二PMOS管的栅极接入第二控制信号;第三PMOS管的栅极接入第三控制信号,第三PMOS管的源极连接第四PMOS管的源极、且第三PMOS管的源极和第四PMOS管的源极都连接第六PMOS管的漏极;第四PMOS管的栅极接入第四控制信号;第五PMOS管的源极、第六PMOS管的源极连接第二电压源,第五PMOS管的栅极连接第六PMOS管的栅极;所述第一控制信号、第二控制信号、第三控制信号和第四控制信号为所述输入的差分控制信号;所述第二控制信号为所述第一控制信号的差分信号;所述第四控制信号为所述第三控制信号的差分信号。The gate of the first NMOS transistor is connected to the gate of the second NMOS transistor, and the gate of the first NMOS transistor and the gate of the second NMOS transistor are connected to the first voltage source, the source of the first NMOS transistor, and the second NMOS. The source of the tube is grounded; the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor and the drain of the third PMOS transistor; the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor and the fourth PMOS transistor The drain of the first PMOS transistor is connected to the first control signal, the source of the first PMOS transistor is connected to the source of the second PMOS transistor, and the source of the first PMOS transistor and the source of the second PMOS transistor Connected to the drain of the fifth PMOS transistor; the gate of the second PMOS transistor is connected to the second control signal; the gate of the third PMOS transistor is connected to the third control signal, and the source of the third PMOS transistor is connected to the fourth PMOS transistor The source, the source of the third PMOS transistor and the source of the fourth PMOS transistor are both connected to the drain of the sixth PMOS transistor; the gate of the fourth PMOS transistor is connected to the fourth control signal; the source of the fifth PMOS transistor a source of the sixth PMOS transistor is connected to the second voltage source, and a gate of the fifth PMOS transistor is connected to a gate of the sixth PMOS transistor; the first control signal, the second control signal, and the third control signal And a fourth control signal is input to the differential control signal; a second control signal is a differential signal of said first control signal; said fourth control signal to a differential signal of the third control signal.
上述方案中,所述第四支路包括第一电阻、第二电阻、第三电阻,所述第五支路包括第三NMOS管、第四NMOS管、第五NMOS管、第七PMOS管、第八PMOS管、第九PMOS管、第十PMOS管;In the above solution, the fourth branch includes a first resistor, a second resistor, and a third resistor, and the fifth branch includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a seventh PMOS transistor. An eighth PMOS transistor, a ninth PMOS transistor, and a tenth PMOS transistor;
第一电阻的一端连接第一NMOS管的漏极、第一PMOS管的漏极和第三PMOS管的漏极,另一端连接第二电阻;第二电阻一端连接第二NMOS管的漏极、第二PMOS管的漏极和第四PMOS管的漏极,另一端连接第一电阻;第三电阻的一端连接第四NMOS管的栅极、第一电阻和第二电阻,另一端连接第三电压源;第三NMOS管的漏极连接第四NMOS管的源极和 第五NMOS管的源极,第三NMOS管的栅极连接第一电压源,第三NMOS管的源极接地;第七PMOS管的栅极连接第八PMOS管的栅极,第七PMOS管的漏极连接第七PMOS管的栅极、第八PMOS管的栅极、第九PMOS管的漏极、第四NMOS管的漏极;第十PMOS管的栅极连接第九PMOS管的栅极,第十PMOS管的漏极连接第十PMOS管的栅极、第九PMOS管的栅极、第八PMOS管的漏极、第五NMOS管的漏极、第五PMOS管的栅极、第六PMOS管的栅极;第七PMOS管的源极、第八PMOS管的源极、第九PMOS管的源极、第十PMOS管的源极都连接第二电压源。One end of the first resistor is connected to the drain of the first NMOS transistor, the drain of the first PMOS transistor and the drain of the third PMOS transistor, and the other end is connected to the second resistor; one end of the second resistor is connected to the drain of the second NMOS transistor, a drain of the second PMOS transistor and a drain of the fourth PMOS transistor, and the other end is connected to the first resistor; one end of the third resistor is connected to the gate of the fourth NMOS transistor, the first resistor and the second resistor, and the other end is connected to the third a voltage source; a drain of the third NMOS transistor is connected to a source of the fourth NMOS transistor and a source of the fifth NMOS transistor, a gate of the third NMOS transistor is connected to the first voltage source, and a source of the third NMOS transistor is grounded; The gate of the seventh PMOS transistor is connected to the gate of the eighth PMOS transistor, and the drain of the seventh PMOS transistor is connected to the gate of the seventh PMOS transistor, the gate of the eighth PMOS transistor, the drain of the ninth PMOS transistor, and the fourth NMOS. The drain of the tube; the gate of the tenth PMOS transistor is connected to the gate of the ninth PMOS transistor, and the drain of the tenth PMOS transistor is connected to the gate of the tenth PMOS transistor, the gate of the ninth PMOS transistor, and the eighth PMOS transistor a drain, a drain of the fifth NMOS transistor, a gate of the fifth PMOS transistor, a gate of the sixth PMOS transistor, a source of the seventh PMOS transistor, a source of the eighth PMOS transistor, and a ninth The source of the PMOS transistor and the source of the tenth PMOS transistor are all connected to the second voltage source.
上述方案中,所述电压偏置电路包括第四电阻、第五电阻;In the above solution, the voltage bias circuit includes a fourth resistor and a fifth resistor;
第四电阻的一端连接第五NMOS管的栅极和第五电阻,另一端连接第四电压源;第五电阻一端连接第五NMOS管的栅极和第四电阻,另一端接地。One end of the fourth resistor is connected to the gate of the fifth NMOS transistor and the fifth resistor, and the other end is connected to the fourth voltage source; one end of the fifth resistor is connected to the gate of the fifth NMOS transistor and the fourth resistor, and the other end is grounded.
上述方案中,所述零点补偿电路包括第六电阻、电容;In the above solution, the zero point compensation circuit includes a sixth resistor and a capacitor;
第六电阻的一端连接第四NMOS管的栅极、第一电阻、第二电阻、第三电阻,另一端连接电容;电容一端连接第六电阻,另一端接地。One end of the sixth resistor is connected to the gate of the fourth NMOS transistor, the first resistor, the second resistor, and the third resistor, and the other end is connected to the capacitor; one end of the capacitor is connected to the sixth resistor, and the other end is grounded.
上述方案中,所述第一电阻的阻值等于所述第二电阻的阻值。In the above solution, the resistance of the first resistor is equal to the resistance of the second resistor.
上述方案中,所述第一NMOS管的宽长比等于所述第二NMOS管的宽长比;所述第三NMOS管的宽长比等于所述第一NMOS管的宽长比;所述第四NMOS管的宽长比等于第五NMOS管的宽长比;In the above solution, the aspect ratio of the first NMOS transistor is equal to the aspect ratio of the second NMOS transistor; the width to length ratio of the third NMOS transistor is equal to the aspect ratio of the first NMOS transistor; The width to length ratio of the fourth NMOS transistor is equal to the width to length ratio of the fifth NMOS transistor;
所述第一PMOS管的宽长比与第二PMOS管的宽长比、第三PMOS管的宽长比、第四PMOS管的宽长比相等;所述第五PMOS管的宽长比等于第六PMOS管的宽长比;所述第七PMOS管的宽长比与第八PMOS管的宽长比、第九PMOS管的宽长比、第十PMOS管的宽长比相等。The aspect ratio of the first PMOS transistor is equal to the aspect ratio of the second PMOS transistor, the aspect ratio of the third PMOS transistor, and the width to length ratio of the fourth PMOS transistor; the width to length ratio of the fifth PMOS transistor is equal to a width to length ratio of the sixth PMOS transistor; a width to length ratio of the seventh PMOS transistor is equal to a width to length ratio of the eighth PMOS transistor, a width to length ratio of the ninth PMOS transistor, and a width to length ratio of the tenth PMOS transistor.
本申请实施例还提供一种基于电荷泵的处理方法,所述方法包括:The embodiment of the present application further provides a charge pump based processing method, the method comprising:
利用输入的差分控制信号,产生电荷泵的差分输出电压;Using the input differential control signal to generate a differential output voltage of the charge pump;
基于所述差分输出电压和共模偏置电压,生成反馈电压信号;Generating a feedback voltage signal based on the differential output voltage and the common mode bias voltage;
根据所述反馈电压信号调整所述差分输出电压的共模电压。Adjusting a common mode voltage of the differential output voltage according to the feedback voltage signal.
上述方案中,所述方法还包括:In the above solution, the method further includes:
根据所述差分输出电压、所述共模偏置电压、所述反馈电压信号和所述差分输出电压的共模电压得到反馈函数;And obtaining a feedback function according to the differential output voltage, the common mode bias voltage, the feedback voltage signal, and a common mode voltage of the differential output voltage;
在所述反馈函数中引入零点,进行相位补偿。A zero point is introduced in the feedback function to perform phase compensation.
上述方案中,所述利用输入的差分控制信号,产生电荷泵的差分输出电压,包括:In the above solution, the differential output voltage of the charge pump is generated by using the input differential control signal, including:
根据输入的差分控制信号、充电电流和放电电流源产生的放电电流,确定电荷泵的差分输出电压;所述充电电流包括根据所述反馈电压信号对充电电流源产生的充电电流进行调整后得到的电流。Determining a differential output voltage of the charge pump according to the input differential control signal, the charging current, and the discharge current generated by the discharge current source; the charging current includes: adjusting the charging current generated by the charging current source according to the feedback voltage signal Current.
所述基于所述差分输出电压和共模偏置电压,生成反馈电压信号,包括:Generating a feedback voltage signal based on the differential output voltage and the common mode bias voltage, including:
基于所述差分输出电压,利用电阻分压的方式,获取待检测电压;所述待检测电压大于所述差分输出电压之和的一半;And obtaining, according to the differential output voltage, a voltage to be detected by using a voltage division method; the voltage to be detected is greater than a half of a sum of the differential output voltages;
比较所述待检测电压和所述共模偏置电压,根据比较结果产生反馈电压信号。The voltage to be detected and the common mode bias voltage are compared, and a feedback voltage signal is generated according to the comparison result.
本申请实施例又提供一种锁相环电路,所述锁相环电路包括:鉴频鉴相器、与所述鉴频鉴相器连接的电荷泵、与所述电荷泵连接的低通滤波器、与所述低通滤波器连接的压控振荡器;其中,The embodiment of the present application further provides a phase locked loop circuit, the phase locked loop circuit includes: a frequency discrimination phase detector, a charge pump connected to the phase frequency detector, and a low pass filter connected to the charge pump And a voltage controlled oscillator connected to the low pass filter; wherein
所述电荷泵包括电荷泵主电路、共模反馈电路、电压偏置电路;The charge pump includes a charge pump main circuit, a common mode feedback circuit, and a voltage bias circuit;
所述电荷泵主电路,配置为利用输入的差分控制信号,产生电荷泵的差分输出电压;The charge pump main circuit is configured to generate a differential output voltage of the charge pump by using the input differential control signal;
所述共模反馈电路,配置为基于所述差分输出电压和所述电压偏置电路提供的共模偏置电压,生成反馈电压信号,并将所述反馈电压信号输出至所述电荷泵主电路,以基于所述反馈电压信号调整所述电荷泵主电路产生的差分输出的共模电压。The common mode feedback circuit is configured to generate a feedback voltage signal based on the differential output voltage and a common mode bias voltage provided by the voltage bias circuit, and output the feedback voltage signal to the charge pump main circuit And adjusting a common mode voltage of the differential output generated by the charge pump main circuit based on the feedback voltage signal.
上述方案中,所述电荷泵具体为以上所述任意一种电荷泵。In the above solution, the charge pump is specifically any one of the charge pumps described above.
本申请实施例又提供一种存储介质,存储有计算机可执行指令,所述计算机可执行指令被执行时实现上述方案任意一项所述的基于电荷泵的处理方法。The embodiment of the present application further provides a storage medium storing computer executable instructions, and when the computer executable instructions are executed, implementing the charge pump based processing method according to any one of the foregoing aspects.
本申请实施例提供的电荷泵、基于电荷泵的处理方法及锁相环电路,该电荷泵包括:电荷泵主电路、共模反馈电路、电压偏置电路;所述电荷泵主电路,用于利用输入的差分控制信号,产生电荷泵的差分输出电压;所述共模反馈电路,用于基于所述差分输出电压和所述电压偏置电路提供的共模偏置电压,生成反馈电压信号,并将所述反馈电压信号输出至所述电荷泵主电路,以基于所述反馈电压信号调整所述电荷泵主电路产生的差分输出电压的共模电压。可见,本申请实施例提供的电荷泵通过将差分输出电压的变化转化为反馈电压信号,以基于所述反馈电压信号调节输出的差分输出电压,能够保证电荷泵在低电压环境下产生具有较高稳定性和匹配性的差分输出电压。The charge pump, the charge pump-based processing method and the phase-locked loop circuit provided by the embodiment of the present application include: a charge pump main circuit, a common mode feedback circuit, and a voltage bias circuit; and the charge pump main circuit is used for Generating a differential output voltage of the charge pump using the input differential control signal; the common mode feedback circuit for generating a feedback voltage signal based on the differential output voltage and a common mode bias voltage provided by the voltage bias circuit, And outputting the feedback voltage signal to the charge pump main circuit to adjust a common mode voltage of the differential output voltage generated by the charge pump main circuit based on the feedback voltage signal. It can be seen that the charge pump provided by the embodiment of the present application can convert the differential output voltage into a feedback voltage signal to adjust the output differential output voltage based on the feedback voltage signal, thereby ensuring that the charge pump is generated in a low voltage environment. Differential output voltage for stability and matching.
图1为本申请实施例一提供的电荷泵的组成结构示意图;1 is a schematic structural diagram of a charge pump provided in Embodiment 1 of the present application;
图2为本申请实施例一提供的基于电荷泵的处理方法的实现流程示意图;2 is a schematic diagram showing an implementation flow of a charge pump-based processing method according to Embodiment 1 of the present application;
图3为本申请实施例一提供的电荷泵的具体组成结构示意图;3 is a schematic structural diagram of a specific structure of a charge pump according to Embodiment 1 of the present application;
图4为本申请实施例二提供的锁相环电路的组成结构示意图。FIG. 4 is a schematic structural diagram of a phase locked loop circuit according to Embodiment 2 of the present application.
实施例一Embodiment 1
图1为本申请实施例一提供的电荷泵的组成结构示意图,该电荷泵1包括:电荷泵主电路11、共模反馈电路12、电压偏置电路13;其中,1 is a schematic structural diagram of a charge pump according to Embodiment 1 of the present application. The charge pump 1 includes a charge pump main circuit 11, a common mode feedback circuit 12, and a voltage bias circuit 13;
所述电荷泵主电路11,配置为利用输入的差分控制信号,产生电荷泵的差分输出电压;The charge pump main circuit 11 is configured to generate a differential output voltage of the charge pump by using the input differential control signal;
所述共模反馈电路12,配置为基于所述差分输出电压和所述电压偏置电路13提供的共模偏置电压,生成反馈电压信号,并将所述反馈电压信号输出至所述电荷泵主电路,以基于所述反馈电压信号调整所述电荷泵主电路产生的差分输出电压的共模电压。The common mode feedback circuit 12 is configured to generate a feedback voltage signal based on the differential output voltage and a common mode bias voltage provided by the voltage bias circuit 13, and output the feedback voltage signal to the charge pump a main circuit to adjust a common mode voltage of a differential output voltage generated by the charge pump main circuit based on the feedback voltage signal.
其中,所述电荷泵主电路11包括:第一支路111、与所述第一支路111连接的第二支路112、与所述第二支路112连接的第三支路113;The charge pump main circuit 11 includes a first branch 111, a second branch 112 connected to the first branch 111, and a third branch 113 connected to the second branch 112;
所述第一支路111,作为放电电流源,配置为为所述第二支路112提供放电电流;The first branch 111, as a discharge current source, is configured to provide a discharge current for the second branch 112;
所述第三支路113,作为充电电流源,配置为为所述第二支路112提供充电电流;以及,接收所述共模反馈电路12输出的反馈电压信号,调整所述充电电流;The third branch 113, as a charging current source, is configured to provide a charging current for the second branch 112; and receive a feedback voltage signal output by the common mode feedback circuit 12 to adjust the charging current;
所述第二支路112,配置为根据输入的差分控制信号、充电电流和放电电流,确定电荷泵的差分输出电压。The second branch 112 is configured to determine a differential output voltage of the charge pump based on the input differential control signal, the charging current, and the discharging current.
所述第二支路112,具体配置为:根据输入的差分控制信号、所述第三支路113提供的充电电流和所述第一支路111提供的放电电流,确定电荷泵的差分输出电压;根据输入的差分控制信号、所述第三支路113提供的调整后的充电电流和所述第一支路111提供的放电电流,调整所述差分输出电压。The second branch 112 is specifically configured to determine a differential output voltage of the charge pump according to the input differential control signal, the charging current provided by the third branch 113, and the discharge current provided by the first branch 111. The differential output voltage is adjusted based on the input differential control signal, the adjusted charging current provided by the third branch 113, and the discharge current provided by the first branch 111.
这里,所述第二支路112根据输入的差分控制信号、所述调整后的充电电流和放电电流,调整所述差分输出电压,目的在于通过调整电荷泵的差分输出电压,以实现对电荷泵的差分输出电压的共模电压的调整。Here, the second branch 112 adjusts the differential output voltage according to the input differential control signal, the adjusted charging current and the discharging current, in order to realize the charge pump by adjusting the differential output voltage of the charge pump. The differential output voltage is adjusted for the common mode voltage.
所述共模反馈电路12包括第四支路121、第五支路122;The common mode feedback circuit 12 includes a fourth branch 121 and a fifth branch 122;
所述第四支路121,配置为基于所述差分输出电压,利用电阻分压的方式,获取待检测电压;所述待检测电压大于所述差分输出电压之和的一半;The fourth branch 121 is configured to acquire a voltage to be detected by means of a resistor divider according to the differential output voltage; the voltage to be detected is greater than a half of a sum of the differential output voltages;
所述第五支路122,配置为比较所述待检测电压和所述电压偏置电路13提供的共模偏置电压,根据比较结果产生反馈电压信号,并将所述反馈电压信号输出给所述电荷泵主电路11。The fifth branch 122 is configured to compare the voltage to be detected and the common mode bias voltage provided by the voltage bias circuit 13, generate a feedback voltage signal according to the comparison result, and output the feedback voltage signal to the The charge pump main circuit 11 is described.
这里,当所述差分输出电压发生变化时,将引起所述电荷泵主电路产生的差分输出电压的共模电压的变化,从而使得所述差分输出电压的变化将体现在所述待检测电压中,因此,共模反馈电路12将所述电压偏置电路13提供的共模偏置电压作为参考而产生反馈电压信号,以使所述电荷泵主 电路11根据所述反馈电压信号调节差分输出电压,确保差分输出电压的稳定性和匹配性。Here, when the differential output voltage changes, a change in the common mode voltage of the differential output voltage generated by the charge pump main circuit is caused, so that a change in the differential output voltage is reflected in the to-be-detected voltage. Therefore, the common mode feedback circuit 12 generates a feedback voltage signal by using the common mode bias voltage supplied from the voltage bias circuit 13 as a reference, so that the charge pump main circuit 11 adjusts the differential output voltage according to the feedback voltage signal. To ensure the stability and matching of the differential output voltage.
进一步地,所述电荷泵1还包括:零点补偿电路14,配置为对所述共模反馈电路13的相位进行补偿。Further, the charge pump 1 further includes a zero point compensation circuit 14 configured to compensate a phase of the common mode feedback circuit 13.
这里,所述零点补偿电路14通过引入零点对所述共模反馈电路13的相位进行补偿,可进一步提高电荷泵的稳定性即进一步提高差分输出电压的稳定性。Here, the zero point compensation circuit 14 compensates the phase of the common mode feedback circuit 13 by introducing a zero point, which can further improve the stability of the charge pump, that is, further improve the stability of the differential output voltage.
图2为本申请实施例一提供的基于电荷泵的处理方法的实现流程示意图,该方法包括:2 is a schematic flowchart of an implementation process of a charge pump-based processing method according to Embodiment 1 of the present application, where the method includes:
步骤101:利用输入的差分控制信号,产生电荷泵的差分输出电压;Step 101: Generate a differential output voltage of the charge pump by using the input differential control signal;
具体地,根据输入的差分控制信号、充电电流源产生的充电电流和放电电流源产生的放电电流,确定电荷泵的差分输出电压;根据所述反馈电压信号调整所述充电电流源产生的充电电流;根据输入的差分控制信号、调整后的充电电流源产生的充电电流和所述放电电流,调整所述差分输出电压。Specifically, determining a differential output voltage of the charge pump according to the input differential control signal, the charging current generated by the charging current source, and the discharging current generated by the discharging current source; and adjusting a charging current generated by the charging current source according to the feedback voltage signal And adjusting the differential output voltage according to the input differential control signal, the charging current generated by the adjusted charging current source, and the discharging current.
步骤102:基于所述差分输出电压和共模偏置电压,生成反馈电压信号;Step 102: Generate a feedback voltage signal based on the differential output voltage and the common mode bias voltage.
具体地,基于所述差分输出电压,利用电阻分压的方式,获取待检测电压;所述待检测电压大于所述差分输出电压之和的一半;比较所述待检测电压和所述共模偏置电压,根据比较结果产生反馈电压信号。Specifically, based on the differential output voltage, a voltage to be detected is obtained by using a voltage division method; the voltage to be detected is greater than a half of a sum of the differential output voltages; and the voltage to be detected and the common mode offset are compared. The voltage is set, and a feedback voltage signal is generated according to the comparison result.
步骤103:根据所述反馈电压信号调整所述差分输出电压的共模电压。Step 103: Adjust a common mode voltage of the differential output voltage according to the feedback voltage signal.
进一步地,该方法还包括:Further, the method further includes:
根据所述差分输出电压、所述共模偏置电压、所述反馈电压信号和所述差分输出电压的共模电压得到反馈函数;And obtaining a feedback function according to the differential output voltage, the common mode bias voltage, the feedback voltage signal, and a common mode voltage of the differential output voltage;
在所述反馈函数中引入零点,进行相位补偿。A zero point is introduced in the feedback function to perform phase compensation.
需要说明的是,本申请实施例提供的基于电荷泵的处理方法可以通过上述电荷泵实现。It should be noted that the charge pump based processing method provided by the embodiment of the present application can be implemented by the above charge pump.
图3为本申请实施例一提供的电荷泵的具体组成结构示意图,该电荷 泵包括:第一NMOS管M1、第二NMOS管M2、第一PMOS管M3、第二PMOS管M4、第三PMOS管M5、第四PMOS管M6、第五PMOS管M7、第六PMOS管M8、第三NMOS管M9、第四NMOS管M10、第五NMOS管M11、第七PMOS管M12、第八PMOS管M13、第九PMOS管M14、第十PMOS管M15、第一电阻R1、第二电阻R2、第三电阻R3、第四电阻R4、第五电阻R5、第六电阻R6、电容C;其中,第一NMOS管M1、第二NMOS管M2构成第一支路,第一PMOS管M3、第二PMOS管M4、第三PMOS管M5、第四PMOS管M6构成第二支路,第五PMOS管M7、第六PMOS管M8构成第三支路,即第一NMOS管M1、第二NMOS管M2、第一PMOS管M3、第二PMOS管M4、第三PMOS管M5、第四PMOS管M6、第五PMOS管M7、第六PMOS管M8构成电荷泵主电路;第一电阻R1、第二电阻R2、第三电阻R3构成第四支路,第三NMOS管M9、第四NMOS管M10、第五NMOS管M11、第七PMOS管M12、第八PMOS管M13、第九PMOS管M14、第十PMOS管M15构成第五支路,即第一电阻R1、第二电阻R2、第三电阻R3、第三NMOS管M9、第四NMOS管M10、第五NMOS管M11、第七PMOS管M12、第八PMOS管M13、第九PMOS管M14、第十PMOS管M15构成共模反馈电路;第四电阻R4、第五电阻R5构成电压偏置电路;第六电阻R6、电容C构成零点补偿电路;3 is a schematic structural diagram of a specific structure of a charge pump according to Embodiment 1 of the present application. The charge pump includes: a first NMOS transistor M1, a second NMOS transistor M2, a first PMOS transistor M3, a second PMOS transistor M4, and a third PMOS. Tube M5, fourth PMOS transistor M6, fifth PMOS transistor M7, sixth PMOS transistor M8, third NMOS transistor M9, fourth NMOS transistor M10, fifth NMOS transistor M11, seventh PMOS transistor M12, and eighth PMOS transistor M13 a ninth PMOS transistor M14, a tenth PMOS transistor M15, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a capacitor C; The NMOS transistor M1 and the second NMOS transistor M2 form a first branch, and the first PMOS transistor M3, the second PMOS transistor M4, the third PMOS transistor M5, and the fourth PMOS transistor M6 form a second branch, and the fifth PMOS transistor M7, The sixth PMOS transistor M8 constitutes a third branch, that is, the first NMOS transistor M1, the second NMOS transistor M2, the first PMOS transistor M3, the second PMOS transistor M4, the third PMOS transistor M5, the fourth PMOS transistor M6, and the fifth The PMOS transistor M7 and the sixth PMOS transistor M8 form a main circuit of the charge pump; the first resistor R1, the second resistor R2, and the third resistor R3 form a fourth branch, a third NMOS transistor M9, a fourth NMOS transistor M10, and a fifth NMOS. Tube M11, seventh PM The OS tube M12, the eighth PMOS tube M13, the ninth PMOS tube M14, and the tenth PMOS tube M15 form a fifth branch, that is, the first resistor R1, the second resistor R2, the third resistor R3, and the third NMOS transistor M9, The four NMOS transistors M10, the fifth NMOS transistor M11, the seventh PMOS transistor M12, the eighth PMOS transistor M13, the ninth PMOS transistor M14, and the tenth PMOS transistor M15 form a common mode feedback circuit; the fourth resistor R4 and the fifth resistor R5 constitute a voltage bias circuit; a sixth resistor R6 and a capacitor C constitute a zero point compensation circuit;
其中,图3所示的电荷泵中的连接关系为:Among them, the connection relationship in the charge pump shown in Figure 3 is:
在电荷泵主电路中,第一NMOS管M1的栅极连接第二NMOS管M2的栅极、且第一NMOS管M1的栅极和第二NMOS管M2的栅极都连接第一电压源VDD1,第一NMOS管M1的源极、第二NMOS管M2的源极接地;第一NMOS管M1的漏极连接第一PMOS管M3的漏极和第三PMOS管M5的漏极;第二NMOS管M2的漏极连接第二PMOS管M4的漏极和第四PMOS管M6的漏极;第一PMOS管M3的栅极接入第一控制信号UP,第一PMOS管M3的源极连接第二PMOS管M4的源极、且第一PMOS管M3的源极和第二PMOS管M4的源极都连接第五PMOS管M7的漏极;第二PMOS管M4的栅极接入第二控制信号UPB;第三PMOS管M5的栅极接入第三控制信号DNB,第三PMOS管M5的源极连接第四PMOS管 M6的源极、且第三PMOS管M5的源极和第四PMOS管M6的源极都连接第六PMOS管M8的漏极;第四PMOS管M6的栅极接入第四控制信号DN;第五PMOS管M7的源极、第六PMOS管M8的源极连接第二电压源VDD2,第五PMOS管M7的栅极连接第六PMOS管M8的栅极;所述第一控制信号UP、第二控制信号UPB、第三控制信号DNB和第四控制信号DN为所述输入的差分控制信号;所述第二控制信号UPB为所述第一控制信号UP的差分信号;所述第四控制信号DN为所述第三控制信号DNB的差分信号。In the main circuit of the charge pump, the gate of the first NMOS transistor M1 is connected to the gate of the second NMOS transistor M2, and the gate of the first NMOS transistor M1 and the gate of the second NMOS transistor M2 are connected to the first voltage source VDD1. The source of the first NMOS transistor M1 and the source of the second NMOS transistor M2 are grounded; the drain of the first NMOS transistor M1 is connected to the drain of the first PMOS transistor M3 and the drain of the third PMOS transistor M5; the second NMOS The drain of the tube M2 is connected to the drain of the second PMOS transistor M4 and the drain of the fourth PMOS transistor M6; the gate of the first PMOS transistor M3 is connected to the first control signal UP, and the source of the first PMOS transistor M3 is connected. The source of the second PMOS transistor M4, and the source of the first PMOS transistor M3 and the source of the second PMOS transistor M4 are connected to the drain of the fifth PMOS transistor M7; the gate of the second PMOS transistor M4 is connected to the second control The signal UPB; the gate of the third PMOS transistor M5 is connected to the third control signal DNB, the source of the third PMOS transistor M5 is connected to the source of the fourth PMOS transistor M6, and the source of the third PMOS transistor M5 and the fourth PMOS The source of the tube M6 is connected to the drain of the sixth PMOS transistor M8; the gate of the fourth PMOS transistor M6 is connected to the fourth control signal DN; the source of the fifth PMOS transistor M7 and the source of the sixth PMOS transistor M8 are connected. Second voltage source VDD2, fifth PMOS transistor M7 The gate is connected to the gate of the sixth PMOS transistor M8; the first control signal UP, the second control signal UPB, the third control signal DNB and the fourth control signal DN are the input differential control signals; The second control signal UPB is a differential signal of the first control signal UP; the fourth control signal DN is a differential signal of the third control signal DNB.
在共模反馈电路中,第一电阻R1的一端连接第一NMOS管M1的漏极、第一PMOS管M3的漏极和第三PMOS管M5的漏极,另一端连接第二电阻R2;第二电阻R2一端连接第二NMOS管M2的漏极、第二PMOS管M4的漏极和第四PMOS管M6的漏极,另一端连接第一电阻R1;第三电阻R3的一端连接第四NMOS管M6的栅极、第一电阻R1和第二电阻R2,另一端连接第三电压源VDD3;第三NMOS管M5的漏极连接第四NMOS管M10的源极和第五NMOS管M11的源极,第三NMOS管M9的栅极连接第一电压源VDD1,第三NMOS管M9的源极接地;第七PMOS管M12的栅极连接第八PMOS管M13的栅极,第七PMOS管M12的漏极连接第七PMOS管M12的栅极、第八PMOS管M13的栅极、第九PMOS管M14的漏极、第四NMOS管M10的漏极;第十PMOS管M15的栅极连接第九PMOS管M14的栅极,第十PMOS管M15的漏极连接第十PMOS管M15的栅极、第九PMOS管M14的栅极、第八PMOS管M13的漏极、第五NMOS管M11的漏极、第五PMOS管M7的栅极、第六PMOS管M8的栅极;第七PMOS管M12的源极、第八PMOS管M13的源极、第九PMOS管M14的源极、第十PMOS管M15的源极都连接第二电压源VDD2。In the common mode feedback circuit, one end of the first resistor R1 is connected to the drain of the first NMOS transistor M1, the drain of the first PMOS transistor M3 and the drain of the third PMOS transistor M5, and the other end is connected to the second resistor R2; One end of the two resistor R2 is connected to the drain of the second NMOS transistor M2, the drain of the second PMOS transistor M4 and the drain of the fourth PMOS transistor M6, and the other end is connected to the first resistor R1; one end of the third resistor R3 is connected to the fourth NMOS The gate of the tube M6, the first resistor R1 and the second resistor R2, and the other end is connected to the third voltage source VDD3; the drain of the third NMOS transistor M5 is connected to the source of the fourth NMOS transistor M10 and the source of the fifth NMOS transistor M11 The gate of the third NMOS transistor M9 is connected to the first voltage source VDD1, the source of the third NMOS transistor M9 is grounded; the gate of the seventh PMOS transistor M12 is connected to the gate of the eighth PMOS transistor M13, and the seventh PMOS transistor M12 The drain is connected to the gate of the seventh PMOS transistor M12, the gate of the eighth PMOS transistor M13, the drain of the ninth PMOS transistor M14, the drain of the fourth NMOS transistor M10, and the gate connection of the tenth PMOS transistor M15. The gate of the nine PMOS transistor M14, the drain of the tenth PMOS transistor M15 is connected to the gate of the tenth PMOS transistor M15, the gate of the ninth PMOS transistor M14, the drain of the eighth PMOS transistor M13, and the fifth NMOS transistor M11. The drain, the gate of the fifth PMOS transistor M7, the gate of the sixth PMOS transistor M8, the source of the seventh PMOS transistor M12, the source of the eighth PMOS transistor M13, the source of the ninth PMOS transistor M14, and the tenth The source of the PMOS transistor M15 is connected to the second voltage source VDD2.
在电压偏置电路中,第四电阻R4的一端连接第五NMOS管M11的栅极和第五电阻R5,另一端连接第四电压源VDD4;第五电阻R5一端连接第五NMOS管M11的栅极和第四电阻R4,另一端接地。In the voltage bias circuit, one end of the fourth resistor R4 is connected to the gate of the fifth NMOS transistor M11 and the fifth resistor R5, and the other end is connected to the fourth voltage source VDD4; one end of the fifth resistor R5 is connected to the gate of the fifth NMOS transistor M11. The pole and the fourth resistor R4 are grounded at the other end.
在零点补偿电路中,第六电阻R6的一端连接第四NMOS管M10的栅极、第一电阻R1、第二电阻R2、第三电阻R3,另一端连接电容C;电容 C一端连接第六电阻R6,另一端接地。In the zero-point compensation circuit, one end of the sixth resistor R6 is connected to the gate of the fourth NMOS transistor M10, the first resistor R1, the second resistor R2, and the third resistor R3, and the other end is connected to the capacitor C; one end of the capacitor C is connected to the sixth resistor. R6, the other end is grounded.
这里,所述第一NMOS管M1、第二NMOS管M2、第一PMOS管M3、第二PMOS管M4、第三PMOS管M5、第四PMOS管M6、第五PMOS管M7、第六PMOS管M8构成的电荷泵主电路为完全对称的结构,该电荷泵主电路通过把PFD输出的充放电信号转化为对电荷泵输出电容的充放电电流,然后通过LPF转变为电压信号,从而对LCVCO进行控制,以实现PLL对相位和频率的跟踪,并产生稳定的时钟信号;第一NMOS管M1、第二NMOS管M2构成的第一支路在第一电压源VDD1的作用下,作为放电电流源,为电荷泵提供下拉电流,即为由第一PMOS管M3、第二PMOS管M4、第三PMOS管M5、第四PMOS管M6构成的第二支路提供放电电流;第一PMOS管M3、第二PMOS管M4、第三PMOS管M5、第四PMOS管M6作为电荷泵的输入端,接入PFD输出的充放电控制信号;但需要注意的是,第一NMOS管M1的宽长比应等于第二NMOS管M2的宽长比,第一PMOS管M3的宽长比与第二PMOS管的宽长比M4、第三PMOS管M5的宽长比、第四PMOS管M6的宽长比相等,第五PMOS管M7的宽长比等于第六PMOS管M8的宽长比。Here, the first NMOS transistor M1, the second NMOS transistor M2, the first PMOS transistor M3, the second PMOS transistor M4, the third PMOS transistor M5, the fourth PMOS transistor M6, the fifth PMOS transistor M7, and the sixth PMOS transistor The main circuit of the charge pump composed of M8 is a completely symmetrical structure. The charge pump main circuit converts the charge and discharge signals outputted by the PFD into a charge and discharge current to the charge pump output capacitor, and then converts it into a voltage signal through the LPF, thereby performing LCVCO on the LCVCO. Controlling to achieve tracking of the phase and frequency of the PLL and generating a stable clock signal; the first branch formed by the first NMOS transistor M1 and the second NMOS transistor M2 acts as a discharge current source under the action of the first voltage source VDD1 Providing a pull-down current for the charge pump, that is, providing a discharge current by the second branch formed by the first PMOS transistor M3, the second PMOS transistor M4, the third PMOS transistor M5, and the fourth PMOS transistor M6; the first PMOS transistor M3, The second PMOS transistor M4, the third PMOS transistor M5, and the fourth PMOS transistor M6 serve as input terminals of the charge pump, and are connected to the charge and discharge control signals of the PFD output; however, it should be noted that the width to length ratio of the first NMOS transistor M1 should be Equal to the aspect ratio of the second NMOS transistor M2, the aspect ratio of the first PMOS transistor M3 and the second P The width-to-length ratio of the MOS transistor is equal to the width-to-length ratio of the third PMOS transistor M5 and the width and length ratio of the fourth PMOS transistor M6, and the width-to-length ratio of the fifth PMOS transistor M7 is equal to the aspect ratio of the sixth PMOS transistor M8.
图3中,UP与UPB、DN与DNB为PFD输出的两对差分输入控制信号,用于控制电荷泵的充放电;VOUTP和VOUTN为差分输出电压,而输出差分信号为VOUT=VOUTP-VOUTN。当UP=DN时,电荷泵处于共模保持状态,即VOUT=0;当UP=1,DN=0时,电荷泵为充电状态,即VOUT上升;当UP=0,DN=1时,电荷泵为放电状态,即VOUT下降。其中,UP、DN的差分信号UPB、DNB分别控制第二PMOS管M4、第三PMOS管M5,第二PMOS管M4、第三PMOS管M5的漏极交叉连接于VOUTP与VOUTN的输出节点,在充放电期间充分加快充放电的速度。本实施例中,以所述第一控制信号UP为充电控制信号、第四控制信号DN为放电控制信号、第二控制信号UPB为第一控制信号UP的差分信号、第三控制信号DNB为第四控制信号DN的差分信号为例进行说明。In Figure 3, UP and UPB, DN and DNB are two pairs of differential input control signals for PFD output, which are used to control the charge and discharge of the charge pump; VOUTP and VOUTN are differential output voltages, and the output differential signals are VOUT=VOUTP-VOUTN. When UP=DN, the charge pump is in the common mode hold state, that is, VOUT=0; when UP=1, DN=0, the charge pump is in the charging state, that is, VOUT rises; when UP=0, DN=1, the charge The pump is in a discharged state, that is, VOUT is lowered. The differential signals UPB and DNB of the UP and DN respectively control the second PMOS transistor M4 and the third PMOS transistor M5, and the drains of the second PMOS transistor M4 and the third PMOS transistor M5 are cross-connected to the output nodes of VOUTP and VOUTN. The charging and discharging speed is fully accelerated during charging and discharging. In this embodiment, the first control signal UP is the charging control signal, the fourth control signal DN is the discharging control signal, the second control signal UPB is the differential signal of the first control signal UP, and the third control signal DNB is the first The differential signal of the four control signals DN is taken as an example for description.
这里,由第一电阻R1、第二电阻R2、第三电阻R3、第三NMOS管M9、第四NMOS管M10、第五NMOS管M11、第七PMOS管M12、第八 PMOS管M13、第九PMOS管M14、第十PMOS管M15构成的共模反馈电路为电荷泵提供稳定的共模工作点,确保电荷泵工作的稳定性。其中,第三电阻R3以电阻分压的方式,使第四NMOS管M10的栅极获得的共模电压VCM大于电荷泵输出共模电压VCMOUT,其中,VCMOUT=(VOUTP+VOUTN)/2。需要注意的是,第一电阻R1的阻值应等于第二电阻R2的阻值;第三电压源VDD3的大小可需要根据实际情况比如第一电阻R1的阻值和电荷泵输出共模电压VCMOUT的大小等因素进行合理设置;第三NMOS管M9的宽长比等于第一NMOS管M1的宽长比;第七PMOS管M12的宽长比与第八PMOS管的宽长比、第九PMOS管的宽长比、第十PMOS管的宽长比相等;第四NMOS管M10的宽长比等于第五NMOS管M11的宽长比;第三NMOS管M9与第一NMOS管M1构成镜像关系,两者的宽长比相等,通过finger或M实现N倍镜像。Here, the first resistor R1, the second resistor R2, the third resistor R3, the third NMOS transistor M9, the fourth NMOS transistor M10, the fifth NMOS transistor M11, the seventh PMOS transistor M12, the eighth PMOS transistor M13, and the ninth The common mode feedback circuit formed by the PMOS transistor M14 and the tenth PMOS transistor M15 provides a stable common mode operating point for the charge pump, ensuring the stability of the charge pump operation. The third resistor R3 is divided by a resistor so that the common mode voltage VCM obtained by the gate of the fourth NMOS transistor M10 is greater than the charge pump output common mode voltage VCMOUT, where VCMOUT=(VOUTP+VOUTN)/2. It should be noted that the resistance of the first resistor R1 should be equal to the resistance of the second resistor R2; the magnitude of the third voltage source VDD3 may need to be based on actual conditions such as the resistance of the first resistor R1 and the charge pump output common mode voltage VCMOUT. The size and other factors are reasonably set; the width to length ratio of the third NMOS transistor M9 is equal to the width to length ratio of the first NMOS transistor M1; the aspect ratio of the seventh PMOS transistor M12 to the width to length ratio of the eighth PMOS transistor, and the ninth PMOS The width to length ratio of the tube and the width to length ratio of the tenth PMOS transistor are equal; the width to length ratio of the fourth NMOS transistor M10 is equal to the width to length ratio of the fifth NMOS transistor M11; and the third NMOS transistor M9 forms a mirror image relationship with the first NMOS transistor M1. The width and length ratios of the two are equal, and N times mirroring is achieved by finger or M.
这里,第四电阻R4的阻值与第五电阻R5的阻值可以相等,也可以不相等;所述第三电压源VDD3和第四电压源VDD4可以是同一个电压源,也可以是不同电压源,即所述第三电压源VDD3和第四电压源VDD4所提供的电压大小既可以相同,也可以不相同;在实际应用中,可根据实际需要选择大小合适的第三电压源VDD3和第四电压源VDD4。Here, the resistance of the fourth resistor R4 and the resistance of the fifth resistor R5 may be equal or not equal; the third voltage source VDD3 and the fourth voltage source VDD4 may be the same voltage source or different voltages. The source, that is, the voltages provided by the third voltage source VDD3 and the fourth voltage source VDD4 may be the same or different; in practical applications, the third voltage source VDD3 and the appropriate size may be selected according to actual needs. Four voltage source VDD4.
这里,电荷泵在正常工作时,当UP和DN之间相互保持平衡状态时,电荷泵输出共模电压VCMOUT保持稳定,使得第四NMOS管M10的栅极的输入电压VCM等于第五NMOS管M11的栅极的输入电压VB即电压偏置电路提供的共模偏置电压,此时,共模反馈电路所产生的反馈电压信号VFB不会调节第五PMOS管M7、第六PMOS管M8输出的充电电流,即保持差分输出电压VOUTP、VOUTN之间的平衡;当因UP和DN的变化而导致差分输出电压VOUTP、VOUTN变化时,由于差分输出电压VOUTP、VOUTN变化相应的会使得第四NMOS管M10的栅极的输入电压VCM发生变化,而第五NMOS管M11的栅极的输入电压VB是稳定不变的,这将导致第四NMOS管M10的栅极的输入电压VCM与第五NMOS管M11的栅极的输入电压VB之间失衡,则会使共模反馈电路将VCM的变化通过反馈电压信号VFB输出给电荷泵主电路,以使电荷泵主电路调节第五PMOS管M7、第六PMOS管M8的充电电流,改变差分输出电压VOUTP、 VOUTN,以重新使第四NMOS管M10的栅极的输入电压VCM等于第五NMOS管M11的栅极的输入电压VB。Here, when the charge pump is in normal operation, when the UP and DN are in equilibrium with each other, the charge pump output common mode voltage VCMOUT remains stable, so that the input voltage VCM of the gate of the fourth NMOS transistor M10 is equal to the fifth NMOS transistor M11. The input voltage VB of the gate is the common mode bias voltage provided by the voltage bias circuit. At this time, the feedback voltage signal VFB generated by the common mode feedback circuit does not adjust the output of the fifth PMOS transistor M7 and the sixth PMOS transistor M8. The charging current, that is, maintains the balance between the differential output voltages VOUTP and VOUTN; when the differential output voltages VOUTP and VOUTN change due to changes in UP and DN, the fourth NMOS transistor is caused by the differential output voltages VOUTP and VOUTN. The input voltage VCM of the gate of M10 changes, and the input voltage VB of the gate of the fifth NMOS transistor M11 is stable, which will cause the input voltage VCM of the gate of the fourth NMOS transistor M10 and the fifth NMOS transistor. The imbalance between the input voltage VB of the gate of M11 causes the common mode feedback circuit to output the VCM change to the charge pump main circuit through the feedback voltage signal VFB, so that the charge pump main circuit adjusts the fifth PMOS transistor M7, sixth. PMOS M8 charging current, changing the differential output voltage VOUTP, VOUTN, to re-enable gate input of the fourth NMOS transistor M10 is equal to the gate voltage VCM fifth NMOS transistor M11 of the input voltage VB.
本实施中,第一NMOS管M1、第二NMOS管M2、第一PMOS管M3、第二PMOS管M4、第三PMOS管M5、第四PMOS管M6、第五PMOS管M7、第六PMOS管M8构成的电荷泵主电路将差分输入控制信号对UP与UPB、DN与DNB转化为差分输出信号VOUTP和VOUTN,第一电阻R1、第二电阻R2、第三电阻R3、第三NMOS管M9、第四NMOS管M10、第五NMOS管M11、第七PMOS管M12、第八PMOS管M13、第九PMOS管M14、第十PMOS管M15构成的共模反馈电路根据差分输出信号VOUTP和VOUTN获取待检测电压即第四NMOS管M10的栅极的输入电压VCM,将VCM的变化转化为反馈电压信号VFB反馈给电荷泵主电路进行共模调节,以使得差分输出信号既具有较高的稳定性,又具有很好的匹配性。本实施例提供的电荷泵可以被应用于锁相环电路、时钟数据恢复电路、存储器电路读入/读出电路等集成电路中。In this implementation, the first NMOS transistor M1, the second NMOS transistor M2, the first PMOS transistor M3, the second PMOS transistor M4, the third PMOS transistor M5, the fourth PMOS transistor M6, the fifth PMOS transistor M7, and the sixth PMOS transistor The charge pump main circuit composed of M8 converts the differential input control signal pair UP and UPB, DN and DNB into differential output signals VOUTP and VOUTN, and the first resistor R1, the second resistor R2, the third resistor R3, and the third NMOS transistor M9. The common mode feedback circuit formed by the fourth NMOS transistor M10, the fifth NMOS transistor M11, the seventh PMOS transistor M12, the eighth PMOS transistor M13, the ninth PMOS transistor M14, and the tenth PMOS transistor M15 is obtained according to the differential output signals VOUTP and VOUTN. The detection voltage is the input voltage VCM of the gate of the fourth NMOS transistor M10, and the change of the VCM is converted into the feedback voltage signal VFB and fed back to the main circuit of the charge pump for common mode adjustment, so that the differential output signal has high stability. It also has a good match. The charge pump provided in this embodiment can be applied to an integrated circuit such as a phase locked loop circuit, a clock data recovery circuit, a memory circuit read/write circuit, or the like.
实施例二Embodiment 2
图4为本申请实施例二提供的锁相环电路的组成结构示意图,该锁相环电路包括:电荷泵1、鉴频鉴相器2、低通滤波器3、压控振荡器4;其中,4 is a schematic structural diagram of a phase-locked loop circuit according to Embodiment 2 of the present application. The phase-locked loop circuit includes: a charge pump 1, a phase frequency detector, a low-pass filter 3, and a voltage-controlled oscillator 4; ,
所述鉴频鉴相器2,配置为比较输入的基准信号和所述压控振荡器4的输出信号,生成比较结果;The phase frequency detector 2 is configured to compare the input reference signal with the output signal of the voltage controlled oscillator 4 to generate a comparison result;
所述电荷泵1,配置为根据所述鉴频鉴相器2的比较结果调整输出电压;The charge pump 1 is configured to adjust an output voltage according to a comparison result of the phase frequency detector 2;
所述低通滤波器3,配置为对所述电荷泵1的输出电压进行滤波;The low pass filter 3 is configured to filter an output voltage of the charge pump 1;
压控振荡器4,配置为根据所述低通滤波器3滤波后的输出电压调整输出信号的频率。The voltage controlled oscillator 4 is configured to adjust the frequency of the output signal in accordance with the output voltage filtered by the low pass filter 3.
这里,图4所示的锁相环电路的工作原理为:当所述鉴频鉴相器2检测出所述压控振荡器4的输出信号的频率小于所述基准信号的频率时,所述电荷泵1升高所述电荷泵1的输出电压,所述输出电压经过所述低通滤波器3进行滤波后输出直流电压部分,所述压控振荡器4的输出信号的频 率在所述升高后的电压的控制下提高输出信号的频率。反之,当所述鉴频鉴相器2检测出所述压控振荡器4的输出信号的频率大于所述基准信号的频率时,所述电荷泵1降低所述电荷泵1的输出电压,经过滤波后,所述压控振荡器4根据降低的电压降低输出信号的频率;经过反复调整,直至所述压控振荡器4的输出信号的频率等于所述基准信号的频率时,所述压控振荡器4的输出信号被锁定。Here, the phase-locked loop circuit shown in FIG. 4 operates on the principle that when the phase frequency detector 2 detects that the frequency of the output signal of the voltage-controlled oscillator 4 is less than the frequency of the reference signal, The charge pump 1 raises an output voltage of the charge pump 1, and the output voltage is filtered by the low-pass filter 3 to output a DC voltage portion, and the frequency of the output signal of the voltage controlled oscillator 4 is at the rise The frequency of the output signal is increased under the control of the high voltage. On the contrary, when the phase frequency detector 2 detects that the frequency of the output signal of the voltage controlled oscillator 4 is greater than the frequency of the reference signal, the charge pump 1 lowers the output voltage of the charge pump 1, after After filtering, the voltage controlled oscillator 4 reduces the frequency of the output signal according to the reduced voltage; after repeated adjustments until the frequency of the output signal of the voltage controlled oscillator 4 is equal to the frequency of the reference signal, the voltage control The output signal of the oscillator 4 is locked.
这里,在所述鉴频鉴相器2的两个输入信号中,所述压控振荡器4的输出信号可以是对所述压控振荡器4所输出的信号进行分频后所获得的信号;所述电荷泵1可以是上述实施例一中任意一种电荷泵。Here, in the two input signals of the phase frequency detector 2, the output signal of the voltage controlled oscillator 4 may be a signal obtained by dividing a signal output by the voltage controlled oscillator 4 The charge pump 1 may be any one of the above-described first embodiment.
本申请实施例提供的一种存储介质,存储有计算机可执行指令,所述计算机可执行指令被执行时实现上述实施例任意一项所述的基于电荷泵的处理方法。A storage medium provided by an embodiment of the present application stores a computer executable instruction, and when the computer executable instruction is executed, the charge pump based processing method according to any one of the above embodiments is implemented.
以上所述,仅为本申请的较佳实施例而已,并非用于限定本申请的保护范围。凡在本申请的精神和范围之内所作的任何修改、等同替换和改进等,均包含在本申请的保护范围之内。The above is only the preferred embodiment of the present application and is not intended to limit the scope of the present application. Any modifications, equivalent substitutions and improvements made within the spirit and scope of the present application are included in the scope of the present application.
采用本申请实施例,电荷泵通过将差分输出电压的变化转化为反馈电压信号,以基于所述反馈电压信号调节输出的差分输出电压,能够保证电荷泵在低电压环境下产生具有较高稳定性和匹配性的差分输出电压。With the embodiment of the present application, the charge pump can ensure the high stability of the charge pump in a low voltage environment by converting the differential output voltage into a feedback voltage signal to adjust the output differential output voltage based on the feedback voltage signal. And matching differential output voltage.
Claims (17)
- 一种电荷泵,所述电荷泵包括:电荷泵主电路、共模反馈电路、电压偏置电路;其中,A charge pump includes: a charge pump main circuit, a common mode feedback circuit, and a voltage bias circuit; wherein所述电荷泵主电路,配置为利用输入的差分控制信号,产生电荷泵的差分输出电压;The charge pump main circuit is configured to generate a differential output voltage of the charge pump by using the input differential control signal;所述共模反馈电路,配置为基于所述差分输出电压和所述电压偏置电路提供的共模偏置电压,生成反馈电压信号,并将所述反馈电压信号输出至所述电荷泵主电路,以基于所述反馈电压信号调整所述电荷泵主电路产生的差分输出电压的共模电压。The common mode feedback circuit is configured to generate a feedback voltage signal based on the differential output voltage and a common mode bias voltage provided by the voltage bias circuit, and output the feedback voltage signal to the charge pump main circuit And adjusting a common mode voltage of the differential output voltage generated by the charge pump main circuit based on the feedback voltage signal.
- 根据权利要求1所述的电荷泵,其中,所述电荷泵还包括:零点补偿电路,配置为对所述共模反馈电路的相位进行补偿。The charge pump of claim 1 wherein said charge pump further comprises: a zero point compensation circuit configured to compensate for a phase of said common mode feedback circuit.
- 根据权利要求1或2所述的电荷泵,其中,所述电荷泵主电路包括第一支路、与所述第一支路连接的第二支路、与所述第二支路连接的第三支路;其中,The charge pump according to claim 1 or 2, wherein said charge pump main circuit includes a first branch, a second branch connected to said first branch, and a second branch connected to said second branch Three branches; among them,所述第一支路,作为放电电流源,配置为为所述第二支路提供放电电流;The first branch, as a discharge current source, is configured to provide a discharge current for the second branch;所述第三支路,作为充电电流源,配置为为所述第二支路提供充电电流;以及,接收所述共模反馈电路输出的反馈电压信号,调整所述充电电流;The third branch, as a charging current source, is configured to provide a charging current for the second branch; and receive a feedback voltage signal output by the common mode feedback circuit to adjust the charging current;所述第二支路,配置为根据输入的差分控制信号、充电电流和放电电流,确定电荷泵的差分输出电压。The second branch is configured to determine a differential output voltage of the charge pump based on the input differential control signal, the charging current, and the discharging current.
- 根据权利要求3所述的电荷泵,其中,所述共模反馈电路包括第四支路、第五支路;其中,The charge pump according to claim 3, wherein said common mode feedback circuit comprises a fourth branch and a fifth branch; wherein所述第四支路,配置为基于所述差分输出电压,利用电阻分压的方式,获取待检测电压;所述待检测电压大于所述差分输出电压之和的一半;The fourth branch is configured to acquire a voltage to be detected by means of a resistor divider according to the differential output voltage; the voltage to be detected is greater than a half of a sum of the differential output voltages;所述第五支路,配置为比较所述待检测电压和所述电压偏置电路提供的共模偏置电压,根据比较结果产生反馈电压信号,并将所述反馈电压信 号输出给所述电荷泵主电路。The fifth branch is configured to compare the to-be-detected voltage and a common mode bias voltage provided by the voltage bias circuit, generate a feedback voltage signal according to the comparison result, and output the feedback voltage signal to the charge Pump main circuit.
- 根据权利要求4所述的电荷泵,其中,The charge pump according to claim 4, wherein所述第一支路包括第一NMOS管、第二NMOS管,所述第二支路包括第一PMOS管、第二PMOS管、第三PMOS管、第四PMOS管,所述第三支路包括第五PMOS管、第六PMOS管;The first branch includes a first NMOS transistor and a second NMOS transistor, and the second branch includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor, and the third branch The fifth PMOS transistor and the sixth PMOS transistor are included;第一NMOS管的栅极连接第二NMOS管的栅极、且第一NMOS管的栅极和第二NMOS管的栅极都连接第一电压源,第一NMOS管的源极、第二NMOS管的源极接地;第一NMOS管的漏极连接第一PMOS管的漏极和第三PMOS管的漏极;第二NMOS管的漏极连接第二PMOS管的漏极和第四PMOS管的漏极;第一PMOS管的栅极接入第一控制信号,第一PMOS管的源极连接第二PMOS管的源极、且第一PMOS管的源极和第二PMOS管的源极都连接第五PMOS管的漏极;第二PMOS管的栅极接入第二控制信号;第三PMOS管的栅极接入第三控制信号,第三PMOS管的源极连接第四PMOS管的源极、且第三PMOS管的源极和第四PMOS管的源极都连接第六PMOS管的漏极;第四PMOS管的栅极接入第四控制信号;第五PMOS管的源极、第六PMOS管的源极连接第二电压源,第五PMOS管的栅极连接第六PMOS管的栅极;所述第一控制信号、第二控制信号、第三控制信号和第四控制信号为所述输入的差分控制信号;所述第二控制信号为所述第一控制信号的差分信号;所述第四控制信号为所述第三控制信号的差分信号。The gate of the first NMOS transistor is connected to the gate of the second NMOS transistor, and the gate of the first NMOS transistor and the gate of the second NMOS transistor are connected to the first voltage source, the source of the first NMOS transistor, and the second NMOS. The source of the tube is grounded; the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor and the drain of the third PMOS transistor; the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor and the fourth PMOS transistor The drain of the first PMOS transistor is connected to the first control signal, the source of the first PMOS transistor is connected to the source of the second PMOS transistor, and the source of the first PMOS transistor and the source of the second PMOS transistor Connected to the drain of the fifth PMOS transistor; the gate of the second PMOS transistor is connected to the second control signal; the gate of the third PMOS transistor is connected to the third control signal, and the source of the third PMOS transistor is connected to the fourth PMOS transistor The source, the source of the third PMOS transistor and the source of the fourth PMOS transistor are both connected to the drain of the sixth PMOS transistor; the gate of the fourth PMOS transistor is connected to the fourth control signal; the source of the fifth PMOS transistor a source of the sixth PMOS transistor is connected to the second voltage source, and a gate of the fifth PMOS transistor is connected to a gate of the sixth PMOS transistor; the first control signal, the second control signal, and the third control signal And a fourth control signal is input to the differential control signal; a second control signal is a differential signal of said first control signal; said fourth control signal to a differential signal of the third control signal.
- 根据权利要求5所述的电荷泵,其中,The charge pump according to claim 5, wherein所述第四支路包括第一电阻、第二电阻、第三电阻,所述第五支路包括第三NMOS管、第四NMOS管、第五NMOS管、第七PMOS管、第八PMOS管、第九PMOS管、第十PMOS管;The fourth branch includes a first resistor, a second resistor, and a third resistor, and the fifth branch includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor , a ninth PMOS tube, a tenth PMOS tube;第一电阻的一端连接第一NMOS管的漏极、第一PMOS管的漏极和第三PMOS管的漏极,另一端连接第二电阻;第二电阻一端连接第二NMOS管的漏极、第二PMOS管的漏极和第四PMOS管的漏极,另一端连接第一电阻;第三电阻的一端连接第四NMOS管的栅极、第一电阻和第二电阻,另一端连接第三电压源;第三NMOS管的漏极连接第四NMOS管的源极和 第五NMOS管的源极,第三NMOS管的栅极连接第一电压源,第三NMOS管的源极接地;第七PMOS管的栅极连接第八PMOS管的栅极,第七PMOS管的漏极连接第七PMOS管的栅极、第八PMOS管的栅极、第九PMOS管的漏极、第四NMOS管的漏极;第十PMOS管的栅极连接第九PMOS管的栅极,第十PMOS管的漏极连接第十PMOS管的栅极、第九PMOS管的栅极、第八PMOS管的漏极、第五NMOS管的漏极、第五PMOS管的栅极、第六PMOS管的栅极;第七PMOS管的源极、第八PMOS管的源极、第九PMOS管的源极、第十PMOS管的源极都连接第二电压源。One end of the first resistor is connected to the drain of the first NMOS transistor, the drain of the first PMOS transistor and the drain of the third PMOS transistor, and the other end is connected to the second resistor; one end of the second resistor is connected to the drain of the second NMOS transistor, a drain of the second PMOS transistor and a drain of the fourth PMOS transistor, and the other end is connected to the first resistor; one end of the third resistor is connected to the gate of the fourth NMOS transistor, the first resistor and the second resistor, and the other end is connected to the third a voltage source; a drain of the third NMOS transistor is connected to a source of the fourth NMOS transistor and a source of the fifth NMOS transistor, a gate of the third NMOS transistor is connected to the first voltage source, and a source of the third NMOS transistor is grounded; The gate of the seventh PMOS transistor is connected to the gate of the eighth PMOS transistor, and the drain of the seventh PMOS transistor is connected to the gate of the seventh PMOS transistor, the gate of the eighth PMOS transistor, the drain of the ninth PMOS transistor, and the fourth NMOS. The drain of the tube; the gate of the tenth PMOS transistor is connected to the gate of the ninth PMOS transistor, and the drain of the tenth PMOS transistor is connected to the gate of the tenth PMOS transistor, the gate of the ninth PMOS transistor, and the eighth PMOS transistor a drain, a drain of the fifth NMOS transistor, a gate of the fifth PMOS transistor, a gate of the sixth PMOS transistor, a source of the seventh PMOS transistor, a source of the eighth PMOS transistor, and a ninth The source of the PMOS transistor and the source of the tenth PMOS transistor are all connected to the second voltage source.
- 根据权利要求6所述的电荷泵,其中,The charge pump according to claim 6, wherein所述电压偏置电路包括第四电阻、第五电阻;The voltage bias circuit includes a fourth resistor and a fifth resistor;第四电阻的一端连接第五NMOS管的栅极和第五电阻,另一端连接第四电压源;第五电阻一端连接第五NMOS管的栅极和第四电阻,另一端接地。One end of the fourth resistor is connected to the gate of the fifth NMOS transistor and the fifth resistor, and the other end is connected to the fourth voltage source; one end of the fifth resistor is connected to the gate of the fifth NMOS transistor and the fourth resistor, and the other end is grounded.
- 根据权利要求6或7所述的电荷泵,其中,所述零点补偿电路包括第六电阻、电容;The charge pump according to claim 6 or 7, wherein the zero point compensation circuit comprises a sixth resistor and a capacitor;第六电阻的一端连接第四NMOS管的栅极、第一电阻、第二电阻、第三电阻,另一端连接电容;电容一端连接第六电阻,另一端接地。One end of the sixth resistor is connected to the gate of the fourth NMOS transistor, the first resistor, the second resistor, and the third resistor, and the other end is connected to the capacitor; one end of the capacitor is connected to the sixth resistor, and the other end is grounded.
- 根据权利要求6所述的电荷泵,其中,所述第一电阻的阻值等于所述第二电阻的阻值。The charge pump of claim 6, wherein the resistance of the first resistor is equal to the resistance of the second resistor.
- 根据权利要求6所述的电荷泵,其中,The charge pump according to claim 6, wherein所述第一NMOS管的宽长比等于所述第二NMOS管的宽长比;所述第三NMOS管的宽长比等于所述第一NMOS管的宽长比;所述第四NMOS管的宽长比等于第五NMOS管的宽长比;a width to length ratio of the first NMOS transistor is equal to a width to length ratio of the second NMOS transistor; a width to length ratio of the third NMOS transistor is equal to a width to length ratio of the first NMOS transistor; and the fourth NMOS transistor The width to length ratio is equal to the width to length ratio of the fifth NMOS transistor;所述第一PMOS管的宽长比与第二PMOS管的宽长比、第三PMOS管的宽长比、第四PMOS管的宽长比相等;所述第五PMOS管的宽长比等于第六PMOS管的宽长比;所述第七PMOS管的宽长比与第八PMOS管的宽长比、第九PMOS管的宽长比、第十PMOS管的宽长比相等。The aspect ratio of the first PMOS transistor is equal to the aspect ratio of the second PMOS transistor, the aspect ratio of the third PMOS transistor, and the width to length ratio of the fourth PMOS transistor; the width to length ratio of the fifth PMOS transistor is equal to a width to length ratio of the sixth PMOS transistor; a width to length ratio of the seventh PMOS transistor is equal to a width to length ratio of the eighth PMOS transistor, a width to length ratio of the ninth PMOS transistor, and a width to length ratio of the tenth PMOS transistor.
- 一种基于电荷泵的处理方法,所述方法包括:A charge pump based processing method, the method comprising:利用输入的差分控制信号,产生电荷泵的差分输出电压;Using the input differential control signal to generate a differential output voltage of the charge pump;基于所述差分输出电压和共模偏置电压,生成反馈电压信号;Generating a feedback voltage signal based on the differential output voltage and the common mode bias voltage;根据所述反馈电压信号调整所述差分输出电压的共模电压。Adjusting a common mode voltage of the differential output voltage according to the feedback voltage signal.
- 根据权利要求11所述的方法,其中,所述方法还包括:The method of claim 11 wherein the method further comprises:根据所述差分输出电压、所述共模偏置电压、所述反馈电压信号和所述差分输出电压的共模电压得到反馈函数;And obtaining a feedback function according to the differential output voltage, the common mode bias voltage, the feedback voltage signal, and a common mode voltage of the differential output voltage;在所述反馈函数中引入零点,进行相位补偿。A zero point is introduced in the feedback function to perform phase compensation.
- 根据权利要求11或12所述的方法,其中,所述利用输入的差分控制信号,产生电荷泵的差分输出电压,包括:The method of claim 11 or 12, wherein said generating a differential output voltage of the charge pump using the input differential control signal comprises:根据输入的差分控制信号、充电电流和放电电流源产生的放电电流,确定电荷泵的差分输出电压;所述充电电流包括根据所述反馈电压信号对充电电流源产生的充电电流进行调整后得到的电流。Determining a differential output voltage of the charge pump according to the input differential control signal, the charging current, and the discharge current generated by the discharge current source; the charging current includes: adjusting the charging current generated by the charging current source according to the feedback voltage signal Current.
- 根据权利要求11所述的方法,其中,所述基于所述差分输出电压和共模偏置电压,生成反馈电压信号,包括:The method of claim 11 wherein said generating a feedback voltage signal based on said differential output voltage and a common mode bias voltage comprises:基于所述差分输出电压,利用电阻分压的方式,获取待检测电压;所述待检测电压大于所述差分输出电压之和的一半;And obtaining, according to the differential output voltage, a voltage to be detected by using a voltage division method; the voltage to be detected is greater than a half of a sum of the differential output voltages;比较所述待检测电压和所述共模偏置电压,根据比较结果产生反馈电压信号。The voltage to be detected and the common mode bias voltage are compared, and a feedback voltage signal is generated according to the comparison result.
- 一种锁相环电路,所述锁相环电路包括:鉴频鉴相器、与所述鉴频鉴相器连接的电荷泵、与所述电荷泵连接的低通滤波器、与所述低通滤波器连接的压控振荡器;其中,A phase locked loop circuit, the phase locked loop circuit comprising: a frequency discrimination phase detector, a charge pump connected to the phase frequency detector, a low pass filter connected to the charge pump, and the low a voltage controlled oscillator connected to the pass filter; wherein所述电荷泵包括电荷泵主电路、共模反馈电路、电压偏置电路;The charge pump includes a charge pump main circuit, a common mode feedback circuit, and a voltage bias circuit;所述电荷泵主电路,配置为利用输入的差分控制信号,产生电荷泵的差分输出电压;The charge pump main circuit is configured to generate a differential output voltage of the charge pump by using the input differential control signal;所述共模反馈电路,配置为基于所述差分输出电压和所述电压偏置电路提供的共模偏置电压,生成反馈电压信号,并将所述反馈电压信号输出至所述电荷泵主电路,以基于所述反馈电压信号调整所述电荷泵主电路产 生的差分输出的共模电压。The common mode feedback circuit is configured to generate a feedback voltage signal based on the differential output voltage and a common mode bias voltage provided by the voltage bias circuit, and output the feedback voltage signal to the charge pump main circuit And adjusting a common mode voltage of the differential output generated by the charge pump main circuit based on the feedback voltage signal.
- 根据权利要求15所述的锁相环电路,其中,所述电荷泵具体为权利要求2至10任一项所述的电荷泵。The phase-locked loop circuit according to claim 15, wherein the charge pump is specifically the charge pump according to any one of claims 2 to 10.
- 一种存储介质,存储有计算机可执行指令,所述计算机可执行指令被执行时实现上述权利要求11-14任意一项所述的基于电荷泵的处理方法。A storage medium storing computer executable instructions that, when executed, implement the charge pump based processing method of any of the preceding claims 11-14.
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