CN110943738B - Inductance-capacitance voltage-controlled oscillator with adjustable output clock common mode voltage - Google Patents

Inductance-capacitance voltage-controlled oscillator with adjustable output clock common mode voltage Download PDF

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CN110943738B
CN110943738B CN201910977734.8A CN201910977734A CN110943738B CN 110943738 B CN110943738 B CN 110943738B CN 201910977734 A CN201910977734 A CN 201910977734A CN 110943738 B CN110943738 B CN 110943738B
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tube
circuit
voltage
current
mode voltage
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CN110943738A (en
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宋志杰
朱敏
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Elownipmicroelectronics Beijing Co ltd
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Elownipmicroelectronics Beijing Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

Abstract

The invention discloses an inductance capacitance voltage-controlled oscillator with adjustable common mode voltage of an output clock, which comprises: powerPad, bandgap circuit, LDO circuit, bias circuit and LCVCO circuit; the input end of the PowerPad is connected with an external power supply, and the output end of the PowerPad is connected with the input end of the band gap circuit, the input end of the LDO circuit and the source electrode of the oscillator current tube; the output end of the band gap circuit is connected with the input end of the LDO circuit; the output end of the LDO circuit is connected with the input end of the bias circuit; the input end of the bias circuit is connected with the first differential signal and the second differential signal, and the output end of the bias circuit is connected with the grid electrode of the oscillator current tube; the LCVCO circuit is connected with the drain electrode of the oscillator current tube. The invention can effectively reduce the phase noise of the inductance-capacitance voltage-controlled oscillator on the premise of not obviously increasing the power supply and the power consumption, and simultaneously adjust the common-mode voltage of the output clock of the oscillator, thereby ensuring that the power consumption and the area of the phase-locked loop meet the design requirements.

Description

Inductance-capacitance voltage-controlled oscillator with adjustable output clock common mode voltage
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to an inductance-capacitance voltage-controlled oscillator with an adjustable output clock common-mode voltage.
Background
Phase locked loops (phase locked loops, PLLs) are widely used in electronic design, and in radio frequency communication systems, phase Locked Loops (PLLs) are an extremely critical module that is widely used to provide stable frequencies to transceivers. The radio frequency phase-locked loop circuit is generally composed of a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider. Because of the better phase noise performance, inductance-capacitance voltage controlled oscillators (LCVCOs) are widely used in radio frequency Phase Locked Loop (PLL) circuits, where phase noise and oscillation starting speed are important performances of a phase locked loop, especially in low-jitter clock applications such as high-speed data transmission, VCO is a main contribution of noise, and noise performance directly affects jitter of a phase locked loop clock. How to ensure small area and low power consumption and reduce phase noise becomes the key of circuit design.
A conventional LCVCO circuit is shown in fig. 1, but how to reduce the LCVCO phase noise becomes a key in circuit design because noise present in the power supply and ground can be directly coupled into the circuit, resulting in poor VCO phase noise performance, which is a major contributor in the phase locked loop. One way to reduce phase noise is to power the LCVCO with an LDO, as shown in fig. 2, to isolate the noise on the power supply by the LDO, but since the LCVCO needs to draw a large current from the power supply when operating normally, using the LDO to power it increases the additional power consumption. Still another circuit for reducing phase noise by filtering, as shown in fig. 3, is that the current source introduces a significant amount of phase noise to the oscillator, and for a voltage controlled oscillator current source: 1) Thermal noise in the vicinity of the second harmonic causes phase noise; 2) Only the frequency of the second harmonic needs to have high impedance at the current source end; therefore, adding a narrow band circuit to the current source reduces the phase noise of the oscillator, as shown in fig. 2, C1 shorts the second harmonic noise to ground, and to increase the impedance, an inductor L3 is added between the current source and M1, M2, the inductor and the capacitor oscillating at the second harmonic. While this configuration can effectively reduce the phase noise of the oscillator, the inductance module is introduced at the same time, requiring a considerable increase in area.
Along with the increasing of the output clock frequency of the phase-locked loop, the swing amplitude is gradually reduced, and the temperature and the angle are changed, so that on the premise of ensuring the stable output frequency, how the follow-up circuit correctly recognizes the high and low levels of the output clock is also a design key, and in the traditional circuit, an additional shaping circuit is usually added at the output end of the oscillator to ensure the normal operation of the output clock, so that not only is the additional area increased, but also the additional power consumption is increased.
Disclosure of Invention
Aiming at the defects existing in the prior art, the invention aims to provide the inductance-capacitance voltage-controlled oscillator with the adjustable output clock common-mode voltage, which can effectively reduce the phase noise of the inductance-capacitance voltage-controlled oscillator on the premise of not obviously increasing the power supply and the power consumption, and simultaneously adjust the output clock common-mode voltage of the oscillator, thereby ensuring that the power consumption and the area of a phase-locked loop meet the design requirements.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
an lc voltage controlled oscillator with an adjustable output clock common mode voltage, the lc voltage controlled oscillator comprising: powerPad, bandgap circuit, LDO circuit, bias circuit and LCVCO circuit;
the input end of the PowerPad is connected with an external power supply, and the output end of the PowerPad is connected with the input end of the band gap circuit, the input end of the LDO circuit and the source electrode of the oscillator current tube;
the output end of the band gap circuit is connected with the input end of the LDO circuit;
the output end of the LDO circuit is connected with the input end of the bias circuit;
the input end of the bias circuit is connected with the first differential signal and the second differential signal, and the output end of the bias circuit is connected with the grid electrode of the oscillator current tube;
the LCVCO circuit is connected with the drain electrode of the oscillator current tube.
Further, an lc vco with an adjustable output clock common mode voltage as described above, the bias circuit comprising: the voltage dividing resistor R1, R2, the bias resistor R3, the RC filter resistor R4, the RC filter capacitor C1, the current mirror tube, the enabling tube NM6, the common mode voltage control tube NM5 and the input tube; the current mirror tube includes: NMOS tubes NM1 and NM2, NM3 and NM4, PMOS tubes PM1 and PM2, PM3 and PM4; the input tube includes: NMOS transistors NM7 and NM8;
the positive end of the R1 is connected with a power supply provided by the LDO circuit, and the negative end of the R1 is connected with the positive ends of the R2 and the R4; the positive end of R3 is connected with the power supply, and the negative end is connected with the grid electrode and the drain electrode of NM1 and the grid electrode of NM 2; the sources of the NM1, NM2, NM3 and NM4 are grounded, and the sources of the PM1, PM2, PM3 and PM4 are connected with a power supply; the drain electrode of the NM2 is connected with the source electrodes of the NM5, NM7 and NM8; the positive end of the C1 is connected with the negative end of the R4 and the grid electrode of the NM5, and the negative end is connected with the output end of the bias circuit; the grid electrode and the drain electrode of the PM1 are connected with the grid electrode of the PM2 and the drain electrode of the NM 5; the drain electrode of the PM2 is connected with the drain electrode and the grid electrode of the NM3 and the grid electrode of the NM 4; the drain electrode of the NM4 is connected with the source electrode of the NM6 and the output end of the bias circuit; the grid electrode of the PM3 is connected with the drain electrodes of the PM4, the NM7 and the NM8, and the drain electrode is connected with the drain electrode of the NM 6; the grid electrode and the drain electrode of the PM4 are connected with the grid electrode of the PM 3; the grid of NM6 is connected with an enable signal, the grid of NM7 is connected with the first differential signal, and the grid of NM8 is connected with the second differential signal.
Further, according to the inductor-capacitor voltage-controlled oscillator with the adjustable output clock common mode voltage, the oscillator current tube is a PMOS tube.
Further, in the lc vco with an adjustable output clock common mode voltage as described above, the enabling tube NM6 and the common mode voltage control tube NM5 are NMOS tubes.
Further, according to the inductor-capacitor voltage-controlled oscillator with the adjustable output clock common mode voltage, the LDO circuit is used for suppressing noise of an external power supply input by the PowerPad and providing the suppressed power supply for the bias circuit.
Further, an lc vco with an adjustable output clock common mode voltage as described above, the bias circuit is configured to:
the voltage of the accessed power supply is divided through the voltage dividing resistors R1 and R2, the divided voltage is supplied to the grid electrode of the common mode voltage control tube NM5 through an RC filter circuit formed by the R4 and the C1, the NM5 is conducted, and meanwhile, a high-frequency fluctuation signal in the divided voltage is filtered through the RC filter circuit.
Further, an lc vco with an adjustable output clock common mode voltage as described above, the bias circuit is configured to:
forming a current through the R3 and the NM1, mirroring the current into two branches of the NM2 through the NM1 and the NM2, enabling a part of the current flowing through the NM2 to flow into the NM5 and the PM1 respectively when the enabling signal is enabled, mirroring the current into the PM2 branch and the PM3 branch through the PM1 and the PM2, and mirroring the current to the output end of the bias circuit through the PM3 and the PM4; in the other, the other part of current flowing through the NM2 is mirrored to the output end of the bias circuit through the PM3 and PM4 after passing through the NM7, the NM8 and the PM4; and the voltage signal at the output end of the bias circuit is mirrored to provide bias voltage for the LCVCO circuit so as to reduce the phase noise of the inductance-capacitance voltage-controlled oscillator.
Further, the inductance-capacitance voltage-controlled oscillator with the adjustable output clock common-mode voltage is disclosed, and the bias circuit is also used for adjusting the output clock common-mode voltage.
Further, as described above, the lc vco with an adjustable output clock common mode voltage, the bias circuit is specifically configured to:
when the LCVCO circuit starts vibrating, the common mode voltage V1 of the first differential signal and the second differential signal generates an impedance R1 after passing through the NM7 and the NM8, the voltage V2 divided by the divider resistors R1 and R2 generates an impedance R2 after passing through the NM5, and if V1 is equal to V2, the current value flowing through the NM5 and the PM1 is the same as the current value flowing through the NM7, the NM8 and the PM4;
when V1 is smaller than V2, r1 is larger than r2, the current passing through the NM7, NM8 and PM4 is reduced, the current passing through the PM3 and PM4 after being mirrored is correspondingly reduced, the current passing through the PM5 and PM1 after being mirrored to the PM2 and NM3 is correspondingly increased, the current passing through the NM3 and NM4 after being mirrored is correspondingly increased, the output voltage of the output end of the bias circuit is reduced, and at the moment, the current of the oscillator current tube controlled by the output voltage is increased, and the common-mode voltage V1 is improved until V1 and V2 are equal.
Further, as described above, the lc vco with an adjustable output clock common mode voltage, the bias circuit is specifically configured to:
when V1 is greater than V2, r1 is less than r2, the current passing through NM7, NM8, and PM4 increases, the current passing through the mirror images of PM3 and PM4 increases correspondingly, the current passing through PM5 and PM1 and mirror images of PM2 and NM3 decreases correspondingly, the current passing through the mirror images of NM3 and NM4 decreases correspondingly, the output voltage of the output end of the bias circuit increases, and at this time, the current of the oscillator current tube controlled by the output voltage decreases, and the common-mode voltage V1 decreases until V1 and V2 are equal.
The invention has the beneficial effects that: the invention can effectively reduce the phase noise of the inductance-capacitance voltage-controlled oscillator on the premise of not obviously increasing the power supply and the power consumption, and simultaneously adjust the common-mode voltage of the output clock of the oscillator, thereby ensuring that the power consumption and the area of the phase-locked loop meet the design requirements. The bias circuit is powered by the LDO, noise isolation is carried out by the LDO, noise introduced by the grid electrode of the current tube of the oscillator can be reduced, compared with a traditional structure in which the oscillator is directly powered by the LDO, the phase noise performance is not greatly different, and the power consumption is greatly reduced compared with that of the structure in which the oscillator is directly powered by the high-voltage power supply due to the fact that the power is still supplied by the low-voltage power supply.
Drawings
Fig. 1 is a circuit diagram of a conventional LC oscillator provided in an embodiment of the present invention;
FIG. 2 is a schematic diagram of an oscillator powered by an LDO according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an oscillator with LC filter structure according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an lc vco with an adjustable output clock common mode voltage according to an embodiment of the present invention;
fig. 5 is a schematic diagram of the structure of the bias circuit in fig. 4.
Detailed Description
The invention is described in further detail below with reference to the drawings and the detailed description.
Aiming at various technical problems mentioned in the background art, the invention provides a design method of an LCVCO bias circuit, which can effectively reduce the phase noise of an inductance-capacitance voltage controlled oscillator (LCVCO) on the premise that the power supply and the power consumption are not obviously increased, and simultaneously adjust the common-mode voltage of the output clock of the oscillator, thereby ensuring that the power consumption and the area of a phase-locked loop meet the design requirements.
As shown in fig. 4, an lc vco with an adjustable output clock common mode voltage, the lc vco includes: powerPad, bandgap circuit (BG), LDO circuit, bias circuit (Bias), and LCVCO circuit;
the input end of the PowerPad is connected with an external power supply, and the output end of the PowerPad is connected with the input end of the band gap circuit, the input end of the LDO circuit and the source electrode of the oscillator current tube;
the output end of the band gap circuit is connected with the input end of the LDO circuit;
the output end of the LDO circuit is connected with the input end of the bias circuit;
the input end of the bias circuit is connected with the first differential signal and the second differential signal, and the output end of the bias circuit is connected with the grid electrode of the oscillator current tube;
the LCVCO circuit is connected with the drain electrode of the oscillator current tube.
As shown in fig. 5, the bias circuit includes: the voltage dividing resistor R1, R2, the bias resistor R3, the RC filter resistor R4, the RC filter capacitor C1, the current mirror tube, the enabling tube NM6, the common mode voltage control tube NM5 and the input tube; the current mirror tube includes: NMOS tubes NM1 and NM2, NM3 and NM4, PMOS tubes PM1 and PM2, PM3 and PM4; the input tube includes: NMOS transistors NM7 and NM8;
the positive end of R1 is connected with the power supply provided by the LDO circuit, and the negative end is connected with the positive ends of R2 and R4; the positive end of R3 is connected with a power supply, and the negative end is connected with the grid electrode and the drain electrode of NM1 and the grid electrode of NM 2; the sources of NM1, NM2, NM3 and NM4 are grounded, and the sources of PM1, PM2, PM3 and PM4 are connected with a power supply; the drain electrode of NM2 is connected with the source electrodes of NM5, NM7 and NM8; the positive end of C1 is connected with the negative end of R4 and the grid electrode of NM5, and the negative end is connected with the output end of the bias circuit; the grid electrode and the drain electrode of PM1 are connected with the grid electrode of PM2 and the drain electrode of NM 5; the drain electrode of PM2 is connected with the drain electrode and the grid electrode of NM3 and the grid electrode of NM 4; the drain electrode of NM4 is connected with the source electrode of NM6 and the output end of the bias circuit; the grid electrode of PM3 is connected with the drain electrodes of PM4, NM7 and NM8, and the drain electrode is connected with the drain electrode of NM 6; the grid electrode and the drain electrode of PM4 are connected with the grid electrode of PM 3; the gate of NM6 is connected to the enable signal, the gate of NM7 is connected to the first differential signal, and the gate of NM8 is connected to the second differential signal.
The oscillator current tube is a PMOS tube.
The enable tube NM6 and the common mode voltage control tube NM5 are NMOS tubes.
The LDO circuit is used for suppressing noise of an external power supply input by the PowerPad and providing the suppressed power supply for the bias circuit.
The bias circuit is used for:
the voltage of the accessed power supply is divided through the voltage dividing resistors R1 and R2, the divided voltage is supplied with power to the grid electrode of the common mode voltage control tube NM5 through an RC filter circuit formed by R4 and C1, the NM5 is conducted, and meanwhile, high-frequency fluctuation signals in the divided voltage are filtered through the RC filter circuit.
The bias circuit is used for:
forming a current through R3 and NM1, mirroring the current into two branches of NM2 through NM1 and NM2, enabling a part of the current flowing through NM2 to flow into NM5 and PM1 respectively when enabling signals, mirroring the current into a PM2 branch and a PM3 branch through PM1 and PM2, and mirroring the current into an output end of a bias circuit through PM3 and PM4; in the other, the other part of current flowing through NM2 is mirrored to the output end of the bias circuit through PM3 and PM4 after passing through NM7, NM8 and PM4; the voltage signal at the output end of the bias circuit provides bias voltage for the LCVCO circuit after being mirrored, so as to reduce the phase noise of the inductance-capacitance voltage-controlled oscillator.
The bias circuit is also used to adjust the output clock common mode voltage.
The bias circuit is specifically used for:
when the LCVCO circuit starts vibrating, the common-mode voltage V1 of the first differential signal and the second differential signal generates impedance R1 after NM7 and NM8 are passed, the voltage V2 after the voltage division of the voltage dividing resistors R1 and R2 generates impedance R2 after NM5 is passed, and if V1 is equal to V2, the current value flowing through NM5 and PM1 is the same as the current value flowing through NM7, NM8 and PM4;
when V1 is smaller than V2, r1 is larger than r2, the current passing through NM7, NM8 and PM4 is reduced, the current passing through PM3 and PM4 after being mirrored is correspondingly reduced, the current passing through PM5 and PM1 after being mirrored to PM2 and NM3 is correspondingly increased, the current passing through NM3 and NM4 after being mirrored is correspondingly increased, the output voltage Vdriver at the output end of the bias circuit is reduced, the current of a PMOS tube (oscillator current tube) controlled by the output voltage Vdriver is increased, the common-mode voltage V1 is improved until V1 and V2 are equal, and at the moment, the common-mode signal is also adjusted to V2;
when V1 is greater than V2, r1 is less than r2, the current passing through NM7, NM8 and PM4 increases, the current passing through PM3 and PM4 after being mirrored increases correspondingly, the current passing through PM5 and PM1 after being mirrored to PM2 and NM3 decreases correspondingly, the current passing through NM3 and NM4 after being mirrored decreases correspondingly, the output voltage Vdriver at the output end of the bias circuit increases, the PMOS tube current controlled by the output voltage Vdriver decreases, the common mode voltage V1 decreases until V1 and V2 are equal, and at the moment, the common mode signal is also adjusted to V2.
The bias circuit of the invention supplies power through LDO (low dropout regulator, low dropout linear voltage regulator), noise isolation is carried out through LDO, noise introduced by the grid electrode of the tail current tube can be reduced, compared with the traditional structure of directly supplying power to the oscillator through LDO, the phase noise performance of the circuit structure is not greatly different, and the power consumption of the circuit structure is greatly reduced compared with the power consumption of directly supplying power from high voltage power supply because the circuit structure is also supplied with power by low voltage power supply.
On the basis of optimizing the phase noise of an oscillator, the invention adds comparator circuits NM4, NM6 and PM3, the bias circuit outputs bias voltage to adjust the current of an oscillator current tube, differential voltage signals vco_m (first differential signal) and vco_p (first differential signal) after the oscillator starts vibrating are used as input signals to participate in the adjustment of the bias voltage signals output by the bias circuit, the common-mode voltage of the differential voltage signals vco_m and vco_p and the value of NM5 grid voltage are compared by the comparators, the bias voltage is adjusted, and the common-mode voltage of the vco_m and vco_p is ensured to be the value of NM5 grid voltage, wherein the NM5 grid voltage value can be adjusted by adjusting the resistance values of R1 and R2.
The design of the bias circuit reduces the phase noise of the oscillator on the premise of ensuring that the power consumption and the area are not additionally increased, and can effectively adjust the common-mode voltage value of the output clock so as to ensure the normal operation of the subsequent circuit. The invention is not limited to LC oscillators, and is also applicable to oscillators composed of partial tail current ring-tap structures.
As shown in fig. 4, the power supply of the whole oscillator is a low-voltage external power supply, and the external power supply supplies power to a BG (Band Gap) and an LDO circuit simultaneously, the BG supplies reference voltage to the LDO, the LDO supplies power to a bias circuit, and the bias circuit supplies bias voltage to the gate of a current tube of the oscillator.
Because the external power supply needs to supply power to different modules, the external power supply is inevitably coupled into a lot of noise, and therefore the power supply vreg_vp after noise suppression is provided for the bias circuit through the high power supply rejection ratio of the LDO.
The structure of the bias circuit is shown in fig. 5, the LDO is used as a power supply of the bias circuit, the high power supply of the LDO can be used for suppressing noise of an external power supply, the voltage is divided by resistors R1 and R2, the divided voltage is used for supplying power to the grid electrode of the NM5 tube through an RC low-pass filter circuit formed by R4 and C1, the voltage after the voltage division of R1 and R2 needs to be ensured to lead NM5 to be conducted, and meanwhile, the RC low-pass filter circuit can be used for filtering out high-frequency fluctuation of the divided voltage generated by R1 and R2; the power supply forms current through R3 and NM1, the current is mirrored into a NM2 branch circuit through NM1 and NM2 mirror images, the current is divided into two parts, when an enable signal EN is enabled, the current flowing through NM2 can flow into a NM5 branch circuit and a PM1 branch circuit respectively, then the current is mirrored into a PM2 branch circuit and a PM3 branch circuit through PM1 and PM2 mirror images, and the current is mirrored into a Vdriver signal (bias voltage signal) at an output end through mirror images PM3 and PM4; the other part of the current flowing through NM2 flows through NM7, NM8 and PM4 and then is mirrored to the Vdriver signal at the output end through PM3 and PM4 mirror tubes, and the Vdriver signal provides bias voltage for the oscillator current tube after being mirrored, so that the phase noise of the oscillator can be greatly reduced compared with the bias power supply for an external power supply.
The bias circuit provides a "clean" bias voltage and also has the effect of adjusting the common mode voltage of the output clock. When the oscillator starts vibrating, vco_m and vco_p are differential voltage signals, the impedance of the common mode voltage V1 after NM7 and NM8 is R1, and the impedance generated when the voltage value V2 after the voltage division of R1 and R2 acts on NM5 is R2. If v1=v2, the current flowing through NM5, PM1 and the current flowing through NM7, NM8, PM4 have the same value.
When V1 is smaller than V2, r1 is larger than r2, currents passing through NM7, NM8 and PM4 are relatively reduced, currents passing through PM3 and PM4 are correspondingly reduced, currents passing through PM5 and PM1 and being mirrored to PM2 and NM3 are correspondingly increased, currents passing through NM3 and NM4 are correspondingly increased, vdriver voltage is finally reduced, currents of a PMOS tube controlled by the Vdriver voltage are further increased, vco_m and vco_p common-mode voltage V1 are improved, and vco_m and vco_p common-mode voltage V1 are finally equal to a preset value V2; conversely, when the common mode voltages V1 of vco_m and vco_p are higher than the preset value V2, the Vdriver voltage is increased, and the common mode voltage of the output clock is reduced; finally, the common-mode voltage of the output clock is adjusted.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (9)

1. An lc vco with an adjustable output clock common mode voltage, the lc vco comprising: powerPad, bandgap circuit, LDO circuit, bias circuit and LCVCO circuit;
the input end of the PowerPad is connected with an external power supply, and the output end of the PowerPad is connected with the input end of the band gap circuit, the input end of the LDO circuit and the source electrode of the oscillator current tube;
the output end of the band gap circuit is connected with the input end of the LDO circuit;
the output end of the LDO circuit is connected with the input end of the bias circuit;
the input end of the bias circuit is connected with the first differential signal and the second differential signal, and the output end of the bias circuit is connected with the grid electrode of the oscillator current tube;
the LCVCO circuit is connected with the drain electrode of the oscillator current tube;
the bias circuit includes: the voltage dividing resistor R1, R2, the bias resistor R3, the RC filter resistor R4, the RC filter capacitor C1, the current mirror tube, the enabling tube NM6, the common mode voltage control tube NM5 and the input tube; the current mirror tube includes: NMOS tubes NM1 and NM2, NM3 and NM4, PMOS tubes PM1 and PM2, PM3 and PM4; the input tube includes: NMOS transistors NM7 and NM8;
the positive end of the resistor R1 is connected with a power supply provided by the LDO circuit, and the negative end of the resistor R2 is connected with the positive ends of the resistor R4; the positive end of the resistor R3 is connected with the power supply, and the negative end of the resistor R3 is connected with the grid electrode and the drain electrode of the NMOS tube NM1 and the grid electrode of the NMOS tube NM 2; the sources of the NMOS tubes NM1, NM2, NM3 and NM4 are grounded, and the sources of the PMOS tubes PM1, PM2, PM3 and PM4 are connected with a power supply; the drain electrode of the NMOS tube NM2 is connected with the common mode voltage control tube NM5 and the sources of NMOS tubes NM7 and NM8; the positive end of the capacitor C1 is connected with the negative end of the resistor R4 and the grid electrode of the common mode voltage control tube NM5, and the negative end is connected with the output end of the bias circuit; the grid electrode and the drain electrode of the PMOS tube PM1 are connected with the grid electrode of the PMOS tube PM2 and the drain electrode of the common mode voltage control tube NM 5; the drain electrode of the PM2 is connected with the drain electrode and the grid electrode of the NMOS tube NM3 and the grid electrode of the NMOS tube NM 4; the drain electrode of the NMOS tube NM4 is connected with the source electrode of the enabling tube NM6 and the output end of the bias circuit; the grid electrode of the PMOS tube PM3 is connected with the drain electrodes of the PM4 and NMOS tubes NM7 and NM8, and the drain electrode is connected with the drain electrode of the enabling tube NM 6; the grid electrode and the drain electrode of the PMOS tube PM4 are connected with the grid electrode of the PMOS tube PM 3; the gate of the enable tube NM6 is connected to an enable signal, the gate of the NMOS tube NM7 is connected to the first differential signal, and the gate of the NMOS tube NM8 is connected to the second differential signal.
2. The inductor-capacitor voltage controlled oscillator with an adjustable common mode voltage of an output clock according to claim 1, wherein the oscillator current tube is a PMOS tube.
3. An lc vco with an adjustable output clock common mode voltage as claimed in claim 1, wherein said enable tube NM6 and said common mode voltage control tube NM5 are NMOS tubes.
4. The lc vco of claim 1, wherein the LDO circuit is configured to reject noise from an external power supply input to the PowerPad and to provide the reject power to the bias circuit.
5. An lc vco with an adjustable output clock common mode voltage as claimed in claim 1, wherein said bias circuit is adapted to:
the voltage of the connected power supply is divided through the voltage dividing resistors R1 and R2, the divided voltage is supplied to the grid electrode of the common mode voltage control tube NM5 through an RC filter circuit formed by the resistor R4 and the capacitor C1, the common mode voltage control tube NM5 is conducted, and meanwhile, a high-frequency fluctuation signal in the divided voltage is filtered through the RC filter circuit.
6. An lc vco with an adjustable output clock common mode voltage as claimed in claim 1, wherein said bias circuit is adapted to:
forming current through the resistor R3 and the NMOS tube NM1, mirroring the current into two branches of the NMOS tube NM2 through the NMOS tube NM1 and the NMOS tube NM2, enabling a part of the current flowing through the NMOS tube NM2 to flow to the common mode voltage control tube NM5 and the PMOS tube PM1 respectively when the enabling signal is enabled, mirroring the current into the branch of the PMOS tube PM2 and the branch of the PMOS tube PM3 through the PMOS tubes PM1 and PM2, and mirroring the current into the output end of the bias circuit through the PMOS tubes PM3 and PM4; in the other one, the other part of current flowing through the NMOS tube NM2 is mirrored to the output end of the bias circuit through the PMOS tubes PM3 and PM4 after passing through the NMOS tubes NM7, NM8 and the PMOS tube PM4; and the voltage signal at the output end of the bias circuit is mirrored to provide bias voltage for the LCVCO circuit so as to reduce the phase noise of the inductance-capacitance voltage-controlled oscillator.
7. An lc vco with an adjustable output clock common mode voltage as claimed in claim 2, wherein said bias circuit is further adapted to adjust the output clock common mode voltage.
8. The lc vco of claim 7, wherein said bias circuit is specifically configured to:
when the LCVCO circuit starts vibrating, the common-mode voltage V1 of the first differential signal and the second differential signal passes through the NMOS transistors NM7 and NM8 to generate an impedance R1, the voltage V2 divided by the voltage dividing resistors R1 and R2 passes through the common-mode voltage control transistor NM5 to generate an impedance R2, and if V1 is equal to V2, the current value flowing through the common-mode voltage control transistor NM5 and the PMOS transistor PM1 is the same as the current value flowing through the NMOS transistors NM7, NM8 and the PMOS transistor PM4;
when V1 is smaller than V2, r1 is larger than r2, the current passing through the NMOS transistors NM7, NM8, and PM4 is reduced, the current passing through the PMOS transistors PM3 and PM4 after being mirrored is correspondingly reduced, the current passing through the PMOS transistors PM5 and PM1 and mirrored to the PMOS transistors PM2 and NM3 is correspondingly increased, the current passing through the NMOS transistors NM3 and NM4 after being mirrored is correspondingly increased, the output voltage of the output end of the bias circuit is reduced, and at the moment, the current of the oscillator current tube controlled by the output voltage is increased, and the common-mode voltage V1 is increased until V1 and V2 are equal.
9. The inductor capacitor voltage controlled oscillator of claim 8, wherein the bias circuit is specifically configured to:
when V1 is greater than V2, r1 is less than r2, the current passing through the NMOS transistors NM7, NM8 and the PMOS transistor PM4 increases, the current passing through the PMOS transistors PM3 and PM4 is correspondingly increased, the current passing through the PMOS transistors PM5 and PM1 and then being mirrored to the PMOS transistors PM2 and NM3 is correspondingly reduced, the current passing through the NMOS transistors NM3 and NM4 is correspondingly reduced, the output voltage of the output end of the bias circuit increases, and at the moment, the current of the oscillator current tube controlled by the output voltage decreases, the common-mode voltage V1 is reduced until V1 and V2 are equal.
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