CN110572151B - Phase-locked loop circuit - Google Patents
Phase-locked loop circuit Download PDFInfo
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- CN110572151B CN110572151B CN201910865849.8A CN201910865849A CN110572151B CN 110572151 B CN110572151 B CN 110572151B CN 201910865849 A CN201910865849 A CN 201910865849A CN 110572151 B CN110572151 B CN 110572151B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The embodiment of the invention discloses a phase-locked loop circuit. Comprising the following steps: the device comprises a phase frequency detector, a charge pump, a filter circuit, a voltage-current conversion circuit, a first capacitor, a voltage buffer unit, a second capacitor, a current mirror unit, a current control oscillator and a frequency divider; the phase frequency detector, the charge pump, the voltage-current conversion circuit, the current control oscillator and the frequency divider are connected in sequence; the filter circuit is connected between the first node and the grounding end; the first capacitor is connected between the second node and the grounding end; the input end of the voltage buffer unit is connected with the second node, and the input end of the voltage buffer unit is connected with one end of the second capacitor; the other end of the second capacitor is connected with the input end of the current mirror unit, and the output end of the current mirror unit output unit is connected with the second node. Voltage fluctuation caused by the oscillator can be reduced, so that jitter of an output clock of the phase-locked loop circuit is reduced.
Description
Technical Field
The embodiment of the invention relates to the technical field of circuits, in particular to a phase-locked loop circuit.
Background
With the development of wireless communication technology and integrated circuit technology, more and more wireless communication systems are integrated on a chip. The phase-locked loop can generate accurate clock signals or frequency signals, so that the phase-locked loop can be widely applied to clock generators, and in electronic systems such as wireless communication transceiver systems, clock/data recovery circuits and the like, the phase-locked loop-based frequency synthesizer can be widely applied to radio frequency transceiver systems. These demands have prompted the research and development of phase-locked loop circuits.
In the prior art, voltage fluctuation is caused by an oscillator in the phase-locked loop, so that clock jitter output by the phase-locked loop circuit is larger, and therefore, it is important to reduce the output jitter of the phase-locked loop.
Disclosure of Invention
The embodiment of the invention provides a phase-locked loop circuit which can reduce voltage fluctuation caused by an oscillator, thereby reducing jitter of an output clock of the phase-locked loop circuit.
In a first aspect, an embodiment of the present invention provides a phase-locked loop circuit, including: the device comprises a phase frequency detector, a charge pump, a filter circuit, a voltage-current conversion circuit, a first capacitor, a voltage buffer unit, a second capacitor, a current mirror unit, a current control oscillator and a frequency divider;
the phase frequency detector is provided with a reference signal input end and a feedback signal input end connected with the frequency divider; the phase frequency detector, the charge pump, the voltage-current conversion circuit, the current control oscillator and the frequency divider are connected in sequence;
the filter circuit is connected between the first node and the grounding end; wherein a first node is located between the charge pump and the voltage-to-current conversion circuit;
the first capacitor is connected between the second node and the grounding end; wherein a second node is located between the voltage-to-current conversion circuit and the current controlled oscillator;
the input end of the voltage buffer unit is connected with the second node, and the input end of the voltage buffer unit is connected with one end of the second capacitor; the other end of the second capacitor is connected with the input end of the current mirror unit, and the output end of the current mirror unit output unit is connected with the second node.
Further, the voltage-current conversion circuit comprises a first PMOS tube; the current controlled oscillator includes three inverters;
the grid electrode of the first PMOS tube is connected with the output end of the charge pump, the source electrode of the first PMOS tube is connected with a power supply, and the drain electrodes of the first PMOS tube are respectively connected with the input stages of the three inverters; the three inverters are connected in series in a mode that the middle stage is connected with the output stage; the second node is positioned between the drain electrode of the first PMOS tube and the input stages of the three inverters.
Further, the inverter comprises a PMOS tube and an NMOS tube.
Further, the filter circuit comprises a first resistor and a third capacitor;
one end of the first resistor is connected with the first node, and the other end of the first resistor is connected with one end of the third capacitor; the other end of the third capacitor is connected with the grounding end.
Further, the voltage buffer unit comprises two PMOS tubes, namely a second PMOS tube and a third PMOS tube;
the grid electrode of the second PMOS tube is connected with the first node, the source electrode of the second PMOS tube is connected with a power supply, and the drain electrode of the second PMOS tube is respectively connected with the source electrode of the third PMOS tube and one end of the second capacitor; and the grid electrode of the third PMOS tube is connected with the second node, and the drain electrode of the third PMOS tube is connected with the ground terminal.
Further, the current mirror unit comprises two PMOS tubes and two NMOS tubes; the first NMOS transistor is connected with the first PMOS transistor;
grid electrodes of the fourth PMOS tube and the fifth PMOS tube are connected with the first node, and source electrodes of the fourth PMOS tube and the fifth PMOS tube are connected with a power supply; the drain electrode of the fourth PMOS tube is connected with the drain electrode of the first NMOS tube; the drain electrode of the fifth PMOS tube is connected with the drain electrode of the second NMOS tube; the sources of the first NMOS tube and the second NMOS tube are connected with a grounding end; and the drain electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube.
Further, the other end of the second capacitor is connected with the drain electrode of the fourth PMOS tube.
The phase-locked loop circuit provided by the embodiment of the invention comprises a phase frequency detector, a charge pump, a filter circuit, a voltage-current conversion circuit, a first capacitor, a voltage buffer unit, a second capacitor, a current mirror image unit, a current control oscillator and a frequency divider; the first capacitor is connected between the second node and the grounding end; the second node is positioned between the voltage-current conversion circuit and the current control oscillator; the input end of the voltage buffer unit is connected with the second node, and the input end of the voltage buffer unit is connected with one end of the second capacitor; the other end of the second capacitor is connected with the input end of the current mirror unit, and the output end of the current mirror unit output unit is connected with the second node. Voltage fluctuation caused by the oscillator can be reduced, so that jitter of an output clock of the phase-locked loop circuit is reduced.
Drawings
Fig. 1 is a schematic diagram of a phase-locked loop circuit according to a first embodiment of the present invention;
fig. 2 is a schematic diagram of a current controlled oscillator according to a first embodiment of the present invention;
fig. 3 is a schematic diagram of a partial structure of a phase-locked loop circuit according to a first embodiment of the present invention;
fig. 4 is a schematic diagram of voltages and currents of nodes in a pll circuit according to a first embodiment of the invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Example 1
Fig. 1 is a schematic structural diagram of a pll circuit according to a first embodiment of the present invention, as shown in fig. 1, the pll circuit includes: the circuit comprises a phase frequency detector, a charge pump, a filter circuit, a voltage-current conversion circuit, a first capacitor, a voltage buffer unit, a second capacitor, a current mirror unit, a current control oscillator and a frequency divider.
The phase frequency detector is provided with a reference signal input end and a feedback signal input end connected with the frequency divider; the phase frequency detector, the charge pump, the voltage-current conversion circuit, the current control oscillator and the frequency divider are connected in sequence. The filter circuit is connected between the first node and the grounding end; wherein the first node is located between the charge pump and the voltage to current conversion circuit. The first capacitor is connected between the second node and the grounding end; wherein the second node is located between the voltage-to-current conversion circuit and the current controlled oscillator. The input end of the voltage buffer unit is connected with the second node, and the input end of the voltage buffer unit is connected with one end of the second capacitor; the other end of the second capacitor is connected with the input end of the current mirror unit, and the output end of the current mirror unit output unit is connected with the second node.
As shown in fig. 1, the filter circuit includes a first resistor and a third capacitor; one end of the first resistor is connected with the first node, and the other end of the first resistor is connected with one end of the third capacitor; the other end of the third capacitor is connected with the ground terminal.
Fig. 2 is a schematic diagram of a current controlled oscillator according to an embodiment of the present invention. As shown in fig. 2, the voltage-current conversion circuit includes a first PMOS transistor; the current controlled oscillator includes three inverters. The grid electrode of the first PMOS tube is connected with the output end of the charge pump, the source electrode of the first PMOS tube is connected with the power supply, and the drain electrodes of the first PMOS tube are respectively connected with the input stages of the three inverters. The three inverters are connected in series with the intermediate stage connected to the output stage. The second node is positioned between the drain electrode of the first PMOS tube and the input stages of the three inverters. In this embodiment, the inverter includes a PMOS transistor and an NMOS transistor.
Fig. 3 is a schematic diagram of a partial structure of a pll circuit according to an embodiment of the present invention, where, as shown in fig. 3, a voltage buffer unit includes two PMOS transistors, which are a second PMOS transistor and a third PMOS transistor, respectively. The grid electrode of the second PMOS tube is connected with the first node, the source electrode of the second PMOS tube is connected with the power supply, and the drain electrode of the second PMOS tube is respectively connected with the source electrode of the third PMOS tube and one end of the second capacitor; and the grid electrode of the third PMOS tube is connected with the second node, and the drain electrode of the third PMOS tube is connected with the ground terminal.
The current mirror unit comprises two PMOS tubes and two NMOS tubes; the first NMOS transistor is connected with the first PMOS transistor; the grid electrodes of the fourth PMOS tube and the fifth PMOS tube are connected with the first node, and the source electrodes are connected with the power supply; the drain electrode of the fourth PMOS tube is connected with the drain electrode of the first NMOS tube; the drain electrode of the fifth PMOS tube is connected with the drain electrode of the second NMOS tube; the source electrodes of the first NMOS tube and the second NMOS tube are connected with the grounding end; the drain electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube. The other end of the second capacitor is connected with the drain electrode of the fourth PMOS tube.
In this embodiment, the first node is voltage controlled and is implemented by a charge pump, a first resistor and a third capacitor, the first resistor and the third capacitor together form a zero and a pole of the loop, and the zero is located at
Wherein R is 1 A resistance value of the first resistor C 3 Is the capacitance value of the third capacitor. The pole is located at the origin. The first PMOS tube realizes the conversion from voltage to current. Assuming that the equivalent resistance of the current controlled oscillator is R2, R2 and the first capacitor form another pole of the loop, which pole is located +.>
Wherein C is 1 A capacitor which is a first capacitorValues. In this embodiment, to ensure loop stability, ω, of the current controlled oscillator p To be greater than omega z By a certain multiple. For example, to achieve a 60 degree phase margin, ω is to be satisfied p ＞8*ω z This requires that the value of C1 not be too large, so that the stabilizing effect of C1 on the voltage and current of the second node is limited.
In this embodiment, a voltage buffer unit, a second capacitor, and a current mirror unit are connected at the second node. Fig. 4 is a schematic diagram of voltages and currents of each node in the pll circuit according to the present embodiment. Each node comprises: a second node (node b), a voltage buffer unit output node (node c), and a current mirror unit input node (node d). As shown in fig. 4, when the equivalent resistance of the current controlled oscillator changes or the voltage of the second node changes due to other sudden causes, the voltage of the node c will change. If the voltage of the node d has upward or downward pulse, the second capacitor couples the pulse to the control end of the current mirror unit, so that the current mirror module is controlled to output a pulse current to the second node to compensate the current flowing to the current control oscillator, and the purpose of stabilizing the voltage of the second node is achieved. When the voltage of the second node changes in a step mode, the circuit only responds in a short time after the step time, and the normal working state of the circuit is not affected.
In the pll circuit of fig. 3, since the current flowing through the first PMOS transistor cannot be suddenly changed, the voltage of the second node is changed when each unit of the oscillator is turned on or off. The second PMOS transistor is a source follower, and a voltage increase at the second node causes a voltage increase at the node c. Since the voltage across the capacitor cannot jump, the voltage increase at node c also results in a voltage increase at node d. The second NMOS transistor is in the saturation region, and the voltage rise of the node d causes the current flowing through the second NMOS transistor to increase, and the reduced current in the oscillator is discharged through the second NMOS transistor, so that the voltage rise amplitude of the second node is reduced.
The equivalent capacitance of the third PMOS tube is far smaller than that of the second capacitor, and the capacitance value of the third PMOS tube after the third PMOS tube and the second PMOS tube are connected in series is approximately equal to that of the third PMOS tube, so that the poles and the zeros introduced by the added circuit do not influence the main poles and the zeros of the loop.
The phase-locked loop circuit provided by the embodiment comprises a phase frequency detector, a charge pump, a filter circuit, a voltage-current conversion circuit, a first capacitor, a voltage buffer unit, a second capacitor, a current mirror image unit, a current control oscillator and a frequency divider; the first capacitor is connected between the second node and the grounding end; the second node is positioned between the voltage-current conversion circuit and the current control oscillator; the input end of the voltage buffer unit is connected with the second node, and the input end of the voltage buffer unit is connected with one end of the second capacitor; the other end of the second capacitor is connected with the input end of the current mirror unit, and the output end of the current mirror unit output unit is connected with the second node. Voltage fluctuation caused by the oscillator can be reduced, so that jitter of an output clock of the phase-locked loop circuit is reduced.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (7)
1. A phase locked loop circuit comprising: the device comprises a phase frequency detector, a charge pump, a filter circuit, a voltage-current conversion circuit, a first capacitor, a voltage buffer unit, a second capacitor, a current mirror unit, a current control oscillator and a frequency divider;
the phase frequency detector is provided with a reference signal input end and a feedback signal input end connected with the frequency divider; the phase frequency detector, the charge pump, the voltage-current conversion circuit, the current control oscillator and the frequency divider are connected in sequence;
the filter circuit is connected between the first node and the grounding end; wherein a first node is located between the charge pump and the voltage-to-current conversion circuit;
the first capacitor is connected between the second node and the grounding end; wherein a second node is located between the voltage-to-current conversion circuit and the current controlled oscillator;
the input end of the voltage buffer unit is connected with the second node, and the output end of the voltage buffer unit is connected with one end of the second capacitor; the other end of the second capacitor is connected with the input end of the current mirror unit, and the output end of the current mirror unit is connected with the second node; when the voltage of the second node fluctuates, the voltage buffer unit can stabilize the voltage of the second node, and the normal working state of the circuit is not affected.
2. The circuit of claim 1, wherein the voltage to current conversion circuit comprises a first PMOS transistor; the current controlled oscillator includes three inverters;
the grid electrode of the first PMOS tube is connected with the output end of the charge pump, the source electrode of the first PMOS tube is connected with a power supply, and the drain electrodes of the first PMOS tube are respectively connected with the input stages of the three inverters; the three inverters are connected in series in a mode that the middle stage is connected with the output stage; the second node is positioned between the drain electrode of the first PMOS tube and the input stages of the three inverters.
3. The circuit of claim 2, wherein the inverter comprises a PMOS transistor and an NMOS transistor.
4. The circuit of claim 1, wherein the filter circuit comprises a first resistor and a third capacitor;
one end of the first resistor is connected with the first node, and the other end of the first resistor is connected with one end of the third capacitor; the other end of the third capacitor is connected with the grounding end.
5. The circuit of claim 1, wherein the voltage buffer unit comprises two PMOS transistors, a second PMOS transistor and a third PMOS transistor, respectively;
the grid electrode of the second PMOS tube is connected with the first node, the source electrode of the second PMOS tube is connected with a power supply, and the drain electrode of the second PMOS tube is respectively connected with the source electrode of the third PMOS tube and one end of the second capacitor; and the grid electrode of the third PMOS tube is connected with the second node, and the drain electrode of the third PMOS tube is connected with the ground terminal.
6. The circuit of claim 1, wherein the current mirror unit comprises two PMOS transistors and two NMOS transistors; the first NMOS transistor is connected with the first PMOS transistor;
grid electrodes of the fourth PMOS tube and the fifth PMOS tube are connected with the first node, and source electrodes of the fourth PMOS tube and the fifth PMOS tube are connected with a power supply; the drain electrode of the fourth PMOS tube is connected with the drain electrode of the first NMOS tube; the drain electrode of the fifth PMOS tube is connected with the drain electrode of the second NMOS tube; the sources of the first NMOS tube and the second NMOS tube are connected with a grounding end; and the drain electrode and the grid electrode of the first NMOS tube are connected with the grid electrode of the second NMOS tube.
7. The circuit of claim 6, wherein the other end of the second capacitor is connected to the drain of the fourth PMOS transistor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910865849.8A CN110572151B (en) | 2019-09-12 | 2019-09-12 | Phase-locked loop circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910865849.8A CN110572151B (en) | 2019-09-12 | 2019-09-12 | Phase-locked loop circuit |
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| CN110572151A CN110572151A (en) | 2019-12-13 |
| CN110572151B true CN110572151B (en) | 2023-06-30 |
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| CN111106829B (en) * | 2019-12-20 | 2023-06-27 | 睿兴科技(南京)有限公司 | High-precision ring oscillation circuit and micro-control system |
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| US4862015A (en) * | 1988-03-03 | 1989-08-29 | Motorola, Inc. | Constant propagation delay current reference |
| JP2938562B2 (en) * | 1990-11-28 | 1999-08-23 | 株式会社日立製作所 | Phase locked loop IC |
| CN102035547A (en) * | 2010-12-06 | 2011-04-27 | 上海集成电路研发中心有限公司 | Voltage-to-current converter |
| US9099995B2 (en) * | 2013-03-14 | 2015-08-04 | Qualcomm Incorporated | Ring oscillator circuit and method |
| CN107979356B (en) * | 2017-12-21 | 2021-07-02 | 上海华力微电子有限公司 | Voltage controlled oscillator circuit |
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