CN110572151A - Phase-locked loop circuit - Google Patents

Phase-locked loop circuit Download PDF

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Publication number
CN110572151A
CN110572151A CN201910865849.8A CN201910865849A CN110572151A CN 110572151 A CN110572151 A CN 110572151A CN 201910865849 A CN201910865849 A CN 201910865849A CN 110572151 A CN110572151 A CN 110572151A
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China
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node
capacitor
voltage
pmos tube
pmos
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CN201910865849.8A
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CN110572151B (en
Inventor
孙杰
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Chen Core Technology Co Ltd
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Chen Core Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The embodiment of the invention discloses a phase-locked loop circuit. The method comprises the following steps: the phase frequency detector comprises a phase frequency detector, a charge pump, a filter circuit, a voltage-current conversion circuit, a first capacitor, a voltage buffer unit, a second capacitor, a current mirror unit, a current control oscillator and a frequency divider; the phase frequency detector, the charge pump, the voltage-current conversion circuit, the current control oscillator and the frequency divider are connected in sequence; the filter circuit is connected between the first node and a grounding end; the first capacitor is connected between the second node and the grounding end; the input end of the voltage buffer unit is connected with the second node, and the input end of the voltage buffer unit is connected with one end of the second capacitor; the other end of the second capacitor is connected with the input end of the current mirror image unit, and the output end of the output unit of the current mirror image unit is connected with the second node. The voltage fluctuation caused by the oscillator can be reduced, and therefore the jitter of the output clock of the phase-locked loop circuit is reduced.

Description

Phase-locked loop circuit
Technical Field
the embodiment of the invention relates to the technical field of circuits, in particular to a phase-locked loop circuit.
Background
With the development of wireless communication technology and integrated circuit technology, more and more wireless communication systems are integrated on a chip. The phase-locked loop can generate an accurate clock signal or a frequency signal, so the phase-locked loop is widely applied to a clock generator, and a frequency synthesizer based on the phase-locked loop is widely applied to a radio frequency transceiving system in an electronic system such as a wireless communication transceiving system, a clock/data recovery circuit and the like. These needs have prompted the study and development of phase-locked loop circuits.
in the prior art, an oscillator in a phase-locked loop causes voltage fluctuation, so that clock jitter of the output of the phase-locked loop circuit is large, and therefore it is important to reduce the output jitter of the phase-locked loop.
disclosure of Invention
the embodiment of the invention provides a phase-locked loop circuit, which can reduce voltage fluctuation caused by an oscillator so as to reduce the jitter of an output clock of the phase-locked loop circuit.
in a first aspect, an embodiment of the present invention provides a phase-locked loop circuit, including: the phase frequency detector comprises a phase frequency detector, a charge pump, a filter circuit, a voltage-current conversion circuit, a first capacitor, a voltage buffer unit, a second capacitor, a current mirror unit, a current control oscillator and a frequency divider;
The phase frequency detector is provided with a reference signal input end and a feedback signal input end connected with the frequency divider; the phase frequency detector, the charge pump, the voltage-current conversion circuit, the current control oscillator and the frequency divider are connected in sequence;
The filter circuit is connected between the first node and a grounding end; wherein a first node is located between the charge pump and the voltage-to-current conversion circuit;
the first capacitor is connected between the second node and the grounding end; wherein a second node is located between the voltage-to-current conversion circuit and the current controlled oscillator;
The input end of the voltage buffer unit is connected with the second node, and the input end of the voltage buffer unit is connected with one end of the second capacitor; the other end of the second capacitor is connected with the input end of the current mirror image unit, and the output end of the output unit of the current mirror image unit is connected with the second node.
further, the voltage-current conversion circuit comprises a first PMOS tube; the current controlled oscillator comprises three inverters;
The grid electrode of the first PMOS tube is connected with the output end of the charge pump, the source electrode of the first PMOS tube is connected with a power supply, and the drain electrode of the first PMOS tube is respectively connected with the input stages of the three phase inverters; the three inverters are connected in series in a manner that the intermediate stage is connected with the output stage; the second node is positioned between the drain electrode of the first PMOS tube and the input stages of the three inverters.
Further, the phase inverter comprises a PMOS tube and an NMOS tube.
Further, the filter circuit comprises a first resistor and a third capacitor;
One end of the first resistor is connected with the first node, and the other end of the first resistor is connected with one end of the third capacitor; and the other end of the third capacitor is connected with a grounding end.
further, the voltage buffer unit comprises two PMOS tubes, namely a second PMOS tube and a third PMOS tube;
the grid electrode of the second PMOS tube is connected with the first node, the source electrode of the second PMOS tube is connected with a power supply, and the drain electrode of the second PMOS tube is respectively connected with the source electrode of the third PMOS tube and one end of the second capacitor; and the grid electrode of the third PMOS tube is connected with the second node, and the drain electrode of the third PMOS tube is connected with the grounding end.
Further, the current mirror unit comprises two PMOS tubes and two NMOS tubes; a fourth PMOS tube, a fifth PMOS tube, a first NMOS tube and a second NMOS tube respectively;
the grid electrodes of the fourth PMOS tube and the fifth PMOS tube are connected with the first node, and the source electrodes are connected with a power supply; the drain electrode of the fourth PMOS tube is connected with the drain electrode of the first NMOS tube; the drain electrode of the fifth PMOS tube is connected with the drain electrode of the second NMOS tube; the source electrodes of the first NMOS tube and the second NMOS tube are both connected with a grounding end; and the drain electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube.
Further, the other end of the second capacitor is connected with the drain electrode of the fourth PMOS transistor.
The phase-locked loop circuit provided by the embodiment of the invention comprises a phase frequency detector, a charge pump, a filter circuit, a voltage-current conversion circuit, a first capacitor, a voltage buffer unit, a second capacitor, a current mirror unit, a current control oscillator and a frequency divider; the first capacitor is connected between the second node and the grounding end; the second node is positioned between the voltage-current conversion circuit and the current control oscillator; the input end of the voltage buffer unit is connected with the second node, and the input end of the voltage buffer unit is connected with one end of the second capacitor; the other end of the second capacitor is connected with the input end of the current mirror image unit, and the output end of the output unit of the current mirror image unit is connected with the second node. The voltage fluctuation caused by the oscillator can be reduced, and therefore the jitter of the output clock of the phase-locked loop circuit is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a phase-locked loop circuit according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram of a current controlled oscillator according to a first embodiment of the present invention;
Fig. 3 is a schematic diagram of a partial structure of a pll circuit according to a first embodiment of the present invention;
Fig. 4 is a schematic diagram of voltages and currents at nodes in a pll circuit according to a first embodiment of the present invention.
Detailed Description
the present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
Fig. 1 is a schematic structural diagram of a phase-locked loop circuit according to an embodiment of the present invention, as shown in fig. 1, the phase-locked loop circuit includes: the phase frequency detector comprises a phase frequency detector, a charge pump, a filter circuit, a voltage-current conversion circuit, a first capacitor, a voltage buffer unit, a second capacitor, a current mirror unit, a current control oscillator and a frequency divider.
the phase frequency detector is provided with a reference signal input end and a feedback signal input end connected with the frequency divider; the phase frequency detector, the charge pump, the voltage-current conversion circuit, the current control oscillator and the frequency divider are connected in sequence. The filter circuit is connected between the first node and the grounding end; wherein the first node is located between the charge pump and the voltage-to-current conversion circuit. The first capacitor is connected between the second node and the grounding end; wherein the second node is located between the voltage-to-current conversion circuit and the current controlled oscillator. The input end of the voltage buffer unit is connected with the second node, and the input end of the voltage buffer unit is connected with one end of the second capacitor; the other end of the second capacitor is connected with the input end of the current mirror image unit, and the output end of the output unit of the current mirror image unit is connected with the second node.
As shown in fig. 1, the filter circuit includes a first resistor and a third capacitor; one end of the first resistor is connected with the first node, and the other end of the first resistor is connected with one end of the third capacitor; the other end of the third capacitor is connected with the grounding end.
fig. 2 is a schematic structural diagram of a current controlled oscillator according to an embodiment of the present invention. As shown in fig. 2, the voltage-current conversion circuit includes a first PMOS transistor; the current controlled oscillator comprises three inverters. The grid electrode of the first PMOS tube is connected with the output end of the charge pump, the source electrode of the first PMOS tube is connected with the power supply, and the drain electrode of the first PMOS tube is respectively connected with the input stages of the three phase inverters. The three inverters are connected in series in such a manner that the intermediate stage is connected to the output stage. The second node is positioned between the drain electrode of the first PMOS pipe and the input stages of the three inverters. In this embodiment, the inverter includes a PMOS transistor and an NMOS transistor.
Fig. 3 is a schematic diagram of a partial structure of a pll circuit according to an embodiment of the present invention, and as shown in fig. 3, the voltage buffer unit includes two PMOS transistors, which are a second PMOS transistor and a third PMOS transistor, respectively. The grid electrode of the second PMOS tube is connected with the first node, the source electrode of the second PMOS tube is connected with the power supply, and the drain electrode of the second PMOS tube is respectively connected with the source electrode of the third PMOS tube and one end of the second capacitor; the grid electrode of the third PMOS tube is connected with the second node, and the drain electrode of the third PMOS tube is connected with the grounding end.
The current mirror unit comprises two PMOS tubes and two NMOS tubes; a fourth PMOS tube, a fifth PMOS tube, a first NMOS tube and a second NMOS tube respectively; the grid electrodes of the fourth PMOS tube and the fifth PMOS tube are connected with the first node, and the source electrodes are connected with the power supply; the drain electrode of the fourth PMOS tube is connected with the drain electrode of the first NMOS tube; the drain electrode of the fifth PMOS tube is connected with the drain electrode of the second NMOS tube; the source electrodes of the first NMOS tube and the second NMOS tube are connected with the grounding end; the drain electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube. The other end of the second capacitor is connected with the drain electrode of the fourth PMOS tube.
In this embodiment, the first node is voltage controlled and implemented by a charge pump, a first resistor and a third capacitor, the first resistor and the third capacitor together form a zero and a pole of a loop, and the zero is located atWherein R is1Is the resistance value of the first resistor, C3Is the capacitance value of the third capacitor. The pole is located at the origin. The first PMOS tube realizes the conversion from voltage to current. Assuming that the equivalent resistance of the current controlled oscillator is R2, R2 and the first capacitor form another pole of the loop, which is located atWherein C is1is the capacitance value of the first capacitor. In this embodiment, ω is a constant loop of the current controlled oscillatorpTo be compared with omegazIs a certain multiple larger. For example, to achieve a phase margin of 60 degrees, ω is satisfiedp＞8*ωzThis requires that the value of C1 not be too large, so that C1 has a limited effect on the voltage and current at the second node.
In this embodiment, a voltage buffer unit, a second capacitor, and a current mirror unit are connected at the second node. Fig. 4 is a schematic diagram of voltages and currents at nodes in the pll circuit according to the present embodiment. Each node includes: a second node (node b), a voltage buffer unit output end node (node c), and a current mirror unit input end node (node d). As shown in fig. 4, when the voltage of the second node changes due to the equivalent resistance change of the current controlled oscillator or other sudden reasons, the voltage of the node c will change accordingly. If the voltage of the node d has an upward or downward pulse, the second capacitor couples the pulse to the control end of the current mirror unit, so that the current mirror module is controlled to output a pulse current to the second node to compensate the current flowing to the current control oscillator, and the purpose of stabilizing the voltage of the second node is achieved. When the voltage of the second node has step change, the circuit only responds within a short time after the step moment, and the normal working state of the circuit cannot be influenced.
In the phase-locked loop circuit in fig. 3, since the current flowing through the first PMOS transistor cannot change abruptly, the voltage of the second node changes when the oscillator is turned on or off. The second PMOS transistor is a source follower, and the voltage increase of the second node will cause the voltage of the node c to increase. Since the voltage across the capacitor cannot jump, the voltage at node c also increases, resulting in an increase in the voltage at node d. When the second NMOS transistor is in a saturation region, the voltage increase at the node d will cause the current flowing through the second NMOS transistor to increase, and the reduced current in the oscillator will be discharged through the second NMOS transistor, thereby reducing the voltage increase amplitude at the second node.
the equivalent capacitance of the third PMOS tube is far smaller than that of the second capacitor, and the capacitance value after the third PMOS tube and the second PMOS tube are connected in series is approximately equal to that of the third PMOS tube, so that the pole and the zero introduced by the newly added circuit do not influence the main pole and the zero of the loop.
The phase-locked loop circuit provided by the embodiment comprises a phase frequency detector, a charge pump, a filter circuit, a voltage-current conversion circuit, a first capacitor, a voltage buffer unit, a second capacitor, a current mirror unit, a current control oscillator and a frequency divider; the first capacitor is connected between the second node and the grounding end; the second node is positioned between the voltage-current conversion circuit and the current control oscillator; the input end of the voltage buffer unit is connected with the second node, and the input end of the voltage buffer unit is connected with one end of the second capacitor; the other end of the second capacitor is connected with the input end of the current mirror image unit, and the output end of the output unit of the current mirror image unit is connected with the second node. The voltage fluctuation caused by the oscillator can be reduced, and therefore the jitter of the output clock of the phase-locked loop circuit is reduced.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (7)

1. A phase-locked loop circuit, comprising: the phase frequency detector comprises a phase frequency detector, a charge pump, a filter circuit, a voltage-current conversion circuit, a first capacitor, a voltage buffer unit, a second capacitor, a current mirror unit, a current control oscillator and a frequency divider;
The phase frequency detector is provided with a reference signal input end and a feedback signal input end connected with the frequency divider; the phase frequency detector, the charge pump, the voltage-current conversion circuit, the current control oscillator and the frequency divider are connected in sequence;
The filter circuit is connected between the first node and a grounding end; wherein a first node is located between the charge pump and the voltage-to-current conversion circuit;
The first capacitor is connected between the second node and the grounding end; wherein a second node is located between the voltage-to-current conversion circuit and the current controlled oscillator;
the input end of the voltage buffer unit is connected with the second node, and the input end of the voltage buffer unit is connected with one end of the second capacitor; the other end of the second capacitor is connected with the input end of the current mirror image unit, and the output end of the output unit of the current mirror image unit is connected with the second node.
2. The circuit of claim 1, wherein the voltage-to-current conversion circuit comprises a first PMOS transistor; the current controlled oscillator comprises three inverters;
The grid electrode of the first PMOS tube is connected with the output end of the charge pump, the source electrode of the first PMOS tube is connected with a power supply, and the drain electrode of the first PMOS tube is respectively connected with the input stages of the three phase inverters; the three inverters are connected in series in a manner that the intermediate stage is connected with the output stage; the second node is positioned between the drain electrode of the first PMOS tube and the input stages of the three inverters.
3. The circuit of claim 2, wherein the inverter comprises a PMOS transistor and an NMOS transistor.
4. the circuit of claim 1, wherein the filter circuit comprises a first resistor and a third capacitor;
one end of the first resistor is connected with the first node, and the other end of the first resistor is connected with one end of the third capacitor; and the other end of the third capacitor is connected with a grounding end.
5. The circuit of claim 1, wherein the voltage buffer unit comprises two PMOS transistors, namely a second PMOS transistor and a third PMOS transistor;
The grid electrode of the second PMOS tube is connected with the first node, the source electrode of the second PMOS tube is connected with a power supply, and the drain electrode of the second PMOS tube is respectively connected with the source electrode of the third PMOS tube and one end of the second capacitor; and the grid electrode of the third PMOS tube is connected with the second node, and the drain electrode of the third PMOS tube is connected with the grounding end.
6. The circuit of claim 1, wherein the current mirror unit comprises two PMOS transistors and two NMOS transistors; a fourth PMOS tube, a fifth PMOS tube, a first NMOS tube and a second NMOS tube respectively;
The grid electrodes of the fourth PMOS tube and the fifth PMOS tube are connected with the first node, and the source electrodes are connected with a power supply; the drain electrode of the fourth PMOS tube is connected with the drain electrode of the first NMOS tube; the drain electrode of the fifth PMOS tube is connected with the drain electrode of the second NMOS tube; the source electrodes of the first NMOS tube and the second NMOS tube are both connected with a grounding end; and the drain electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube.
7. The circuit of claim 6, wherein the other end of the second capacitor is connected to the drain of the fourth PMOS transistor.
CN201910865849.8A 2019-09-12 2019-09-12 Phase-locked loop circuit Active CN110572151B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111106829A (en) * 2019-12-20 2020-05-05 睿兴科技(南京)有限公司 High-precision ring oscillation circuit and micro control system

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Publication number Priority date Publication date Assignee Title
US4862015A (en) * 1988-03-03 1989-08-29 Motorola, Inc. Constant propagation delay current reference
JPH04196922A (en) * 1990-11-28 1992-07-16 Hitachi Ltd Phase locked loop ic
CN102035547A (en) * 2010-12-06 2011-04-27 上海集成电路研发中心有限公司 Voltage-to-current converter
CN105075122A (en) * 2013-03-14 2015-11-18 高通股份有限公司 Ring oscillator circuit and method
CN107979356A (en) * 2017-12-21 2018-05-01 上海华力微电子有限公司 A kind of voltage-controlled oscillator circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862015A (en) * 1988-03-03 1989-08-29 Motorola, Inc. Constant propagation delay current reference
JPH04196922A (en) * 1990-11-28 1992-07-16 Hitachi Ltd Phase locked loop ic
CN102035547A (en) * 2010-12-06 2011-04-27 上海集成电路研发中心有限公司 Voltage-to-current converter
CN105075122A (en) * 2013-03-14 2015-11-18 高通股份有限公司 Ring oscillator circuit and method
CN107979356A (en) * 2017-12-21 2018-05-01 上海华力微电子有限公司 A kind of voltage-controlled oscillator circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111106829A (en) * 2019-12-20 2020-05-05 睿兴科技(南京)有限公司 High-precision ring oscillation circuit and micro control system
CN111106829B (en) * 2019-12-20 2023-06-27 睿兴科技(南京)有限公司 High-precision ring oscillation circuit and micro-control system

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