JP2012034212A - Phase-locked loop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase-locked loop circuit that can prevent a stationary phase error from occurring due to leakage at an input section of a voltage-controlled oscillator with a simple circuit configuration.SOLUTION: The phase-locked loop circuit comprises: a phase comparator 1 that detects a phase difference between a reference clock signal and a feedback clock signal; a charge pump circuit 2 that outputs current according to a detected phase difference to a capacitor; and a voltage-controlled oscillator 4 that generates an output clock signal having an oscillation frequency in response to the control voltage based on the amount of charge accumulated on the capacitor. The phase-locked loop circuit suppresses control voltage fluctuations due to the leakage current by generating the equivalent current to the leakage current flowing through the input section of the voltage-controlled oscillator 4 when the control voltage is in a lock state, and outputting correction current according to the generated current to the capacitor through a current mirror circuit.

Description

  The present invention relates to a phase locked loop (PLL) circuit.

  The PLL circuit has a function of multiplying a clock frequency, adjusting a skew of a clock signal in an LSI (Large-scale Integrated Circuit), etc., and realizing an increase in LSI speed and scale in recent years. Therefore, it is provided as an essential circuit (macro).

  With such market trends, it has become natural that PLL circuits are mounted on semiconductor chips. It has been recognized that with the reduction in voltage and miniaturization of semiconductor chips, the transistors constituting the PLL circuit are also being reduced in voltage and miniaturization. However, due to miniaturization in recent years, the amount of characteristic deterioration due to transistor leakage, which has been negligible as an analog operation of an analog circuit, has become so large that it cannot be ignored, and has become one of the major factors that deteriorate the steady phase error.

  7 is a diagram illustrating a configuration example of the PLL circuit, and FIGS. 8 and 9 are timing charts illustrating an operation example of the PLL circuit in FIG. The PLL circuit includes a phase comparison circuit (PFD) 201, a charge pump circuit (CP) 202, a low-pass filter (LPF) 203, a voltage controlled oscillation circuit (VCO) 204, and a frequency divider (DIV) 205. The voltage controlled oscillation circuit 204 includes an oscillator (OSC) 206 and an input transistor 207.

  The phase comparison circuit 201 compares the rising (or falling) phase of the reference clock signal REFCLK with the rising (or falling) phase of the feedback clock signal FBCLK. The phase comparison circuit 201 outputs the phase difference between the reference clock signal REFCLK and the feedback clock signal FBCLK to the charge pump circuit 202 as control signals UPB and DN. When the feedback clock signal FBCLK is delayed with respect to the reference clock signal REFCLK, the control signals UPB and DN become low level. Further, when the feedback clock signal FBCLK is advanced with respect to the reference clock signal REFCLK, the control signals UPB and DN become high level.

  The charge pump circuit 202 controls the control voltage VCNT by injecting or extracting charges according to the control signals UPB and DN with respect to the capacitance in the low-pass filter 203. When the control signals UPB and DN become low level, the capacitance in the low-pass filter 203 is connected to the power supply voltage, and the control voltage VCNT rises. When the control signals UPB and DN become high level, the capacitance in the low-pass filter 203 is connected to the reference potential, and the control voltage VCNT decreases. The voltage controlled oscillation circuit 204 outputs an output clock signal CKO having an oscillation frequency corresponding to the control voltage VCNT. When the control voltage VCNT increases, the frequency of the output clock signal CKO increases, and when the control voltage VCNT decreases, the frequency of the output clock signal CKO decreases. The frequency divider 205 divides the output clock signal CKO by N and outputs a feedback clock signal FBCLK. The output clock signal CKO is output as a frequency N times higher than the reference clock signal REFCLK.

  In more detail, when the phase of the feedback clock signal FBCLK is advanced from the reference clock signal REFCLK, the operation is performed such that the frequency of the output clock signal CKO is recognized as being too high and the frequency of the output clock signal CKO is lowered. Do. Therefore, the phase comparison circuit 201 sets the control signals UPB and DN to the high level, and the charge pump circuit 202 extracts the charge accumulated in the capacitor in the low-pass filter 203, thereby lowering the control voltage VCNT. On the other hand, when the phase of the feedback clock signal FBCLK is delayed from the reference clock signal REFCLK, the frequency of the output clock signal CKO is increased by recognizing that the frequency of the output clock signal CKO is too low. Therefore, the phase comparison circuit 201 sets the control signals UPB and DN to low level, and the charge pump circuit 202 increases the control voltage VCNT by injecting charge into the capacitor in the low-pass filter 203. In this way, the PLL circuit adjusts the frequency of the output clock signal CKO and locks it at the target frequency by changing the control voltage VCNT so that the phases of the reference clock signal REFCLK and the feedback clock signal FBCLK are matched.

  In the PLL circuit of FIG. 7, charge transfer from the charge pump circuit 202 to the capacitor in the low-pass filter 203 is not performed while the control signal UPB is at a high level and the control signal DN is at a low level. That is, while the control signal UPB is at a high level and the control signal DN is at a low level, both the output of the charge pump circuit 202 and the input of the voltage controlled oscillation circuit 204 are high impedance, and the charge accumulated in the capacitor in the low-pass filter 203 Is retained. As a result, as shown in FIG. 8, the control voltage VCNT maintains a constant value, and the frequency of the output clock signal CKO also maintains a constant value.

  However, due to the recent miniaturization of transistors, the input portion of the voltage controlled oscillation circuit 204 is no longer taking high impedance, and so-called gate leakage current is generated. For this reason, the charge accumulated in the capacitor in the low-pass filter 203 escapes from the input part of the voltage controlled oscillation circuit 204 (or the charge is injected from the input part of the voltage controlled oscillation circuit 204). As a result, as shown in FIG. 9, the control voltage VCNT cannot be maintained at a constant value during a period in which the control signal UPB is at a high level and the control signal DN is at a low level, so that the control voltage VCNT is lowered and the output clock signal The frequency of CKO will also decrease.

  As described above, since the control voltage VCNT cannot be maintained at a constant value while the control signal UPB is at the high level and the control signal DN is at the low level, even if the control voltage VCNT is adjusted to match the phase, the phase comparison is performed next. Sometimes the control voltage VCNT deviates from the adjusted value. Therefore, a steady phase difference (steady phase error) φ occurs between the reference clock signal REFCLK and the feedback clock signal FBCLK. Further, since the phase comparison circuit 201 controls the control voltage VCNT every time the clock signal rises so as to eliminate this phase difference (steady phase error) φ, the output clock signal CKO is spurious (frequency shift) every time the clock signal rises. Occurs.

  Patent Document 1 below proposes a technique for suppressing a stationary phase error caused by a leak generated at the input unit of the voltage controlled oscillation circuit 204. The PLL circuit described in Patent Document 1 includes a first charge pump circuit and a first low-pass filter to which a voltage controlled oscillation circuit is connected, a second charge pump circuit and a second low voltage filter to which a voltage controlled oscillation circuit is not connected. A dummy circuit including two low-pass filters is provided. Then, the control voltage at the input node of the voltage controlled oscillation circuit is compared with the control voltage at the node of the corresponding dummy circuit, and charge is injected or extracted from the input node of the voltage controlled oscillation circuit according to the comparison result. As a result, fluctuations in the control voltage due to leakage at the input part of the voltage controlled oscillation circuit are suppressed, and the steady phase error is suppressed.

  Patent Document 2 below proposes a PLL circuit including a leakage current compensation circuit that compensates for a leakage current in a low-pass filter in order to use a thin gate oxide film MOS transistor having a leakage current as a capacitor in the low-pass filter. . The leakage current compensation circuit samples and holds the voltage of the low-pass filter when the charge pump circuit is active, and supplies the current to the low-pass filter so that the held voltage is compared with the voltage of the low-pass filter when inactive. It is described to do. Similar to the PLL circuit described in Patent Document 2, a PLL circuit that compensates for leakage current in the low-pass filter is described in Patent Document 3 below. Patent Document 4 below detects whether the input voltage input to the voltage controlled oscillation circuit is a voltage within a predetermined range so that the oscillation frequency does not exceed the operable frequency of the frequency divider. In other cases, a PLL circuit that charges and discharges a charge in a low-pass filter has been proposed.

JP 2009-77308 A JP 2007-184778 A JP 2008-147868 A JP 2007-104585 A

  The PLL circuit described in Patent Document 1 is generated at the input portion of the voltage controlled oscillation circuit by providing a dummy circuit including a second charge pump circuit and a second low-pass filter to which the voltage controlled oscillation circuit is not connected. The steady-state phase error due to the leak is reduced. Here, since the capacitance of the low-pass filter has a relatively large circuit area compared to other circuit elements, the circuit area of the low-pass filter is also large. Further, the ratio of the low-pass filter is large in the circuit area of the PLL circuit. Therefore, when two sets of charge pump circuits and low-pass filters are provided as in the PLL circuit described in Patent Document 1, the circuit area becomes very large.

  An object of the present invention is to provide a phase-locked loop circuit that can prevent a stationary phase error due to leakage at an input portion of a voltage-controlled oscillation circuit with a simple circuit configuration.

  One aspect of the phase locked loop circuit is a phase comparison circuit that detects the phase difference between the reference clock signal and the feedback clock signal, a capacitor that holds the first voltage, and a current that corresponds to the detected phase difference is output to the capacitor A charge pump circuit that generates an output clock signal having an oscillation frequency corresponding to the first voltage of the capacitor, and outputs the output clock signal or a signal corresponding thereto as a feedback clock signal to the phase comparison circuit. Have. Furthermore, when the first voltage is a voltage in the locked state, a current generation circuit that generates a current equal to the leak current flowing in the input unit of the voltage controlled oscillation circuit, and a correction current according to the generated current Current mirror circuit for outputting to

  According to the present invention, the current generation circuit generates a current equal to the leakage current flowing in the input part of the voltage controlled oscillation circuit included in the phase lock loop circuit, and outputs a correction current corresponding to the current to the capacitor via the current mirror circuit. . Thereby, it is possible to suppress the fluctuation of the first voltage due to the leakage current at the input portion of the voltage controlled oscillation circuit with a simple circuit configuration, and it is possible to prevent a steady phase error.

It is a figure which shows the structural example of the PLL circuit by the 1st Embodiment of this invention. 3 is a timing chart illustrating an operation example of the PLL circuit illustrated in FIG. 1. It is a figure which shows the structural example of the PLL circuit by the 2nd Embodiment of this invention. It is a figure which shows the structural example of the PLL circuit by the 3rd Embodiment of this invention. It is a figure which shows the structural example of the PLL circuit by the 4th Embodiment of this invention. It is a figure which shows the structural example of the PLL circuit in embodiment of this invention. It is a figure which shows the structural example of a PLL circuit. 8 is a timing chart illustrating an operation example of the PLL circuit illustrated in FIG. 7. 8 is a timing chart illustrating an operation example of the PLL circuit illustrated in FIG. 7.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
A first embodiment of the present invention will be described.
FIG. 1 is a diagram illustrating a configuration example of a phase-locked loop (PLL) circuit according to the first embodiment, and FIG. 2 is a timing chart illustrating an operation example of the PLL circuit of FIG.

  As shown in FIG. 1, the PLL circuit includes a phase comparison circuit (PFD) 1, a charge pump circuit (CP) 2, a low pass filter (LPF) 3, a voltage controlled oscillation circuit (VCO) 4, and a frequency divider (DIV). 5 The PLL circuit includes an amplifier 21, resistors 22 and 23, a gate capacitor 24, and p-channel MOS field effect transistors 25 and 26. The charge pump circuit 2 includes switches 11 and 14 and constant current sources 12 and 13. The low pass filter 3 includes a resistor 15 and capacitors 16 and 17. The voltage controlled oscillation circuit 4 includes an oscillator (OSC) 18 and an input transistor 19.

  A series connection circuit of the switch 11 and the constant current source 12 is connected between nodes of the positive power supply voltage and the control voltage VCNTA. A series connection circuit of the constant current source 13 and the switch 14 is connected between the node of the control voltage VCNTA and a reference potential (for example, ground potential). A series connection circuit of the resistor 15 and the capacitor 16 is connected between the node of the control voltage VCNTA and the reference potential. The capacitor 17 is connected between the node of the control voltage VCNTA and the reference potential. The input transistor 19 is an n-channel MOS field effect transistor, the gate is connected to the node of the control voltage VCNTA, the source is connected to the reference potential, and the drain is connected to the oscillator 18.

  The phase comparison circuit 1 compares the rising (or falling) phase of the reference clock signal REFCLK with the rising (or falling) phase of the feedback clock signal FBCLK. The phase comparison circuit 1 outputs the phase difference between the reference clock signal REFCLK and the feedback clock signal FBCLK to the charge pump circuit 2 as control signals UPB and DN. When the feedback clock signal FBCLK is delayed with respect to the reference clock signal REFCLK, the control signals UPB and DN become low level. Further, when the feedback clock signal FBCLK is advanced with respect to the reference clock signal REFCLK, the control signals UPB and DN become high level. Here, the control signal UPB is a high level signal when negated, and the control signal DN is a low level signal when negated. The pulse widths (lengths of asserted periods) of the control signals UPB and DN become wider as the phase difference between the feedback clock signal FBCLK and the reference clock signal REFCLK is larger.

  The charge pump circuit 2 outputs a current corresponding to the control signals UPB and DN to the low-pass filter 3, and injects or extracts charges corresponding to the control signals UPB and DN to the capacitors 16 and 17 in the low-pass filter 3. Thus, the control voltage VCNTA is controlled. The switch 11 is turned on (conductive state) when the control signal UPB becomes low level, and turned off (non-conductive state) when the control signal UPB becomes high level. The switch 14 is turned on (conductive state) when the control signal DN becomes high level and turned off (non-conductive state) when the control signal DN becomes low level. When the control signals UPB and DN are at a low level, the capacitors 16 and 17 in the low-pass filter 3 are connected to the positive power supply voltage to inject charges, and the control voltage VCNTA rises. Further, when the control signals UPB and DN become high level, the capacitors 16 and 17 in the low-pass filter 3 are connected to the reference potential, the charge is extracted, and the control voltage VCNTA decreases. Note that when the rising (or falling) phases of the feedback clock signal FBCLK and the reference clock signal REFCLK are the same, the control signal UPB becomes low level and the control signal DN becomes high level with a narrow pulse width, and the control voltage VCNTA does not change.

  The voltage controlled oscillation circuit 4 outputs an output clock signal CKO having an oscillation frequency corresponding to the control voltage VCNTA. When the control voltage VCNTA increases, the frequency of the output clock signal CKO increases, and when the control voltage VCNTA decreases, the frequency of the output clock signal CKO decreases. The frequency divider 5 divides the output clock signal CKO by N and outputs a feedback clock signal FBCLK. The output clock signal CKO is output as a frequency N times higher than the reference clock signal REFCLK.

The basic operation of the PLL circuit according to the first embodiment will be described.
When the phase of the feedback clock signal FBCLK is ahead of the reference clock signal REFCLK, the control signals UPB and DN become high level, the switch 11 in the charge pump circuit 2 is turned off, and the switch 14 is turned on. As a result, the capacitors 16 and 17 in the low-pass filter 3 are connected to the reference potential, the charges accumulated in the capacitors 16 and 17 are extracted, and the control voltage VCNTA decreases. The voltage controlled oscillation circuit 4 reduces the oscillation frequency of the output clock signal CKO when the control voltage VCNTA decreases. As a result, the feedback clock signal FBCLK has a smaller amount of phase advance with respect to the reference clock signal REFCLK, and eventually the phase difference between the two becomes zero.

  On the contrary, when the phase of the feedback clock signal FBCLK is delayed from the reference clock signal REFCLK, the control signals UPB and DN become low level, the switch 11 in the charge pump circuit 2 is turned on, and the switch 14 is turned off. . As a result, the capacitors 16 and 17 in the low-pass filter 3 are connected to the power supply voltage, charges are injected into the capacitors 16 and 17, and the control voltage VCNTA rises. The voltage controlled oscillation circuit 4 increases the oscillation frequency of the output clock signal CKO when the control voltage VCNTA increases. As a result, the feedback clock signal FBCLK has a small amount of phase delay with respect to the reference clock signal REFCLK, and eventually the phase difference between the two becomes zero.

  Here, the node of the control voltage VCNTA is connected to the input terminal of the voltage controlled oscillation circuit 4 (the gate of the input transistor 19). As described above, due to the recent miniaturization of transistors, the input portion of the voltage controlled oscillation circuit 4 does not have a complete high impedance, and the gate leakage current IA of the input transistor 19 is generated. For this reason, even if both the switches 11 and 14 in the charge pump circuit 2 are off, the charges accumulated in the capacitors 16 and 17 in the low-pass filter 3 escape through the input part of the voltage controlled oscillation circuit 4. . As a result, if no improvement measures are taken, the control voltage input to the voltage controlled oscillation circuit 4 does not become a constant value like the control voltage VCNTA 'indicated by the broken line in FIG.

  In the present embodiment, a circuit including an amplifier 21, resistors 22 and 23, a gate capacitor 24, and p-channel transistors 25 and 26 is used to correct a change in the control voltage due to leakage at the input portion of the voltage controlled oscillation circuit 4. The control voltage input to the control oscillation circuit 4 is kept constant.

  The resistor 22 is connected between the node of the positive power supply voltage and the voltage VTARG, and the resistor 23 is connected between the node of the voltage VTARG and the reference potential. The voltage VTARG is equal to the control voltage VCNTA to be supplied to the voltage controlled oscillation circuit 4 when the reference clock signal REFCLK and the feedback clock signal FBCLK are in phase, that is, in the locked state. The voltage VTARG is determined in advance based on simulation or the like at the time of design. Further, the resistance values of the resistors 22 and 23 are set so that the determined voltage can be obtained by dividing the resistance between the positive power supply voltage and the reference potential. The amplifier 21 has one input terminal connected to the node of the voltage VTARG and the other input terminal connected to the node of the control voltage VCNTB. The output terminal of the amplifier 21 is connected to the node of the control voltage VCNTB.

  The gate capacitance 24 is a gate capacitance having the same size as the gate size of the input transistor 19 in the voltage controlled oscillation circuit 4 and is configured using an n-channel transistor having the same size as the input transistor 19. The gate capacitor 24 has a gate connected to the node of the control voltage VCNTB, and a source and a drain connected to a reference potential. In the p-channel transistor 25, the source is connected to the positive power supply voltage, and the gate and drain are connected to the node of the control voltage VCNTB. The p-channel transistor 26 is a transistor having the same size as the p-channel transistor 25, and has a source connected to a positive power supply voltage and a drain connected to the node of the control voltage VCNTA. Further, the gate of p channel transistor 26 is connected to the gate of p channel transistor 25 via node VCNTFB. That is, the p-channel transistors 25 and 26 constitute a current mirror circuit in which the p-channel transistor 25 is an input-side transistor and the p-channel transistor 26 is an output-side transistor.

  As described above, the gate capacitor 24 has the same size as that of the input transistor 19, and the voltage VTARG is equal to the control voltage VCNTA in the locked state. The amplifier 21 compares the voltage VTARG with the control voltage VCNTB and performs control so that the control voltage VCNTB is equal to the voltage VTARG, so that the gate leakage current IB in the gate capacitor 24 becomes the gate leakage current IA in the input transistor 19. Is equal to Since the p-channel transistors 25 and 26 constitute a current mirror circuit, the input current in the p-channel transistor 25 on the input side is equal to the output current IC in the p-channel transistor 26 on the output side. That is, the gate leakage current IB and the output current IC are equal. Therefore, by controlling the control voltage VCNTB to be equal to the voltage VTARG, the gate leakage current IA flowing out at the node of the control voltage VCNTA and the flowing-in current (correction current) IC become equal, and the amount of leakage due to the gate leakage current IA Charge is supplied by the current IC. As a result, as shown in FIG. 2, the control voltage VCNTA can be kept constant when both the switches 11 and 14 in the charge pump circuit 2 are off.

  As described above, according to the present embodiment, a current equal to the gate leakage current in the input transistor 19 in the voltage controlled oscillation circuit 4 is generated using the gate capacitor 24, and the control voltage VCNTA is generated via the current mirror circuit. Run to node. As a result, the same amount of charge as that lost due to the gate leakage current in the input transistor 19 can be supplied to the node of the control voltage VCNTA, and the control voltage VCNTA due to charge leakage at the input portion of the voltage controlled oscillation circuit 4 can be supplied. Can be prevented. Therefore, an increase in circuit area can be suppressed with a simple circuit configuration, fluctuations in the control voltage VCNTA due to leakage at the input portion of the voltage controlled oscillation circuit 4 can be suppressed, and a steady phase error can be prevented. Further, by preventing the steady phase error, it is possible to suppress spurious (frequency shift) generated in the output clock signal CKO of the voltage controlled oscillation circuit 4.

(Second Embodiment)
Next, a second embodiment of the present invention will be described.
FIG. 3 is a diagram illustrating a configuration example of a PLL circuit according to the second embodiment. 3, components having the same functions as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.

  As shown in FIG. 3, the PLL circuit includes a phase comparison circuit (PFD) 1, a charge pump circuit (CP) 2, a low pass filter (LPF) 3, a voltage controlled oscillation circuit (VCO) 4, and a frequency divider (DIV). 5 The PLL circuit includes an amplifier 31, resistors 32 and 33, a gate capacitor 34, and n-channel MOS field effect transistors 35 and 36. The series connection circuit of the resistor 15 and the capacitor 16 is connected between the nodes of the positive power supply voltage and the control voltage VCNTA, and the capacitor 17 is connected between the nodes of the positive power supply voltage and the control voltage VCNTA. The input transistor 30 of the voltage controlled oscillation circuit 4 is a p-channel MOS field effect transistor, the gate is connected to the node of the control voltage VCNTA, the source is connected to the positive power supply voltage, and the drain is connected to the oscillator 18. The basic operation of the PLL circuit according to the second embodiment is the same as the basic operation of the PLL circuit according to the first embodiment.

  In the second embodiment, the control voltage change due to the leakage of the input part of the voltage controlled oscillation circuit 4 is corrected by using a circuit including the amplifier 31, resistors 32 and 33, gate capacitance 34, and n-channel transistors 35 and 36. The control voltage input to the voltage controlled oscillation circuit 4 is maintained at a constant value.

  The resistor 32 is connected between the node of the positive power supply voltage and the voltage VTARG, and the resistor 33 is connected between the node of the voltage VTARG and the reference potential. The voltage VTARG is equal to the control voltage VCNTA to be supplied to the voltage controlled oscillation circuit 4 in the locked state, and is determined in advance based on simulation or the like at the time of design. The resistance values of the resistors 32 and 33 are set so that the determined voltage can be obtained by dividing the resistance between the positive power supply voltage and the reference potential. The amplifier 31 has one input terminal connected to the node of the voltage VTARG, the other input terminal connected to the node of the control voltage VCNTB, and the output terminal connected to a node of the control voltage VCNTB.

  The gate capacitor 34 is a gate capacitor having the same size as the gate size of the input transistor 30 in the voltage controlled oscillation circuit 4, and is configured using a p-channel transistor having the same size as the input transistor 30. The gate capacitor 34 has a gate connected to the node of the control voltage VCNTB, and a source and a drain connected to a positive power supply voltage. The n-channel transistor 35 has a source connected to the reference potential and a gate and a drain connected to the node of the control voltage VCNTB. The n-channel transistor 36 is a transistor having the same size as the n-channel transistor 35, the source is connected to the reference potential, the drain is connected to the node of the control voltage VCNTA, and the gate is connected to the gate of the n-channel transistor 35. That is, the n-channel transistors 35 and 36 constitute a current mirror circuit in which the n-channel transistor 35 is an input-side transistor and the n-channel transistor 36 is an output-side transistor.

  The amplifier 31 compares the voltage VTARG with the control voltage VCNTB and performs control so that the control voltage VCNTB becomes equal to the voltage VTARG, so that the gate leakage current IB in the gate capacitor 34 becomes the gate leakage current IA in the input transistor 30. Is equal to Further, since the gate leakage current IB and the output current IC are equal, by controlling the control voltage VCNTB to be equal to the voltage VTARG, the gate leakage current IA that flows at the node of the control voltage VCNTA and the current (correction current) IC that flows out are: Will be equal. Therefore, the amount of charge injected into the node of the control voltage VCNTA by the gate leak current IA is extracted from the node of the control voltage VCNTA by the current IC. As a result, the control voltage VCNTA can be kept constant when both the switches 11 and 14 in the charge pump circuit 2 are off.

  As described above, according to the present embodiment, a current equal to the gate leakage current in the input transistor 30 in the voltage controlled oscillation circuit 4 is generated using the gate capacitor 34, and the control voltage VCNTA is generated via the current mirror circuit. Run to node. As a result, the same amount of charge as the amount injected by the gate leakage current in the input transistor 30 can be drawn out from the node of the control voltage VCNTA, and the control by the charge injection from the input part of the voltage controlled oscillation circuit 4 is possible. The increase in voltage VCNTA can be prevented. Therefore, an increase in circuit area can be suppressed with a simple circuit configuration, fluctuations in the control voltage VCNTA due to leakage at the input portion of the voltage controlled oscillation circuit 4 can be suppressed, and a steady phase error can be prevented. Further, by preventing the steady phase error, it is possible to suppress spurious (frequency shift) generated in the output clock signal CKO of the voltage controlled oscillation circuit 4.

(Third embodiment)
Next, a third embodiment of the present invention will be described.
FIG. 4 is a diagram illustrating a configuration example of a PLL circuit according to the third embodiment. 4, components having the same functions as those shown in FIG. 1 are given the same reference numerals, and redundant descriptions are omitted. In the third embodiment (FIG. 4), the constant current sources 12 and 13 are deleted and a resistor 41 is added to the first embodiment (FIG. 1). Hereinafter, differences of the third embodiment from the first embodiment will be described. Resistor 41 is connected between the interconnection point of switches 11 and 14 and the node of control voltage VCNTA. The switch 11 is connected between the positive power supply voltage and the resistor 41, and the switch 14 is connected between the resistor 41 and the reference potential.

  As described above, the present embodiment eliminates the constant current sources 12 and 13 in the charge pump circuit 2 of FIG. 1 and also has a circuit configuration in which the resistor 41 is connected in series to the output of the charge pump circuit 2. The same effect as the embodiment can be realized. Similarly, the circuit configuration in which the constant current sources 12 and 13 in the charge pump circuit 2 of FIG. 3 are deleted and the resistor 41 is connected in series to the output of the charge pump circuit 2 is the same as in the second embodiment. The effect can be realized.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described.
FIG. 5 is a diagram illustrating a configuration example of a PLL circuit according to the fourth embodiment. 5, components having the same functions as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted. In the fourth embodiment (FIG. 5), the low-pass filter 3 is provided outside a PLL circuit IC (integrated circuit) 50 configured as one semiconductor chip as compared with the first embodiment (FIG. 1). The point is different. In other respects, the fourth embodiment is the same as the first embodiment. Even when the low-pass filter 3 is provided outside the PLL circuit IC 50 and the low-pass filter 3 is connected to the node of the control voltage VCNTA in the PLL circuit IC 50, the same effect as in the first embodiment can be realized. Similarly, even when the low-pass filter 3 of FIG. 3 is provided outside the PLL circuit IC 50 and the low-pass filter 3 is connected to the node of the control voltage VCNTA in the PLL circuit IC 50, the same as in the second embodiment. The effect of can be realized. Further, as in the third embodiment, the constant current sources 12 and 13 in the charge pump circuit 2 may be deleted, and the resistor 41 may be connected in series to the output of the charge pump circuit 2.

  In each embodiment described above, the resistor 15 and the capacitor 16 in the low-pass filter 3 may be omitted. Further, the frequency divider 5 may be omitted, and the output clock signal CKO of the voltage controlled oscillation circuit 4 may be directly input to the phase comparison circuit 1 as the feedback clock signal FBCLK. In that case, the output clock signal CKO is output as the same frequency as the reference clock signal REFCLK.

  In each embodiment, the gate capacitance of the same size as the input transistor 19 (or 30) in the voltage controlled oscillation circuit 4 is used to suppress the fluctuation of the control voltage VCNTA due to leakage at the input part of the voltage controlled oscillation circuit 4. However, the present invention is not limited to this. It is only necessary to be able to suppress the potential change of the input node caused by leakage at the input part of the voltage controlled oscillation circuit. For example, as shown in FIG. 6, two voltage controlled oscillation circuits are provided to output an output clock signal. You may make it suppress the electric potential change of the input node in a circuit.

  FIG. 6 is a diagram showing another configuration example of the PLL circuit according to the embodiment of the present invention. The PLL circuit includes a phase comparison circuit 101, a charge pump circuit 102, a low-pass filter 103, a first voltage controlled oscillation circuit 104, a frequency divider 105, a second voltage controlled oscillation circuit 106, and a current mirror circuit (CM) 107. Have. The phase comparison circuit 101, the charge pump circuit 102, the low-pass filter 103, the first voltage controlled oscillation circuit 104, and the frequency divider 105 are the phase comparison circuit 1, the charge pump circuit 2, the low-pass filter 3, the voltage in the above-described embodiment. It corresponds to the control oscillation circuit 4 and the frequency divider 5, respectively.

  The input part of the second voltage controlled oscillator circuit 106 is configured in the same manner as the input part of the first voltage controlled oscillator circuit 104. The second voltage controlled oscillation circuit 106 is a replica circuit of the first voltage controlled oscillation circuit 104 having an internal configuration similar to that of the first voltage controlled oscillation circuit 104, for example. The second voltage controlled oscillation circuit 106 is supplied with a voltage equal to the control voltage VCNT to be supplied to the first voltage controlled oscillation circuit 104 in the locked state as the control voltage. Therefore, a leakage current equal to the leakage current generated in the locked state at the input portion of the first voltage controlled oscillation circuit 104 can be generated at the input portion of the second voltage controlled oscillation circuit 106. The leakage current generated at the input unit of the second voltage controlled oscillation circuit 106 is duplicated by the current mirror circuit 107 and output to the node of the control voltage VCNT as the correction current ICM. As a result, a correction current equal to the leakage current generated in the locked state can be supplied at the input portion of the first voltage controlled oscillation circuit 104, and the control voltage due to the leakage at the input portion of the first voltage controlled oscillation circuit 104 can be supplied. It is possible to suppress fluctuations in VCNT and prevent steady phase errors.

The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.
Various aspects of the present invention will be described below as supplementary notes.

(Appendix 1)
A phase comparison circuit that detects the phase difference by comparing the phases of the reference clock signal and the feedback clock signal;
A capacity for holding the first voltage;
A charge pump circuit that outputs a current corresponding to the phase difference detected by the phase comparison circuit to the capacitor;
Voltage-controlled oscillation that generates an output clock signal having an oscillation frequency corresponding to the first voltage of the capacitor and outputs the output clock signal or a signal corresponding to the output clock signal as the feedback clock signal to the phase comparison circuit Circuit,
A current generation circuit for generating a current equal to a leakage current flowing in the input portion of the voltage controlled oscillation circuit when the first voltage is a voltage in a locked state;
And a current mirror circuit that outputs a correction current corresponding to the current generated by the current generation circuit to the capacitor.
(Appendix 2)
The phase-locked loop circuit according to claim 1, wherein the current generation circuit has the same size as an input transistor of the voltage-controlled oscillation circuit, and has a gate capacitance in which a voltage in the locked state is input to a gate. .
(Appendix 3)
The current generation circuit includes an amplifier in which the voltage in the locked state is input to one input terminal, the other input terminal is connected to the output terminal, and the output terminal is connected to the gate of the gate capacitor. The phase-locked loop circuit according to Supplementary Note 2, wherein the phase-locked loop circuit is characterized.
(Appendix 4)
2. The phase-locked loop circuit according to claim 1, wherein the current generation circuit is a replica circuit of the voltage controlled oscillation circuit to which a voltage in the locked state is input as an input voltage.
(Appendix 5)
The charge pump circuit includes a first switch and a first current source connected between a power supply voltage and the capacitor, and a second switch and a second current source connected between the capacitor and a reference potential. 5. The phase-locked loop circuit according to any one of appendices 1 to 4, wherein the phase-locked loop circuit is provided.
(Appendix 6)
A resistor connected between the charge pump circuit and the capacitor;
The charge pump circuit includes a first switch connected between a power supply voltage and the resistor, and a second switch connected between the resistor and a reference potential. The phase-locked loop circuit according to claim 1.
(Appendix 7)
The phase comparison circuit, the charge pump circuit, the voltage controlled oscillation circuit, the current generation circuit, and the current mirror circuit are provided in the same semiconductor chip,
The phase-locked loop circuit according to any one of appendices 1 to 6, wherein the capacitor is provided outside the semiconductor chip.

DESCRIPTION OF SYMBOLS 1 Phase comparison circuit 2 Charge pump circuit 3 Low pass filter 4 Voltage control oscillation circuit 5 Frequency divider 21, 31 Amplifier 22, 23, 32, 33, 41 Resistance 24, 34 Gate capacity 25, 26 p channel MOS field effect transistor 35, 36 n-channel MOS field effect transistor

Claims (5)

A phase comparison circuit that detects the phase difference by comparing the phases of the reference clock signal and the feedback clock signal;
A capacity for holding the first voltage;
A charge pump circuit that outputs a current corresponding to the phase difference detected by the phase comparison circuit to the capacitor;
Voltage-controlled oscillation that generates an output clock signal having an oscillation frequency corresponding to the first voltage of the capacitor and outputs the output clock signal or a signal corresponding to the output clock signal as the feedback clock signal to the phase comparison circuit Circuit,
A current generation circuit for generating a current equal to a leakage current flowing in the input portion of the voltage controlled oscillation circuit when the first voltage is a voltage in a locked state;
And a current mirror circuit that outputs a correction current corresponding to the current generated by the current generation circuit to the capacitor.   2. The phase-locked loop according to claim 1, wherein the current generation circuit has the same size as an input transistor of the voltage-controlled oscillation circuit, and has a gate capacitance in which a voltage in the locked state is input to a gate. circuit.   2. The phase-locked loop circuit according to claim 1, wherein the current generation circuit is a replica circuit of the voltage controlled oscillation circuit to which a voltage in the locked state is input as an input voltage.   The charge pump circuit includes a first switch and a first current source connected between a power supply voltage and the capacitor, and a second switch and a second current source connected between the capacitor and a reference potential. The phase locked loop circuit according to claim 1, wherein the phase locked loop circuit is provided. A resistor connected between the charge pump circuit and the capacitor;
The charge pump circuit includes a first switch connected between a power supply voltage and the resistor, and a second switch connected between the resistor and a reference potential. The phase lock loop circuit according to any one of the preceding claims.

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