CN109286369B - Voltage-controlled oscillator, integrated chip and electronic equipment - Google Patents
Voltage-controlled oscillator, integrated chip and electronic equipment Download PDFInfo
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- CN109286369B CN109286369B CN201710602561.2A CN201710602561A CN109286369B CN 109286369 B CN109286369 B CN 109286369B CN 201710602561 A CN201710602561 A CN 201710602561A CN 109286369 B CN109286369 B CN 109286369B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/02—Details
- H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1206—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1237—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator
- H03B5/124—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising a voltage dependent capacitance
Abstract
The present invention relates to the field of integrated circuit technologies, and in particular, to a voltage controlled oscillator, an integrated chip, and an electronic device. The voltage controlled oscillator includes: the circuit comprises a resistance unit, a current mirror unit, a bias unit and an oscillation unit. The current mirror unit biases a voltage at a first node of the first current path and a voltage at a third node of the third current path, respectively, to a first bias voltage in response to the first bias voltage provided by the bias unit. The current mirror unit is further configured to adjust a third current flowing through a third current path in response to the resistance configuration of the resistance unit, wherein the first current flowing through the first current path is equal to the third current. Therefore, the charging and discharging time of the capacitor of the oscillating unit can be indirectly adjusted to change the oscillating period of the oscillating unit by configuring the corresponding resistance value of the resistance unit, so that the changed oscillating period is closer to the expected oscillating period, and the output precision of the oscillating period is improved.
Description
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to a voltage controlled oscillator, an integrated chip, and an electronic device.
Background
A voltage-controlled oscillator (VCO) refers to an oscillating circuit in which an output frequency corresponds to an input control voltage, and is widely used in electronic devices. The voltage-controlled oscillator comprises an LC voltage-controlled oscillator, an RC voltage-controlled oscillator and a crystal voltage-controlled oscillator.
In the prior art, a controllable source is superposed on a ring-shaped RC voltage-controlled oscillator to realize the linear control of the output frequency by the input control voltage.
In the process of implementing the invention, the inventor finds that the prior related art has the following problems: because each stage of oscillation unit of the traditional RC voltage-controlled oscillator is greatly influenced by the process and the transmission delay in each stage of oscillation unit is not easy to estimate, a large error exists in the estimation of the oscillation period of the voltage-controlled oscillator.
Disclosure of Invention
An object of the embodiments of the present invention is to provide a voltage controlled oscillator, an integrated chip, and an electronic device, which solve the technical problem of low precision of an oscillation period in the conventional technology.
In order to solve the above technical problems, embodiments of the present invention provide the following technical solutions:
in a first aspect, an embodiment of the present invention provides a voltage controlled oscillator, including: a resistance unit; a current mirror unit connected to the resistance unit through a first current path; a bias unit connected with the current mirror unit through a second current path; an oscillation unit connected to the current mirror unit through a third current path; the current mirror unit is used for responding to a first bias voltage provided by the bias unit and biasing the voltage respectively positioned at the first node of the first current path and the voltage positioned at the third node of the third current path to be the first bias voltage; the current mirror unit is further configured to adjust a third current flowing through the third current path in response to the resistance configuration of the resistance unit, so as to change an oscillation period of the oscillation unit by adjusting a charge-discharge time of a capacitor of the oscillation unit, wherein the first current flowing through the first current path is equal to the third current.
Optionally, the current mirror unit includes: the current mirror circuit is used for responding to the input of an external power supply and outputting at least three branch currents; and the bias circuit is connected with the current mirror circuit, biases one of the at least three branch currents to be a first current and outputs the first current through the first current path, biases the other of the at least three branch currents to be a second current and outputs the second current through the second current path, and biases the other of the at least three branch currents to be a third current and outputs the third current through the third current path.
Optionally, the oscillation unit includes a plurality of stages of ring oscillation circuits, each stage of ring oscillation circuit includes a voltage bias terminal, a voltage input terminal, and a voltage output terminal, the voltage bias terminal of each stage of ring oscillation circuit is connected to the bias circuit through the third current path, the voltage input terminal of the rear stage of ring oscillation circuit is connected to the voltage output terminal of the front stage of ring oscillation circuit, and the voltage input terminal of the first stage of ring oscillation circuit is connected to the voltage output terminal of the final stage of ring oscillation circuit.
Optionally, each stage of the ring oscillator circuit includes a ring oscillator unit and a capacitor unit, the ring oscillator unit includes a first node, a second node and a third node, the first node is the voltage bias terminal and is connected to the current mirror unit through the third current path, the second node is the voltage input terminal, the third node is the voltage output terminal and is connected to the capacitor unit, wherein a voltage corresponding to the third node is the first bias voltage.
Optionally, the capacitance unit comprises a capacitance with an adjustable capacitance value.
Optionally, the current mirror circuit includes: the grid electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are all connected to a fifth node, and the drain electrode of the first PMOS tube is also connected to the fifth node; the bias circuit includes: the drain electrode of the first NMOS tube is connected to the fifth node, the drain electrode of the second PMOS tube, the grid electrode of the first NMOS tube, the drain electrode and the grid electrode of the second NMOS tube and the grid electrode of the third NMOS tube are all connected to the sixth node, the drain electrode of the third PMOS tube is connected to the drain electrode of the third NMOS tube, the source electrode of the first NMOS tube is connected with the resistance unit, the source electrode of the second NMOS tube is connected with the bias unit, and the source electrode of the third NMOS tube is connected with the oscillation unit; the ratio of the width-length ratio of the first PMOS tube to the width-length ratio of the first NMOS tube is a first proportional value; the ratio of the width-length ratio of the second PMOS tube to the width-length ratio of the second NMOS tube is a second ratio value; the first proportional value is equal to the second proportional value.
Optionally, the ratio between the width-to-length ratio of the first PMOS transistor and the width-to-length ratio of the second NMOS transistor is a third ratio value; the ratio of the width-length ratio of the third PMOS tube to the width-length ratio of the third NMOS tube is a fourth ratio value; the third proportional value is proportional to the fourth proportional value.
Optionally, the width-to-length ratio of the first PMOS transistor is equal to the width-to-length ratio of the second PMOS transistor.
Optionally, the bias unit includes a fourth NMOS transistor, a gate and a drain of the fourth NMOS transistor are both connected to the source of the second NMOS transistor, and a source of the fourth NMOS transistor is grounded.
Optionally, the oscillation unit comprises a three-stage ring oscillation circuit; the ring oscillation unit comprises CMOS phase inverters, voltage bias ends of all the CMOS phase inverters are connected with the current mirror unit through the third current path, voltage input ends of the rear stage CMOS phase inverters are connected with voltage output ends of the front stage CMOS phase inverters, and voltage input ends of the first stage CMOS phase inverters are connected with voltage output ends of the last stage CMOS phase inverters.
Optionally, the PMOS transistor of each stage of the CMOS inverter is an inverting transistor.
In a second aspect, an embodiment of the present invention provides an integrated chip including the voltage controlled oscillator of any one of the above.
In a third aspect, an embodiment of the present invention provides an electronic device including the voltage-controlled oscillator of any one of the above.
In various embodiments of the present invention, the current mirror unit biases the voltage at the first node of the first current path and the voltage at the third node of the third current path, respectively, to the first bias voltage in response to the first bias voltage provided by the bias unit. And the current mirror unit is also used for responding to the resistance value configuration of the resistor unit and adjusting a third current flowing through a third current path so as to change the oscillation period of the oscillation unit by adjusting the charging and discharging time of the capacitor of the oscillation unit, wherein the first current flowing through the first current path is equal to the third current. Therefore, the charging and discharging time of the capacitor of the oscillating unit can be indirectly adjusted to change the oscillating period of the oscillating unit by configuring the corresponding resistance value of the resistance unit, so that the changed oscillating period is closer to the expected oscillating period, and the output precision of the oscillating period is improved. And the current mirror unit can limit the current input into the oscillating unit, so that the effect of other parameters in the oscillating unit is reduced, the influence caused by temperature is reduced, and the power consumption is lower.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
Fig. 1 is a schematic block diagram of a voltage controlled oscillator according to an embodiment of the present invention;
fig. 2 is a schematic block diagram of another embodiment of the present invention to provide a voltage controlled oscillator;
FIG. 3 is a schematic block circuit diagram of the ring circuit of FIG. 2;
fig. 4 is a schematic circuit diagram of a voltage controlled oscillator according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The voltage-controlled oscillator provided by the embodiment of the invention can be used for a Phase Locked Loop (PLL), a Clock and Data Recovery (CDR) circuit and the like.
The voltage-controlled oscillator provided by the embodiment of the invention can be a ring-shaped RC voltage-controlled oscillator and can also be an LC voltage-controlled oscillator.
Referring to fig. 1, fig. 1 is a schematic block diagram of a voltage controlled oscillator according to an embodiment of the present invention. As shown in fig. 1, the voltage-controlled oscillator 10 includes a resistance unit 11, a current mirror unit 12, a bias unit 13, and an oscillation unit 14. The current mirror unit 12 is connected to the resistance unit 11 through a first current path 12A, the bias unit 13 is connected to the current mirror unit 12 through a second current path 12B, and the oscillation unit 14 is connected to the current mirror unit 12 through a third current path 12C.
The bias unit 13 can provide the first bias voltage V1 to the current mirror unit 12, and then the current mirror unit 12 biases the voltage at the first node 10A of the first current path 12A and the voltage at the third node 10C of the third current path 12C to the first bias voltage V1 respectively in response to the first bias voltage V1, wherein the voltage at the second node 10B of the second current path 12B is the first bias voltage V1.
Further, the current mirror unit 12 may mirror the first current I1 flowing through the first current path 12A and the third current I3 flowing through the third current path 12C to be equal to each other, that is, the current I1 is I3.
Here, the first current I1 may change following the change of the resistance value of the resistor unit 11, and thus, when the voltage of the first node 10A is equal to the voltage of the third node 10C, the magnitude of the third current I3 may be adjusted by changing the resistance value of the resistor unit 11. However, the third current I3 is used to charge the capacitance of the oscillating unit 14, and the capacitance of the oscillating unit 14 can delay the oscillation period of the oscillating signal. Therefore, the oscillation period of the oscillation unit 14 can be changed by adjusting the magnitude of the third current I3.
Still further, the current mirror unit 12 also adjusts the third current I3 flowing through the third current path 12C in response to the resistance configuration of the resistance unit 11 to change the oscillation period of the oscillation unit 14 by adjusting the charging and discharging time of the capacitance of the oscillation unit 14.
In some embodiments, the resistor unit 11 may be a resistor with an adjustable resistance, and therefore, by adjusting the resistance of the resistor unit 11, the first current I1 can be adjusted so that the current mirror unit 12 replicates the first current I1 to the third current path 12C, i.e., the third current I3 is equal to the first current I1.
Those skilled in the art can select suitable discrete components to design the bias unit 13 and make the bias unit 13 output the first bias voltage V1 according to the teaching of the embodiments of the present invention, and in some embodiments, the first bias voltage V1 may be a voltage that is not affected by temperature. Further, one skilled in the art can select suitable discrete components to design the current mirror unit 12 such that the current mirror unit 12 biases the voltages of the first node 10A and the third node 10C to the first bias voltage V1 in response to the first bias voltage V1.
Therefore, by configuring the resistance value corresponding to the resistance unit 11, the charging and discharging time of the capacitor of the oscillation unit 14 can be indirectly adjusted to change the oscillation period of the oscillation unit, so that the changed oscillation period is closer to the expected oscillation period, thereby improving the accuracy of the oscillation period output. In addition, the current mirror unit 12 can limit the current input to the oscillation unit, thereby reducing the effect of other parameters in the oscillation unit 14, reducing the influence of temperature, and reducing power consumption.
In some embodiments, as shown in fig. 2, the current mirror unit 12 includes: the current mirror circuit 121 and the bias circuit 122 are connected, and the bias circuit 122 and the current mirror circuit 121 are connected.
The current mirror circuit 121 outputs at least three branch currents in response to an input of the external power supply 123. The bias circuit 122 biases one of the at least three branch currents to be the first current I1 and output through the first current path 12A, biases another branch current of the at least three branch currents 12B to be the second current I2 and output through the second current path 12B, and biases another branch current of the at least three branch currents to be the third current I3 and output through the third current path 12C, respectively.
The bias circuit 122 can improve the output reliability of the first current I1, the second current I2 and the third current I3, and reduce the temperature effect on the first current I1, the second current I2 and the third current I3, so that the current mirror unit 12 includes: the current mirror circuit 121 and the bias circuit 122, and the bias circuit 122 and the current mirror circuit 121 have low temperature drift characteristics. Also, the current mirror circuit 121 can limit the current input to the oscillation unit 14, and thus power consumption is lower.
As shown in fig. 2, the oscillating unit 14 includes a plurality of stages of ring oscillating circuits, each stage of ring oscillating circuit includes a voltage bias terminal, a voltage input terminal and a voltage output terminal, and the voltage bias terminal of each stage of ring oscillating circuit is connected to the bias circuit 122 through the third current path 12C. The voltage input end of the rear stage ring oscillation circuit is connected with the voltage output end of the front stage ring oscillation circuit, and the voltage input end of the first stage ring oscillation circuit is connected with the voltage output end of the last stage ring oscillation circuit.
It can be understood that: in the following ring oscillator circuit and the preceding ring oscillator circuit, the preceding ring oscillator circuit is a following ring oscillator circuit with respect to the ring oscillator circuit located in front of the preceding ring oscillator circuit. The rear stage ring oscillator circuit is a front stage ring oscillator circuit relative to the ring oscillator circuit behind the rear stage ring oscillator circuit. Further, the first stage ring oscillator circuit is located at the head end of the oscillation unit 14 composed of the multi-stage ring oscillator circuit, and the last stage ring oscillator circuit is located at the tail end of the oscillation unit 14 composed of the multi-stage ring oscillator circuit. For example: referring to fig. 2, in the ring oscillator circuit 142, compared to the ring oscillator circuit 143, the ring oscillator circuit 142 is a front-stage ring oscillator circuit, and the ring oscillator circuit 143 is a rear-stage ring oscillator circuit. Similarly, in the ring oscillator circuit 143, compared to the ring oscillator circuit 144, the ring oscillator circuit 143 is a front stage ring oscillator circuit, and the ring oscillator circuit 144 is a rear stage ring oscillator circuit. Here, the ring oscillator circuit 141 is a first-stage ring oscillator circuit, and the ring oscillator circuit 14N is a last-stage ring oscillator circuit.
In the embodiment of the invention, by arranging the multistage ring oscillation circuit, a desired low-frequency oscillation signal can be effectively output.
In some embodiments, as shown in fig. 3, each stage of the ring oscillator circuit includes a ring oscillator unit 1411 and a capacitor unit 1412, the ring oscillator unit 1411 includes a first node 31a, a second node 31b and a third node 31C, the first node 31a is a voltage bias terminal and is connected to the bias circuit 122 through a third current path 12C, the second node 31b is a voltage input terminal, and the third node 31C is a voltage output terminal and is connected to the capacitor unit 1412, wherein a voltage corresponding to the third node 31C is the first bias voltage V1.
In some embodiments, the capacitor unit 1412 includes a capacitor with an adjustable capacitance value, so that the charging and discharging time of the capacitor of the oscillation unit 14 can be indirectly adjusted by configuring the corresponding resistance value of the resistor unit 11 and the capacitor of the capacitor unit 1412 to change the oscillation period of the oscillation unit, so that the changed oscillation period is closer to a desired oscillation period, thereby improving the accuracy of the oscillation period output.
In order to explain the voltage-controlled oscillator in detail in the above embodiments, the following detailed description is made with reference to fig. 4, and as shown in fig. 4, the current mirror circuit 121 according to the embodiment of the present invention includes: the sources of the first, second and third PMOS transistors PQ1, PQ2 and PQ3, the sources of the first, second and third PMOS transistors PQ1, PQ2 and PQ3 are all connected to the fourth node 41, the fourth node 41 is further connected to the external power source AVCC, the gates of the first, second and third PMOS transistors PQ1, PQ2 and PQ3 are all connected to the fifth node 42, and the drain of the first PMOS transistor PQ1 is also connected to the fifth node 42.
As shown in fig. 4, the bias circuit 122 includes: a first NMOS transistor NQ1, a second NMOS transistor NQ2, and a third NMOS transistor NQ3, wherein a drain of the first NMOS transistor NQ1 is connected to the fifth node 42, a drain of the second PMOS transistor PQ2, a gate of the first NMOS transistor NQ1, a drain and a gate of the second NMOS transistor NQ2, and a gate of the third NMOS transistor NQ3 are all connected to the sixth node 43, a drain of the third PMOS transistor PQ3 is connected to a drain of the third NMOS transistor NQ3, a source of the first NMOS transistor NQ1 is connected to the resistance unit 11, a source of the second NMOS transistor NQ2 is connected to the bias unit 13, and a source of the third NMOS transistor NQ3 is connected to the oscillation unit 14.
As shown in fig. 4, the bias unit 13 includes a fourth NMOS transistor NQ4, the gate and the drain of the fourth NMOS transistor NQ4 are both connected to the source of the second NMOS transistor NQ2, and the source of the fourth NMOS transistor NQ4 is grounded.
As shown in fig. 4, the voltage controlled oscillator further includes a fifth NMOS transistor NQ5, a gate of the fifth NMOS transistor NQ5 is used for inputting an external enable signal, a drain of the fifth NMOS transistor NQ5 is connected to the sixth node 43, and a source of the fifth NMOS transistor NQ5 is grounded.
As shown in fig. 4, the oscillating unit 14 includes three stages of ring oscillating circuits, each of the ring oscillating units 1411 of each stage of ring oscillating circuit includes a CMOS inverter 51, a voltage bias terminal of each stage of the CMOS inverter 51 is connected to the current mirror unit through a third current path 12C, a voltage input terminal of a subsequent stage of the CMOS inverter is connected to a voltage output terminal of a previous stage of the CMOS inverter, and a voltage input terminal of a first stage of the CMOS inverter is connected to a voltage output terminal of a last stage of the CMOS inverter.
In this embodiment, a ratio between the width-to-length ratio of the first PMOS transistor PQ1 and the width-to-length ratio of the first NMOS transistor NQ1 is a first ratio value, a ratio between the width-to-length ratio of the second PMOS transistor PQ2 and the width-to-length ratio of the second NMOS transistor NQ2 is a second ratio value, and the first ratio value is equal to the second ratio value. Therefore, the source voltages of the first NMOS transistor NQ1 and the second NMOS transistor NQ2 are equal.
In some embodiments, the width-to-length ratio of the first PMOS transistor PQ1 is equal to the width-to-length ratio of the second PMOS transistor PQ2, and the width-to-length ratio of the first NMOS transistor NQ1 is equal to the width-to-length ratio of the second NMOS transistor NQ 2.
Because the fourth NMOS transistor NQ4 is diode connected, the source voltages of the first NMOS transistor NQ1 and the second NMOS transistor NQ2 are close to the drain-source voltage drop Vth of the fourth NMOS transistor NQ 4.
When the resistance value of the resistance unit 11 is R, it is obvious that the first current I1 flowing through the first current path 12A is:
I1＝Vth/R
in some embodiments, the ratio between the width-to-length ratio of the first PMOS transistor and the width-to-length ratio of the second NMOS transistor is a third ratio value, the ratio between the width-to-length ratio of the third PMOS transistor and the width-to-length ratio of the third NMOS transistor is a fourth ratio value, and the third ratio value is in a proportional relationship with the fourth ratio value. Therefore, the source voltage of the second NMOS tube is equal to the source voltage of the third NMOS tube.
As shown in fig. 4, in the oscillation unit 14, the voltage V0 at the voltage output terminal of each stage of the CMOS inverter is equal to the source voltage of the second NMOS transistor NQ 2.
The following is a process of deriving a capacitance charging time required for the capacitance element 1412 of each stage of the ring oscillator circuit to go from 0 to V0:
when the capacitor unit 1412 is charged:
Q＝CU＝It
wherein: u is V0, C is the capacitance value of the capacitor unit 1412 of each stage of the ring oscillator circuit, I is the current flowing through the capacitor unit 1412 of each stage of the ring oscillator circuit, I is I1, t is the charging time of the capacitor unit 1412 of each stage of the ring oscillator circuit, and Q is the charge amount of the capacitor unit 1412 of each stage of the ring oscillator circuit during charging.
Because: I-I1-V0/R-Vth/R
Thus, the following equations are combined:
t＝RC
since the charging time of the capacitor unit 1412 of each stage of the ring oscillator circuit is equal to the discharging time, the period of the ring oscillator circuit is T-2 RC.
As can be seen from the above description, in the process of popularization, the voltage-controlled oscillator 10 is only related to the resistance value of the resistor 11 and the capacitance value of the capacitor 1412, but is not related to other design parameters, so that the voltage-controlled oscillator 10 can output an oscillation signal with a high-precision oscillation period by adjusting the resistance value of the resistor 11 or the capacitance value of the capacitor 1412.
As can be seen from the above, since the capacitance of the capacitance unit 1412 of each stage of the ring oscillator circuit can be adjusted, the parasitic capacitance of each discrete component in the voltage-controlled oscillator can be ignored, and calculation is facilitated.
As can be seen from the above, since the maximum value of the current in the voltage-controlled oscillator is controlled by the current mirror unit, the current of the oscillating unit 14 does not change greatly, and thus, the power consumption can be reduced.
In some embodiments, in order to further reduce the power consumption of the vco, the voltage of the external power source AVCC may be set to 1.5V, so as to reduce the simultaneous conduction time of the upper and lower switching tubes of the CMOS inverter when the output level is inverted up and down.
In some embodiments, since the swing of the output voltage of each stage of the ring oscillator circuit is smaller than the voltage V0, the PMOS transistor of each stage of the CMOS inverter can be an inverting transistor, which is helpful to reduce the charge of the PMOS transistor to the capacitor unit 1412 when the level is inverted from high to low and the upper and lower switching transistors of the CMOS inverter are turned on simultaneously, thereby shortening the discharge time of the capacitor unit 1412 and reducing the power consumption of the whole loop.
In addition, when the voltage-controlled oscillator 10 starts to oscillate, the total current of the ring oscillator circuit is limited by the current mirror unit 12, so the source voltage of the third NMOS transistor can be stabilized within a small range (about 1mv, depending on the process), and the current of the whole voltage-controlled oscillator 10 is also limited within a small range, so that the power consumption of the voltage-controlled oscillator 10 is low.
As another aspect of the embodiments of the present invention, an embodiment of the present invention provides an integrated chip, which includes a voltage controlled oscillator, where the voltage controlled oscillator is the voltage controlled oscillator described in the foregoing embodiments (as shown in fig. 1 to 4).
In this embodiment, by configuring the resistance value corresponding to the resistance unit, the charging and discharging time of the capacitor of the oscillation unit can be indirectly adjusted to change the oscillation period of the oscillation unit, so that the changed oscillation period is closer to the expected oscillation period, thereby improving the accuracy of the oscillation period output. And the current mirror unit can limit the current input into the oscillating unit, so that the effect of other parameters in the oscillating unit is reduced, the influence caused by temperature is reduced, and the power consumption is lower.
As another aspect of the embodiments of the present invention, an embodiment of the present invention provides an electronic device, which includes a voltage-controlled oscillator, where the voltage-controlled oscillator is the voltage-controlled oscillator described in the above embodiments (as shown in fig. 1 to 4).
In this embodiment, by configuring the resistance value corresponding to the resistance unit, the charging and discharging time of the capacitor of the oscillation unit can be indirectly adjusted to change the oscillation period of the oscillation unit, so that the changed oscillation period is closer to the expected oscillation period, thereby improving the accuracy of the oscillation period output. And the current mirror unit can limit the current input into the oscillating unit, so that the effect of other parameters in the oscillating unit is reduced, the influence caused by temperature is reduced, and the power consumption is lower.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; within the idea of the invention, also technical features in the above embodiments or in different embodiments may be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (11)
1. A voltage controlled oscillator, comprising:
a resistance unit;
a current mirror unit connected to the resistance unit through a first current path; the current mirror unit comprises a current mirror circuit and a bias circuit; wherein, the current mirror circuit is used for responding to the input with the external power supply, output at least three branch circuit currents, the current mirror circuit includes: the grid electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are all connected to a fifth node, and the drain electrode of the first PMOS tube is also connected to the fifth node;
the bias circuit is connected to the current mirror circuit, and is configured to bias one of the at least three branch currents to a first current and output the first current through a first current path, bias another one of the at least three branch currents to a second current and output the second current through a second current path, and bias another one of the at least three branch currents to a third current and output the third current through a third current path, respectively, where the bias circuit includes: the drain electrode of the first NMOS tube is connected to the fifth node, the drain electrode of the second PMOS tube, the grid electrode of the first NMOS tube, the drain electrode and the grid electrode of the second NMOS tube and the grid electrode of the third NMOS tube are all connected to the sixth node, the drain electrode of the third PMOS tube is connected to the drain electrode of the third NMOS tube, the source electrode of the first NMOS tube is connected with the resistance unit, the source electrode of the second NMOS tube is connected with the bias unit, and the source electrode of the third NMOS tube is connected with the oscillation unit;
the ratio of the width-length ratio of the first PMOS tube to the width-length ratio of the first NMOS tube is a first ratio value, the ratio of the width-length ratio of the second PMOS tube to the width-length ratio of the second NMOS tube is a second ratio value, and the first ratio value is equal to the second ratio value;
a bias unit connected with the current mirror unit through the second current path;
an oscillation unit connected to the current mirror unit through the third current path;
the current mirror unit is used for responding to a first bias voltage provided by the bias unit and biasing the voltage respectively positioned at the first node of the first current path and the voltage positioned at the third node of the third current path to be the first bias voltage;
the current mirror unit is further configured to adjust a third current flowing through the third current path in response to the resistance configuration of the resistance unit, so as to change an oscillation period of the oscillation unit by adjusting a charge-discharge time of a capacitor of the oscillation unit, wherein the first current flowing through the first current path is equal to the third current.
2. The vco of claim 1, wherein the oscillating unit comprises a plurality of stages of ring oscillator circuits, each stage of ring oscillator circuit comprises a voltage bias terminal, a voltage input terminal and a voltage output terminal, the voltage bias terminal of each stage of ring oscillator circuit is connected to the bias circuit through the third current path, the voltage input terminal of the next stage of ring oscillator circuit is connected to the voltage output terminal of the previous stage of ring oscillator circuit, and the voltage input terminal of the first stage of ring oscillator circuit is connected to the voltage output terminal of the last stage of ring oscillator circuit.
3. The vco of claim 2, wherein each stage of the ring oscillator circuit comprises a ring oscillator unit and a capacitor unit, the ring oscillator unit comprises a first node, a second node and a third node, the first node is the voltage bias terminal and is connected to the current mirror unit through the third current path, the second node is the voltage input terminal, the third node is the voltage output terminal and is connected to the capacitor unit, and a voltage corresponding to the third node is the first bias voltage.
4. The voltage controlled oscillator of claim 3, wherein the capacitance unit comprises a capacitance with an adjustable capacitance value.
5. The voltage controlled oscillator of claim 1,
the ratio of the width-length ratio of the first PMOS tube to the width-length ratio of the second NMOS tube is a third ratio value;
the ratio of the width-length ratio of the third PMOS tube to the width-length ratio of the third NMOS tube is a fourth ratio value;
the third proportional value is proportional to the fourth proportional value.
6. The voltage controlled oscillator of claim 1, wherein a width-to-length ratio of the first PMOS transistor is equal to a width-to-length ratio of the second PMOS transistor.
7. The VCO according to claim 1, wherein said bias unit comprises a fourth NMOS transistor, a gate and a drain of said fourth NMOS transistor are both connected to a source of said second NMOS transistor, and a source of said fourth NMOS transistor is grounded.
8. The voltage controlled oscillator of claim 3,
the oscillation unit comprises a three-stage ring oscillation circuit;
the ring oscillation unit comprises CMOS phase inverters, voltage bias ends of all the CMOS phase inverters are connected with the current mirror unit through the third current path, voltage input ends of the rear stage CMOS phase inverters are connected with voltage output ends of the front stage CMOS phase inverters, and voltage input ends of the first stage CMOS phase inverters are connected with voltage output ends of the last stage CMOS phase inverters.
9. The voltage controlled oscillator of claim 8, wherein the PMOS transistors of each stage of the CMOS inverter are inverting transistors.
10. An integrated chip comprising a voltage controlled oscillator as claimed in any one of claims 1 to 9.
11. An electronic device comprising a voltage controlled oscillator as claimed in any one of claims 1 to 9.
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| CN112165325A (en) * | 2020-09-27 | 2021-01-01 | 灿芯半导体(上海)有限公司 | Voltage controlled oscillator circuit for PLL circuit |
| US11750192B2 (en) * | 2021-02-24 | 2023-09-05 | Nvidia Corp. | Stability of bit generating cells through aging |
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