CN108667456A - A kind of charge pump, processing method and phase-locked loop circuit based on charge pump - Google Patents
A kind of charge pump, processing method and phase-locked loop circuit based on charge pump Download PDFInfo
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- CN108667456A CN108667456A CN201710194256.4A CN201710194256A CN108667456A CN 108667456 A CN108667456 A CN 108667456A CN 201710194256 A CN201710194256 A CN 201710194256A CN 108667456 A CN108667456 A CN 108667456A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
- H03L7/0893—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
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Abstract
The invention discloses a kind of charge mercury, including：Charge pump main circuit, common mode feedback circuit, voltage offset electric circuit；The charge pump main circuit generates the differential output voltage of charge pump for the difference control signal using input；The common mode feedback circuit, for the syntype bias voltage based on the differential output voltage and voltage offset electric circuit offer, generate feedback voltage signal, and export the feedback voltage signal to the charge pump main circuit, to adjust the common-mode voltage for the differential output voltage that the charge pump main circuit generates based on the feedback voltage signal.The present invention further simultaneously discloses a kind of processing method and phase-locked loop circuit based on charge pump.
Description
Technical field
The present invention relates to integrated circuit technique more particularly to a kind of charge pump, processing methods and locking phase based on charge pump
Loop circuit.
Background technology
In recent years, using the phaselocked loop of charge pump construction (PLL, Phase-Locked Loop) due to be capable of providing it is accurate,
The clock signal of low jitter is widely used in various electronic devices.It is existing general using the phaselocked loop of charge pump construction
Including phase frequency detector (FPD, Frequency Phase Detector), charge pump (CP, Charge Pump), low-pass filtering
The components such as device (LPF, Low Pass Filter) and voltage controlled oscillator (VCO, Voltage Control Oscillator).Its
In, the effect of charge pump is the signal amplification for exporting FPD, and charge and discharge are carried out to the capacitance of LPF.Charge pump also referred to as switchs electricity
Appearance formula voltage changer, be it is a kind of using so-called " quick " (flying) or " pumping " capacitance (rather than inductance or transformer) come
The DC-DC converter of energy storage.Charge pump controls electricity in some way using internal switch with field-effect transistors array
The transmission of charge in appearance typically controls the charge and discharge of capacitance in charge pump, to make input voltage with certain with clock signal
Mode be raised and lowered, to reach required output voltage.
However, in some phase-locked loop circuits, existing charge pump is difficult to meet the requirement of the phase-locked loop circuit.For example,
In inductance capacitance phase-locked loop circuit, existing charge pump due under low voltage environment generated differential output voltage do not have
There are higher stability and matching, lead to not the requirement for meeting LC voltage controlled oscillator, causes inductance capacitance locking phase
The performance of loop circuit declines.
Invention content
In view of this, an embodiment of the present invention provides a kind of charge pump, the processing method based on charge pump and phaselocked loop electricity
Road can generate the differential output voltage with higher stability and matching under low voltage environment.
In order to achieve the above objectives, the technical proposal of the invention is realized in this way：
An embodiment of the present invention provides a kind of charge pump, the charge pump includes：
The embodiment of the present invention provides a kind of charge pump, and the charge pump includes：Charge pump main circuit, common mode feedback circuit,
Voltage offset electric circuit；Wherein,
The charge pump main circuit generates the differential output voltage of charge pump for the difference control signal using input；
The common mode feedback circuit, the common mode for being provided based on the differential output voltage and the voltage offset electric circuit
Bias voltage generates feedback voltage signal, and the feedback voltage signal is exported to the charge pump main circuit, to be based on
State the common-mode voltage that feedback voltage signal adjusts the differential output voltage that the charge pump main circuit generates.
In said program, the charge pump further includes：Zero compensation circuit, for the phase to the common mode feedback circuit
It compensates.
In said program, the charge pump main circuit include the first branch, the second branch being connect with the first branch,
The third branch being connect with the second branch；Wherein,
The first branch, as discharge current source, for providing discharge current for the second branch；
The third branch, as charging current source, for providing charging current for the second branch；And it receives
The feedback voltage signal of the common mode feedback circuit output, adjusts the charging current；
The second branch, for according to the difference control signal of input, charging current and discharge current, determining charge pump
Differential output voltage.
In said program, the common mode feedback circuit includes the 4th branch, the 5th branch；Wherein,
4th branch, for obtaining electricity to be detected in the way of electric resistance partial pressure based on the differential output voltage
Pressure；The voltage to be detected is more than the half of the sum of described differential output voltage；
5th branch, the syntype bias electricity provided for the voltage to be detected and the voltage offset electric circuit
Pressure generates feedback voltage signal according to comparison result, and the feedback voltage signal is exported to the charge pump main circuit.
In said program, the first branch includes the first NMOS tube, the second NMOS tube, and the second branch includes first
PMOS tube, the second PMOS tube, third PMOS tube, the 4th PMOS tube, the third branch include the 5th PMOS tube, the 6th PMOS
Pipe；
The grid of first NMOS tube connects the grid of the second NMOS tube and the grid of the first NMOS tube and the second NMOS tube
Grid all connects first voltage source, the source electrode of the first NMOS tube, the second NMOS tube source electrode ground connection；The drain electrode of first NMOS tube connects
Connect the drain electrode of the drain electrode and third PMOS tube of the first PMOS tube；The drain electrode and the of drain electrode the second PMOS tube of connection of second NMOS tube
The drain electrode of four PMOS tube；The grid of first PMOS tube accesses first control signal, and the source electrode of the first PMOS tube connects the 2nd PMOS
The source electrode of pipe and the source electrode of the first PMOS tube and the source electrode of the second PMOS tube all connect the drain electrode of the 5th PMOS tube；2nd PMOS
The grid of pipe accesses second control signal；The grid access third of third PMOS tube controls signal, and the source electrode of third PMOS tube connects
It connects the source electrode of the 4th PMOS tube and the source electrode of third PMOS tube and the source electrode of the 4th PMOS tube all connects the leakage of the 6th PMOS tube
Pole；The 4th control signal of grid access of 4th PMOS tube；The source electrode of 5th PMOS tube, the source electrode connection second of the 6th PMOS tube
Voltage source, the grid of the 5th PMOS tube connect the grid of the 6th PMOS tube；The first control signal, second control signal,
Three control signals and the difference control signal that the 4th control signal is the input；The second control signal is first control
The differential signal of signal processed；The 4th control signal is the differential signal that the third controls signal.
In said program, the 4th branch includes first resistor, second resistance, 3rd resistor, the 5th branch packet
Include third NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 7th PMOS tube, the 8th PMOS tube, the 9th PMOS tube, the tenth PMOS
Pipe；
One end of first resistor connects the leakage of the drain electrode of the first NMOS tube, the drain electrode and third PMOS tube of the first PMOS tube
Pole, the other end connect second resistance；Second resistance one end connects the drain electrode of the second NMOS tube, the drain electrode and the 4th of the second PMOS tube
The drain electrode of PMOS tube, the other end connect first resistor；One end of 3rd resistor connect the grid of the 4th NMOS tube, first resistor and
Second resistance, the other end connect tertiary voltage source；The source electrode and the 5th NMOS of drain electrode the 4th NMOS tube of connection of third NMOS tube
The grid of the source electrode of pipe, third NMOS tube connects first voltage source, the source electrode ground connection of third NMOS tube；The grid of 7th PMOS tube
Connect the grid of the 8th PMOS tube, the grid of drain electrode the 7th PMOS tube of connection of the 7th PMOS tube, the grid of the 8th PMOS tube, the
The drain electrode of nine PMOS tube, the drain electrode of the 4th NMOS tube；The grid of tenth PMOS tube connects the grid of the 9th PMOS tube, the tenth PMOS
The grid of drain electrode the tenth PMOS tube of connection of pipe, the grid of the 9th PMOS tube, the drain electrode of the 8th PMOS tube, the leakage of the 5th NMOS tube
Pole, the grid of the 5th PMOS tube, the 6th PMOS tube grid；The source electrode of 7th PMOS tube, the source electrode of the 8th PMOS tube, the 9th
The source electrode of PMOS tube, the tenth PMOS tube source electrode all connect the second voltage source.
In said program, the voltage offset electric circuit includes the 4th resistance, the 5th resistance；
One end of 4th resistance connects the grid and the 5th resistance of the 5th NMOS tube, and the other end connects the 4th voltage source；The
Five resistance one end connect the grid and the 4th resistance of the 5th NMOS tube, other end ground connection.
In said program, the zero compensation circuit includes the 6th resistance, capacitance；
The grid of the 4th NMOS tube of one end connection of 6th resistance, first resistor, second resistance, 3rd resistor, the other end
Connect capacitance；Capacitance one end connects the 6th resistance, other end ground connection.
In said program, the resistance value of the first resistor is equal to the resistance value of the second resistance.
In said program, the breadth length ratio of first NMOS tube is equal to the breadth length ratio of second NMOS tube；The third
The breadth length ratio of NMOS tube is equal to the breadth length ratio of first NMOS tube；The breadth length ratio of 4th NMOS tube is equal to the 5th NMOS tube
Breadth length ratio；
The breadth length ratio of first PMOS tube and the breadth length ratio of the second PMOS tube, the breadth length ratio of third PMOS tube, the 4th
The breadth length ratio of PMOS tube is equal；The breadth length ratio of 5th PMOS tube is equal to the breadth length ratio of the 6th PMOS tube；7th PMOS
The breadth length ratio of pipe is equal with the breadth length ratio of the 8th PMOS tube, breadth length ratio, the breadth length ratio of the tenth PMOS tube of the 9th PMOS tube.
The embodiment of the present invention also provides a kind of processing method based on charge pump, the method includes：
Using the difference control signal of input, the differential output voltage of charge pump is generated；
Based on the differential output voltage and syntype bias voltage, feedback voltage signal is generated；
The common-mode voltage of the differential output voltage is adjusted according to the feedback voltage signal.
In said program, the method further includes：
According to the differential output voltage, the syntype bias voltage, the feedback voltage signal and the difference output
The common-mode voltage of voltage obtains feedback function；
Zero is introduced in the feedback function, carries out phase compensation.
In said program, the difference control signal using input generates the differential output voltage of charge pump, including：
According to the discharge current that the difference control signal of input, charging current and discharge current source generate, charge pump is determined
Differential output voltage；The charging current includes the charging current generated to charging current source according to the feedback voltage signal
The electric current obtained after being adjusted.
It is described to be based on the differential output voltage and syntype bias voltage, feedback voltage signal is generated, including：
Based on the differential output voltage, in the way of electric resistance partial pressure, voltage to be detected is obtained；The voltage to be detected
More than the half of the sum of the differential output voltage；
Compare the voltage to be detected and the syntype bias voltage, feedback voltage signal is generated according to comparison result.
The embodiment of the present invention provides a kind of phase-locked loop circuit again, and the phase-locked loop circuit includes：Phase frequency detector, with it is described
The charge pump of phase frequency detector connection, the low-pass filter being connect with the charge pump, the pressure being connect with the low-pass filter
Control oscillator；Wherein,
The charge pump includes charge pump main circuit, common mode feedback circuit, voltage offset electric circuit；
The charge pump main circuit generates the differential output voltage of charge pump for the difference control signal using input；
The common mode feedback circuit, the common mode for being provided based on the differential output voltage and the voltage offset electric circuit
Bias voltage generates feedback voltage signal, and the feedback voltage signal is exported to the charge pump main circuit, to be based on
State the common-mode voltage that feedback voltage signal adjusts the difference output that the charge pump main circuit generates.
In said program, the charge pump is specially any one charge pump described above.
Charge pump provided in an embodiment of the present invention, processing method and phase-locked loop circuit based on charge pump, the charge pump packet
It includes：Charge pump main circuit, common mode feedback circuit, voltage offset electric circuit；The charge pump main circuit, for the difference using input
Signal is controlled, the differential output voltage of charge pump is generated；The common mode feedback circuit, for based on the differential output voltage and
The syntype bias voltage that the voltage offset electric circuit provides generates feedback voltage signal, and the feedback voltage signal is exported
To the charge pump main circuit, to adjust the difference output electricity that the charge pump main circuit generates based on the feedback voltage signal
The common-mode voltage of pressure.As it can be seen that charge pump provided in an embodiment of the present invention is by converting the variation of differential output voltage to feedback
Voltage signal can ensure charge pump in low-voltage to adjust the differential output voltage of output based on the feedback voltage signal
The differential output voltage with higher stability and matching is generated under environment.
Description of the drawings
Fig. 1 is the composed structure schematic diagram for the charge pump that the embodiment of the present invention one provides；
Fig. 2 is the implementation process schematic diagram for the processing method based on charge pump that the embodiment of the present invention one provides；
Fig. 3 is the concrete composition structural schematic diagram for the charge pump that the embodiment of the present invention one provides；
Fig. 4 is the composed structure schematic diagram of phase-locked loop circuit provided by Embodiment 2 of the present invention.
Specific implementation mode
Embodiment one
Fig. 1 is the composed structure schematic diagram for the charge pump that the embodiment of the present invention one provides, which includes：Charge pump
Main circuit 11, common mode feedback circuit 12, voltage offset electric circuit 13；Wherein,
The charge pump main circuit 11 generates the difference output electricity of charge pump for the difference control signal using input
Pressure；
The common mode feedback circuit 12, for what is provided based on the differential output voltage and the voltage offset electric circuit 13
Syntype bias voltage generates feedback voltage signal, and the feedback voltage signal is exported to the charge pump main circuit, with base
The common-mode voltage for the differential output voltage that the charge pump main circuit generates is adjusted in the feedback voltage signal.
Wherein, the charge pump main circuit 11 includes：The first branch 111, second connect with the first branch 111
Road 112, the third branch 113 being connect with the second branch 112；
The first branch 111, as discharge current source, for providing discharge current for the second branch 112；
The third branch 113, as charging current source, for providing charging current for the second branch 112；With
And the feedback voltage signal of the output of the common mode feedback circuit 12 is received, adjust the charging current；
The second branch 112, for according to the difference control signal of input, charging current and discharge current, determining electricity
The differential output voltage of lotus pump.
The second branch 112, is specifically used for：It is provided according to the difference control signal of input, the third branch 113
The discharge current that charging current and the first branch 111 provide, determines the differential output voltage of charge pump；According to the difference of input
The electric discharge electricity that charging current and the first branch 111 after the adjustment that dividing control signal, the third branch 113 provide provide
Stream, adjusts the differential output voltage.
Here, the second branch 112 according to after the difference control signal of input, the adjustment charging current and electric discharge
Electric current adjusts the differential output voltage, it is therefore intended that by adjusting the differential output voltage of charge pump, to realize to charge pump
Differential output voltage common-mode voltage adjustment.
The common mode feedback circuit 12 includes the 4th branch 121, the 5th branch 122；
4th branch 121 in the way of electric resistance partial pressure, obtains to be checked for being based on the differential output voltage
Survey voltage；The voltage to be detected is more than the half of the sum of described differential output voltage；
5th branch 122, the common mode provided for the voltage to be detected and the voltage offset electric circuit 13
Bias voltage generates feedback voltage signal according to comparison result, and the feedback voltage signal is exported to the charge pump master
Circuit 11.
Here, when the differential output voltage changes, the difference that the charge pump main circuit generates will be caused defeated
Go out the variation of the common-mode voltage of voltage, so that the variation of the differential output voltage will be embodied in the voltage to be detected
In, therefore, the syntype bias voltage that common mode feedback circuit 12 provides the voltage offset electric circuit 13 generates anti-as reference
Feedthrough voltage signal, so that the charge pump main circuit 11 adjusts differential output voltage according to the feedback voltage signal, it is ensured that poor
Divide the stability and matching of output voltage.
Further, the charge pump 1 further includes：Zero compensation circuit 14, for the common mode feedback circuit 13
Phase compensates.
Here, the phase of the common mode feedback circuit 13 is mended by introducing zero by the zero compensation circuit 14
It repays, the stability that can further improve charge pump further increases the stability of differential output voltage.
Fig. 2 is the implementation process schematic diagram for the processing method based on charge pump that the embodiment of the present invention one provides, this method
Including：
Step 101：Using the difference control signal of input, the differential output voltage of charge pump is generated；
Specifically, the charging current and discharge current source generated according to the difference control signal of input, charging current source is produced
Raw discharge current determines the differential output voltage of charge pump；The charging current source is adjusted according to the feedback voltage signal
The charging current of generation；The charging current and described generated according to the charging current source after the difference control signal of input, adjustment
Discharge current adjusts the differential output voltage.
Step 102：Based on the differential output voltage and syntype bias voltage, feedback voltage signal is generated；
Specifically, voltage to be detected is obtained in the way of electric resistance partial pressure based on the differential output voltage；It is described to wait for
Detect the half that voltage is more than the sum of described differential output voltage；Compare the voltage to be detected and the syntype bias voltage,
Feedback voltage signal is generated according to comparison result.
Step 103：The common-mode voltage of the differential output voltage is adjusted according to the feedback voltage signal.
Further, this method further includes：
According to the differential output voltage, the syntype bias voltage, the feedback voltage signal and the difference output
The common-mode voltage of voltage obtains feedback function；
Zero is introduced in the feedback function, carries out phase compensation.
It should be noted that the processing method provided in an embodiment of the present invention based on charge pump can pass through above-mentioned charge pump
It realizes.
Fig. 3 is the concrete composition structural schematic diagram for the charge pump that the embodiment of the present invention one provides, which includes：First
NMOS tube M1, the second NMOS tube M2, the first PMOS tube M3, the second PMOS tube M4, third PMOS tube M5, the 4th PMOS tube M6,
Five PMOS tube M7, the 6th PMOS tube M8, third NMOS tube M9, the 4th NMOS tube M10, the 5th NMOS tube M11, the 7th PMOS tube
M12, the 8th PMOS tube M13, the 9th PMOS tube M14, the tenth PMOS tube M15, first resistor R1, second resistance R2,3rd resistor
R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, capacitance C；Wherein, the first NMOS tube M1, the second NMOS tube M2 are constituted
The first branch, the first PMOS tube M3, the second PMOS tube M4, third PMOS tube M5, the 4th PMOS tube M6 composition the second branches, the 5th
PMOS tube M7, the 6th PMOS tube M8 constitute third branch, i.e. the first NMOS tube M1, the second NMOS tube M2, the first PMOS tube M3, the
Two PMOS tube M4, third PMOS tube M5, the 4th PMOS tube M6, the 5th PMOS tube M7, the 6th PMOS tube M8 constitute the main electricity of charge pump
Road；First resistor R1, second resistance R2,3rd resistor R3 constitute the 4th branch, third NMOS tube M9, the 4th NMOS tube M10, the
Five NMOS tube M11, the 7th PMOS tube M12, the 8th PMOS tube M13, the 9th PMOS tube M14, the tenth PMOS tube M15 constitute the 5th
Road, i.e. first resistor R1, second resistance R2,3rd resistor R3, third NMOS tube M9, the 4th NMOS tube M10, the 5th NMOS tube
M11, the 7th PMOS tube M12, the 8th PMOS tube M13, the 9th PMOS tube M14, the tenth PMOS tube M15 constitute common mode feedback circuit；
4th resistance R4, the 5th resistance R5 constitute voltage offset electric circuit；6th resistance R6, capacitance C constitute zero compensation circuit；
Wherein, the connection relation in charge pump shown in Fig. 3 is：
In charge pump main circuit, the grid of the first NMOS tube M1 connects the grid and the first NMOS of the second NMOS tube M2
The grid of the grid of pipe M1 and the second NMOS tube M2 all connect first voltage source VDD1, the source electrode of the first NMOS tube M1, second
The source electrode of NMOS tube M2 is grounded；The leakage of the drain electrode and third PMOS tube M5 of the first PMOS tube M3 of drain electrode connection of first NMOS tube M1
Pole；The drain electrode of the drain electrode and the 4th PMOS tube M6 of the second PMOS tube M4 of drain electrode connection of second NMOS tube M2；First PMOS tube M3
The source electrode of grid access first control signal UP, the first PMOS tube M3 connect the source electrode and the first PMOS of the second PMOS tube M4
The source electrode of the source electrode of pipe M3 and the second PMOS tube M4 all connect the drain electrode of the 5th PMOS tube M7；The grid of second PMOS tube M4 accesses
Second control signal UPB；The grid access third of third PMOS tube M5 controls signal DNB, the source electrode connection of third PMOS tube M5
The source electrode and the source electrode of third PMOS tube M5 and the source electrode of the 4th PMOS tube M6 of 4th PMOS tube M6 all connects the 6th PMOS tube M8
Drain electrode；The 4th control signal DN of grid access of 4th PMOS tube M6；The source electrode of 5th PMOS tube M7, the 6th PMOS tube M8
Source electrode connects the grid of the 6th PMOS tube M8 of grid connection of the second voltage source VDD2, the 5th PMOS tube M7；First control
Signal UP, second control signal UPB, the difference control letter that the third control signals of control signal DNB and the 4th DN is the input
Number；The second control signal UPB is the differential signal of the first control signal UP；The 4th control signal DN is described
Third controls the differential signal of signal DNB.
In common mode feedback circuit, one end of first resistor R1 connects the drain electrode of the first NMOS tube M1, the first PMOS tube M3
Drain electrode and third PMOS tube M5 drain electrode, the other end connects second resistance R2；The one end second resistance R2 connects the second NMOS tube
The drain electrode of M2, the drain electrode and the 4th PMOS tube M6 of the second PMOS tube M4 drain electrode, the other end connects first resistor R1；3rd resistor
One end of R3 connects grid, first resistor R1 and the second resistance R2 of the 4th NMOS tube M6, and the other end connects tertiary voltage source
VDD3；The source electrode of the source electrode and the 5th NMOS tube M11 of the 4th NMOS tube M10 of drain electrode connection of third NMOS tube M5, the 3rd NMOS
The grid of pipe M9 connects first voltage source VDD1, the source electrode ground connection of third NMOS tube M9；The grid connection the of 7th PMOS tube M12
The grid of eight PMOS tube M13, the grid, the 8th PMOS tube M13 for connecting the 7th PMOS tube M12 that drain of the 7th PMOS tube M12
Grid, the drain electrode of the 9th PMOS tube M14, the drain electrode of the 4th NMOS tube M10；The grid of tenth PMOS tube M15 connects the 9th PMOS
The grid of pipe M14, the drain electrode connection grid of the tenth PMOS tube M15 of the tenth PMOS tube M15, the grid of the 9th PMOS tube M14, the
The drain electrode of eight PMOS tube M13, the drain electrode of the 5th NMOS tube M11, the grid of the 5th PMOS tube M7, the 6th PMOS tube M8 grid；
The source electrode of 7th PMOS tube M12, the source of the source electrode of the 8th PMOS tube M13, the source electrode of the 9th PMOS tube M14, the tenth PMOS tube M15
Pole all connects the second voltage source VDD2.
In voltage offset electric circuit, one end of the 4th resistance R4 connects the grid and the 5th resistance R5 of the 5th NMOS tube M11,
The other end connects the 4th voltage source VDD4；5th one end resistance R5 connects the grid and the 4th resistance R4 of the 5th NMOS tube M11, separately
One end is grounded.
In zero compensation circuit, one end of the 6th resistance R6 connect the grid of the 4th NMOS tube M10, first resistor R1,
Second resistance R2,3rd resistor R3, the other end connect capacitance C；The one end capacitance C connects the 6th resistance R6, other end ground connection.
Here, the first NMOS tube M1, the second NMOS tube M2, the first PMOS tube M3, the second PMOS tube M4, the 3rd PMOS
The charge pump main circuit that pipe M5, the 4th PMOS tube M6, the 5th PMOS tube M7, the 6th PMOS tube M8 are constituted is full symmetric knot
Structure, the charge pump main circuit are converted into the charging and discharging currents to charge pump output capacitance by the charge and discharge electric signal that PFD is exported,
Then voltage signal is changed by LPF, to control LCVCO, to realize tracking of the PLL to phase and frequency, and
Generate stable clock signal；The first branch that first NMOS tube M1, the second NMOS tube M2 are constituted is first voltage source VDD1's
Under effect, as discharge current source, pull-down current is provided for charge pump, i.e., for by the first PMOS tube M3, the second PMOS tube M4,
The second branch that three PMOS tube M5, the 4th PMOS tube M6 are constituted provides discharge current；First PMOS tube M3, the second PMOS tube M4,
Third PMOS tube M5, input terminals of the 4th PMOS tube M6 as charge pump, the charge and discharge control signal of access PFD outputs；But it needs
It should be noted that the breadth length ratio of the first NMOS tube M1 should be equal to the breadth length ratio of the second NMOS tube M2, the width of the first PMOS tube M3 is long
It is more equal than with the breadth length ratio M4 of the second PMOS tube, the breadth length ratio of third PMOS tube M5, the breadth length ratio of the 4th PMOS tube M6, the 5th
The breadth length ratio of PMOS tube M7 is equal to the breadth length ratio of the 6th PMOS tube M8.
In Fig. 3, UP controls signal with two pairs of Differential Inputs that UPB, DN and DNB are PFD outputs, for controlling charge pump
Charge and discharge；VOUTP and VOUTN is differential output voltage, and output difference signal is VOUT=VOUTP-VOUTN.Work as UP=DN
When, charge pump is in common mode hold mode, i.e. VOUT=0；Work as UP=1, when DN=0, charge pump is charged state, i.e. on VOUT
It rises；Work as UP=0, when DN=1, charge pump is discharge condition, i.e. VOUT declines.Wherein, UPB, DNB points of the differential signal of UP, DN
Do not control the second PMOS tube M4, third PMOS tube M5, the second PMOS tube M4, third PMOS tube M5 drain electrode interconnection in
The output node of VOUTP and VOUTN fully accelerates the speed of charge and discharge during charge and discharge.In the present embodiment, with described first
Control signal UP is charging control signal, the 4th control signal DN is discharge control signal, second control signal UPB is the first control
It is illustrated for the differential signal of signal UP processed, the differential signal that third control signal DNB is the 4th control signal DN.
Here, by first resistor R1, second resistance R2,3rd resistor R3, third NMOS tube M9, the 4th NMOS tube M10,
The common mode that five NMOS tube M11, the 7th PMOS tube M12, the 8th PMOS tube M13, the 9th PMOS tube M14, the tenth PMOS tube M15 are constituted
Feedback circuit provides stable common mode operating point for charge pump, it is ensured that the stability of charge pump.Wherein, 3rd resistor R3 with
The mode of electric resistance partial pressure makes the common-mode voltage VCM that the grid of the 4th NMOS tube M10 obtains be more than charge pump output common mode voltage
VCMOUT, wherein VCMOUT=(VOUTP+VOUTN)/2.It should be noted that the resistance value of first resistor R1 should be equal to the second electricity
Hinder the resistance value of R2；The size of tertiary voltage source VDD3 can need the resistance value and charge pump according to actual conditions such as first resistor R1
The factors such as the size of output common mode voltage VCMOUT are rationally arranged；The breadth length ratio of third NMOS tube M9 is equal to the first NMOS tube
The breadth length ratio of M1；The breadth length ratio of 7th PMOS tube M12 and the breadth length ratio of the 8th PMOS tube, the breadth length ratio of the 9th PMOS tube, the tenth
The breadth length ratio of PMOS tube is equal；The breadth length ratio of 4th NMOS tube M10 is equal to the breadth length ratio of the 5th NMOS tube M11；Third NMOS tube
M9 and the first NMOS tube M1 constitute mirror, and the breadth length ratio of the two is equal, and N times of mirror image is realized by finger or M.
Here, the resistance value with the resistance value of the 5th resistance R5 of the 4th resistance R4 can be equal, can not also be equal；The third
Voltage source VDD3 and the 4th voltage source VDD4 can be the same voltage source, can also be different voltages source, i.e., the described third electricity
The voltage swing that potential source VDD3 and the 4th voltage source VDD4 are provided both can be identical, can not also be identical；In practical applications,
Sizeable tertiary voltage source VDD3 and the 4th voltage source VDD4 can be selected according to actual needs.
Here, charge pump is in normal work, when mutually keeping equilibrium state between UP and DN, charge pump output common mode
Voltage VCMOUT keeps stablizing so that the input voltage VCM of the grid of the 4th NMOS tube M10 is equal to the grid of the 5th NMOS tube M11
The syntype bias voltage that the input voltage VB of pole, that is, voltage offset electric circuit provides, at this point, feedback caused by common mode feedback circuit
The charging current that voltage signal VFB will not adjust the 5th PMOS tube M7, the 6th PMOS tube M8 is exported, that is, keep differential output voltage
Balance between VOUTP, VOUTN；When causing differential output voltage VOUTP, VOUTN to change because of the variation of UP and DN, by
The input voltage VCM of the grid of the 4th NMOS tube M10 can be made to occur accordingly in differential output voltage VOUTP, VOUTN variation
Variation, and the input voltage VB of the grid of the 5th NMOS tube M11 stablizes constant, this will lead to the grid of the 4th NMOS tube M10
It is unbalance between the input voltage VB of the grid of the input voltage VCM and the 5th NMOS tube M11 of pole, then it can make common mode feedback circuit will
The variation of VCM is exported by feedback voltage signal VFB and gives charge pump main circuit, so that charge pump main circuit adjusts the 5th PMOS tube
The charging current of M7, the 6th PMOS tube M8 change differential output voltage VOUTP, VOUTN, to make the 4th NMOS tube M10's again
The input voltage VB of grids of the input voltage VCM of grid equal to the 5th NMOS tube M11.
In this implementation, the first NMOS tube M1, the second NMOS tube M2, the first PMOS tube M3, the second PMOS tube M4, the 3rd PMOS
The charge pump main circuit that pipe M5, the 4th PMOS tube M6, the 5th PMOS tube M7, the 6th PMOS tube M8 are constituted, which controls Differential Input, to be believed
Number differential output signal VOUTP and VOUTN, first resistor R1, second resistance R2, third are converted into UP and UPB, DN and DNB
Resistance R3, third NMOS tube M9, the 4th NMOS tube M10, the 5th NMOS tube M11, the 7th PMOS tube M12, the 8th PMOS tube M13,
The common mode feedback circuit that 9th PMOS tube M14, the tenth PMOS tube M15 are constituted is obtained according to differential output signal VOUTP and VOUTN
The voltage to be detected i.e. input voltage VCM of the grid of the 4th NMOS tube M10 converts the variation of VCM to feedback voltage signal VFB
It feeds back to charge pump main circuit and carries out common mode regulation, so that differential output signal not only has higher stability, but also with very
Good matching.Charge pump provided in this embodiment can be applied to phase-locked loop circuit, clock data recovery circuit, memory
In the integrated circuits such as circuit reading/reading circuit.
Embodiment two
Fig. 4 is the composed structure schematic diagram of phase-locked loop circuit provided by Embodiment 2 of the present invention, which includes：
Charge pump 1, phase frequency detector 2, low-pass filter 3, voltage controlled oscillator 4；Wherein,
The phase frequency detector 2, the output signal of reference signal and the voltage controlled oscillator 4 for comparing input are raw
At comparison result；
The charge pump 1, for adjusting output voltage according to the comparison result of the phase frequency detector 2；
The low-pass filter 3 is filtered for the output voltage to the charge pump 1；
Voltage controlled oscillator 4, the frequency for adjusting output signal according to 3 filtered output voltage of the low-pass filter
Rate.
Here, the operation principle of phase-locked loop circuit shown in Fig. 4 is：When the phase frequency detector 2 detect it is described voltage-controlled
When the frequency of the output signal of oscillator 4 is less than the frequency of the reference signal, the charge pump 1 increases the charge pump 1
Output voltage, the output voltage export direct current part after the low-pass filter 3 is filtered, described voltage-controlled to shake
Swing the frequency that output signal is improved under the control of voltage of the frequency of the output signal of device 4 after the raising.Conversely, when described
It is described when phase frequency detector 2 detects that the frequency of the output signal of the voltage controlled oscillator 4 is more than the frequency of the reference signal
Charge pump 1 reduces the output voltage of the charge pump 1, and after filtered, the voltage controlled oscillator 4 is reduced according to the voltage of reduction
The frequency of output signal；By adjusting repeatedly, until the frequency of the output signal of the voltage controlled oscillator 4 is believed equal to the benchmark
Number frequency when, the output signal of the voltage controlled oscillator 4 is locked.
Here, in two input signals of the phase frequency detector 2, the output signal of the voltage controlled oscillator 4 can be with
It is the signal obtained after the signal exported to the voltage controlled oscillator 4 divides；The charge pump 1 can be above-mentioned reality
Apply any one charge pump in example one.
The foregoing is only a preferred embodiment of the present invention, is not intended to limit the scope of the present invention.It is all
All any modification, equivalent and improvement made by within the spirit and scope of the present invention etc. are all contained in the protection model of the present invention
Within enclosing.
Claims (16)
1. a kind of charge pump, which is characterized in that the charge pump includes：Charge pump main circuit, common mode feedback circuit, voltage bias
Circuit；Wherein,
The charge pump main circuit generates the differential output voltage of charge pump for the difference control signal using input；
The common mode feedback circuit, the syntype bias for being provided based on the differential output voltage and the voltage offset electric circuit
Voltage generates feedback voltage signal, and the feedback voltage signal is exported to the charge pump main circuit, described anti-to be based on
Feedthrough voltage signal adjusts the common-mode voltage for the differential output voltage that the charge pump main circuit generates.
2. charge pump according to claim 1, which is characterized in that the charge pump further includes：Zero compensation circuit is used for
The phase of the common mode feedback circuit is compensated.
3. charge pump according to claim 1 or 2, which is characterized in that the charge pump main circuit include the first branch, with
The second branch of the first branch connection, the third branch being connect with the second branch；Wherein,
The first branch, as discharge current source, for providing discharge current for the second branch；
The third branch, as charging current source, for providing charging current for the second branch；And described in reception
The feedback voltage signal of common mode feedback circuit output, adjusts the charging current；
The second branch, for according to the difference control signal of input, charging current and discharge current, determining the difference of charge pump
Divide output voltage.
4. charge pump according to claim 3, which is characterized in that the common mode feedback circuit includes the 4th branch, the 5th
Branch；Wherein,
4th branch, for obtaining voltage to be detected in the way of electric resistance partial pressure based on the differential output voltage；
The voltage to be detected is more than the half of the sum of described differential output voltage；
5th branch is used for the syntype bias voltage that the voltage to be detected and the voltage offset electric circuit provide,
Feedback voltage signal is generated according to comparison result, and the feedback voltage signal is exported to the charge pump main circuit.
5. charge pump according to claim 4, which is characterized in that
The first branch includes the first NMOS tube, the second NMOS tube, and the second branch includes the first PMOS tube, the 2nd PMOS
Pipe, third PMOS tube, the 4th PMOS tube, the third branch include the 5th PMOS tube, the 6th PMOS tube；
The grid of first NMOS tube connects the grid of the second NMOS tube and the grid of the grid of the first NMOS tube and the second NMOS tube
All connect first voltage source, the source electrode of the first NMOS tube, the second NMOS tube source electrode ground connection；The drain electrode connection the of first NMOS tube
The drain electrode of the drain electrode and third PMOS tube of one PMOS tube；The drain electrode and the 4th of drain electrode the second PMOS tube of connection of second NMOS tube
The drain electrode of PMOS tube；The grid of first PMOS tube accesses first control signal, and the source electrode of the first PMOS tube connects the second PMOS tube
Source electrode and the source electrode of the first PMOS tube and the source electrode of the second PMOS tube all connect the drain electrode of the 5th PMOS tube；Second PMOS tube
Grid access second control signal；The grid access third of third PMOS tube controls signal, the source electrode connection of third PMOS tube
The source electrode and the source electrode of third PMOS tube and the source electrode of the 4th PMOS tube of 4th PMOS tube all connect the drain electrode of the 6th PMOS tube；
The 4th control signal of grid access of 4th PMOS tube；The source electrode of 5th PMOS tube, the second electricity of source electrode connection of the 6th PMOS tube
Potential source, the grid of the 5th PMOS tube connect the grid of the 6th PMOS tube；The first control signal, second control signal, third
Signal and the 4th control signal are controlled as the difference control signal of the input；The second control signal is first control
The differential signal of signal；The 4th control signal is the differential signal that the third controls signal.
6. charge pump according to claim 5, which is characterized in that
4th branch includes first resistor, second resistance, 3rd resistor, and the 5th branch includes third NMOS tube,
Four NMOS tubes, the 5th NMOS tube, the 7th PMOS tube, the 8th PMOS tube, the 9th PMOS tube, the tenth PMOS tube；
One end of first resistor connects the drain electrode of the drain electrode of the first NMOS tube, the drain electrode and third PMOS tube of the first PMOS tube, separately
One end connects second resistance；Second resistance one end connects the drain electrode of the second NMOS tube, the drain electrode of the second PMOS tube and the 4th PMOS
The drain electrode of pipe, the other end connect first resistor；One end of 3rd resistor connects the grid of the 4th NMOS tube, first resistor and second
Resistance, the other end connect tertiary voltage source；The source electrode and the 5th NMOS tube of drain electrode the 4th NMOS tube of connection of third NMOS tube
The grid of source electrode, third NMOS tube connects first voltage source, the source electrode ground connection of third NMOS tube；The grid of 7th PMOS tube connects
The grid of 8th PMOS tube, the grid of drain electrode the 7th PMOS tube of connection of the 7th PMOS tube, the grid of the 8th PMOS tube, the 9th
The drain electrode of PMOS tube, the drain electrode of the 4th NMOS tube；The grid of tenth PMOS tube connects the grid of the 9th PMOS tube, the tenth PMOS tube
The drain electrode connection grid of the tenth PMOS tube, the grid of the 9th PMOS tube, the drain electrode of the 8th PMOS tube, the leakage of the 5th NMOS tube
Pole, the grid of the 5th PMOS tube, the 6th PMOS tube grid；The source electrode of 7th PMOS tube, the source electrode of the 8th PMOS tube, the 9th
The source electrode of PMOS tube, the tenth PMOS tube source electrode all connect the second voltage source.
7. charge pump according to claim 6, which is characterized in that
The voltage offset electric circuit includes the 4th resistance, the 5th resistance；
One end of 4th resistance connects the grid and the 5th resistance of the 5th NMOS tube, and the other end connects the 4th voltage source；5th electricity
Hinder grid and the 4th resistance that one end connects the 5th NMOS tube, other end ground connection.
8. the charge pump described according to claim 6 or 7, which is characterized in that the zero compensation circuit includes the 6th resistance, electricity
Hold；
The grid of the 4th NMOS tube of one end connection of 6th resistance, first resistor, second resistance, 3rd resistor, other end connection
Capacitance；Capacitance one end connects the 6th resistance, other end ground connection.
9. charge pump according to claim 6, which is characterized in that the resistance value of the first resistor is equal to the second resistance
Resistance value.
10. charge pump according to claim 6, which is characterized in that
The breadth length ratio of first NMOS tube is equal to the breadth length ratio of second NMOS tube；The breadth length ratio etc. of the third NMOS tube
In the breadth length ratio of first NMOS tube；The breadth length ratio of 4th NMOS tube is equal to the breadth length ratio of the 5th NMOS tube；
The breadth length ratio of first PMOS tube and the breadth length ratio of the second PMOS tube, the breadth length ratio of third PMOS tube, the 4th PMOS tube
Breadth length ratio it is equal；The breadth length ratio of 5th PMOS tube is equal to the breadth length ratio of the 6th PMOS tube；The width of 7th PMOS tube
Length is more equal than with the breadth length ratio of the 8th PMOS tube, breadth length ratio, the breadth length ratio of the tenth PMOS tube of the 9th PMOS tube.
11. a kind of processing method based on charge pump, which is characterized in that the method includes：
Using the difference control signal of input, the differential output voltage of charge pump is generated；
Based on the differential output voltage and syntype bias voltage, feedback voltage signal is generated；
The common-mode voltage of the differential output voltage is adjusted according to the feedback voltage signal.
12. according to the method for claim 11, which is characterized in that the method further includes：
According to the differential output voltage, the syntype bias voltage, the feedback voltage signal and the differential output voltage
Common-mode voltage obtain feedback function；
Zero is introduced in the feedback function, carries out phase compensation.
13. method according to claim 11 or 12, which is characterized in that the difference control signal using input, production
The differential output voltage of raw charge pump, including：
According to the discharge current that the difference control signal of input, charging current and discharge current source generate, the difference of charge pump is determined
Divide output voltage；The charging current includes being carried out to the charging current that charging current source generates according to the feedback voltage signal
The electric current obtained after adjustment.
14. according to the method for claim 11, which is characterized in that described to be based on the differential output voltage and syntype bias
Voltage generates feedback voltage signal, including：
Based on the differential output voltage, in the way of electric resistance partial pressure, voltage to be detected is obtained；The voltage to be detected is more than
The half of the sum of the differential output voltage；
Compare the voltage to be detected and the syntype bias voltage, feedback voltage signal is generated according to comparison result.
15. a kind of phase-locked loop circuit, which is characterized in that the phase-locked loop circuit includes：Phase frequency detector and the frequency and phase discrimination
The charge pump of device connection, the low-pass filter being connect with the charge pump, the voltage controlled oscillator being connect with the low-pass filter；
Wherein,
The charge pump includes charge pump main circuit, common mode feedback circuit, voltage offset electric circuit；
The charge pump main circuit generates the differential output voltage of charge pump for the difference control signal using input；
The common mode feedback circuit, the syntype bias for being provided based on the differential output voltage and the voltage offset electric circuit
Voltage generates feedback voltage signal, and the feedback voltage signal is exported to the charge pump main circuit, described anti-to be based on
Feedthrough voltage signal adjusts the common-mode voltage for the difference output that the charge pump main circuit generates.
16. phase-locked loop circuit according to claim 15, which is characterized in that the charge pump be specially claim 2 to
10 any one of them charge pumps.
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| CN201710194256.4A CN108667456A (en) | 2017-03-28 | 2017-03-28 | A kind of charge pump, processing method and phase-locked loop circuit based on charge pump |
| PCT/CN2018/080067 WO2018177195A1 (en) | 2017-03-28 | 2018-03-22 | Charge pump, charge pump-based processing method and phase-locked loop circuit, and storage medium |
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| CN110943738A (en) * | 2019-10-15 | 2020-03-31 | 芯创智（北京）微电子有限公司 | Inductance-capacitance voltage-controlled oscillator with adjustable common-mode voltage of output clock |
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