CN101888178B - Charge pump circuit used for reducing current mismatch at extra-low voltage in phase-locked loop - Google Patents
Charge pump circuit used for reducing current mismatch at extra-low voltage in phase-locked loop Download PDFInfo
- Publication number
- CN101888178B CN101888178B CN201010202381A CN201010202381A CN101888178B CN 101888178 B CN101888178 B CN 101888178B CN 201010202381 A CN201010202381 A CN 201010202381A CN 201010202381 A CN201010202381 A CN 201010202381A CN 101888178 B CN101888178 B CN 101888178B
- Authority
- CN
- China
- Prior art keywords
- switch
- pmos device
- links
- pull
- pmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 4
- 230000000295 complement effect Effects 0.000 claims description 6
- 230000007423 decrease Effects 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 238000007599 discharging Methods 0.000 abstract description 21
- 230000000694 effects Effects 0.000 description 5
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
Images
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Electronic Switches (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses a charge pump circuit used for reducing current mismatch at an extra-low voltage in a phase-locked loop. The charge pump comprises a gate current mirror, a pull-up circuit, a pull-down circuit and an operational amplifier, wherein the gate current mirror consists of a first p-metal oxide semiconductor (PMOS) device, a second PMOS device and a first n-metal oxide semiconductor (NMOS) device; the pull-up circuit consists of a third PMOS device, a fourth PMOS device, a first switch and a second switch; the pull-down circuit consists of a second NMOS device, a third NMOS device, a third switch and a fourth switch; the fourth PMOS device realizes the functions of both a pull-up current tube and a pull-up switching tube; and the third NMOS device realizes the functions of both a pull-down current tube and a pull-down switching tube, so that the charge pump circuit realizes the parallel connection of the switching tubes and the current tubes and is suitable to work in an environment of low power supply voltage. A feedback loop formed by the operation amplifier increases the output impedance and reduces the mismatch of charging and discharging current.
Description
Technical field
The present invention relates to technical field of integrated circuits, be specifically related to a kind of charge pump circuit that is used for phase-locked loop utmost point low voltage operating decline low current mismatch.
Background technology
Charge pump phase lock loop (CP-PLL) has characteristics such as high speed, low noise, thereby becomes the most general now a kind of phase-locked loop circuit, is widely used in various telecommunication circuits, frequency synthesizer and the clock recovery circuitry.Charge pump circuit plays important effect in CP-PLL; Its major function is that integration is carried out in the pulse of reflection output signal and input signal phase difference; And with the result of integration form output, then with the frequency of this output voltage control voltage controlled oscillator with voltage variety.
Along with microelectric technique develops to the nano-scale direction, require IC design more and more to draw close to low-voltage (less than 1.0 volts), low-power consumption.Therefore, the Design of Simulating Circuits of Traditional use cascade structure no longer is applicable to low voltage operating usually, and it can not provide the requirement of satisfying signal swing between enough voltage headroom.Likewise, the charge pump circuit of phase-locked loop also is faced with output voltage range, the current mismatch of charge pump and the problem of clock feedthrough mismatch that is difficult under low-voltage, obtain broad.
In traditional charge pump circuit, usually with metal-oxide-semiconductor discharging and recharging as the switch controlled charge pump circuit.When the design charge pump, switching tube can be placed on drain terminal (shown in Fig. 1 (a)), source end (shown in Fig. 1 (b)) or the grid end (shown in Fig. 1 (c)) of tube of current.
When the MOS switching tube was placed on drain electrode, switching tube was connected with tube of current, and under very low operation voltage, power voltage insufficient is to drive two cascade metal-oxide-semiconductors.In addition, adopt the charge pump of this structure, because the output of switching tube and charge pump directly links to each other, it is particularly evident that its electric charge is shared effect, and tube of current experienced the process of linearity to the saturation region, causes the charging and discharging currents mismatch easily.
When the MOS switching tube is placed on source electrode; Though switching tube does not directly link to each other with output; Receive the influence of electric charge injection effect less, and tube of current always works in the saturation region, can eliminate electric charge and share effect; But switching tube is also connected with tube of current, exists the not enough problem of supply voltage driving force equally.
When the MOS switching tube was placed on grid, switching tube was parallelly connected with tube of current, but the charge pump output impedance of this kind structure is less, receives output voltage influence easily, thereby made the charging and discharging currents mismatch, and the reference that has increased on the CP-PLL output spectrum is spuious.
Therefore traditional charge pump circuit exists the serious problem of current mismatch under the operational environment of utmost point low supply voltage.
Summary of the invention
The invention provides a kind of charge pump circuit that is used for charge pump phase lock loop (CP-PLL), can when utmost point operation at low power supply voltage, reduces charging current and discharging current mismatch.
A kind of charge pump circuit comprises: current mirror, pull-up circuit, pull-down circuit and operational amplifier, wherein,
Described current mirror is made up of a PMOS device, the 2nd PMOS device and first nmos device; Wherein, the drain electrode of a PMOS device links to each other with the grid of a PMOS device, and the grid with the 2nd PMOS links to each other again; The source electrode of the one PMOS device all links to each other with supply voltage with the source electrode of the 2nd PMOS; The drain electrode of the 2nd PMOS device links to each other with the drain electrode of first nmos device, and the grid of first nmos device links to each other with the drain electrode of the 2nd PMOS device, and the source electrode of first nmos device links to each other with ground;
Described pull-up circuit; Be used to provide pull-up current to improve the voltage of charge pump output, comprise: as the 3rd PMOS device in pull-up current source, as on draw the 4th PMOS device of controlled xtal pipe and the charging control switch of forming by first switch and second switch.
Wherein, the grid of the 3rd PMOS device links to each other with an end of the output of described operational amplifier, first switch, and the source electrode of the 3rd PMOS device links to each other with supply voltage, and the drain electrode of the 3rd PMOS device links to each other with the negative input end of described operational amplifier; One end of the source electrode of the 4th PMOS device and second switch all links to each other with described supply voltage, and the grid of the 4th PMOS device links to each other with the other end of first switch, the other end of second switch, and the drain electrode of the 4th PMOS device links to each other with the charge pump output node.First switch is by charging signals UP control, and second switch is by complementary signal
control of charging signals.Charging signals UP is the switching signal that is produced by phase frequency detector.
It is thus clear that the grid in pull-up current source links to each other with the output of operational amplifier, and the gate bias voltage in pull-up current source is provided by operational amplifier output terminal; On draw controlled xtal pipe (the 4th PMOS device) both to realize the function of pull-up current pipe (promptly through to pull-up current pipe injection current, can be pulled to supply voltage to output voltage); Realized again last drag switch pipe function (promptly through opening and shutting off the drag switch pipe, can control whether injection current of pull-up current pipe, realize circuit on draw); In the charging control switch, first switch works to isolate the bias voltage of tube of current, and second switch is used to control and draws opening and shutting off of controlled xtal pipe, thereby the charging of control charge pump plays signal controlling.
Described pull-down circuit; Be used to provide pull-down current to reduce the voltage of charge pump output, comprise: as second nmos device in pull-down current source, as the 3rd nmos device of drop-down controlled xtal pipe and the discharge control switch of forming by the 3rd switch and the 4th switch.Wherein, The grid of second nmos device links to each other with the grid of the NMOS pipe of described current mirror and an end of the 3rd switch; The source electrode of second nmos device links to each other with ground, and the drain electrode of second nmos device links to each other with the drain terminal of the 3rd PMOS device of the negative input end of operational amplifier and described pull-up circuit; One end of the source electrode of the 3rd nmos device, the 4th switch all links to each other with ground, and the grid of the 3rd nmos device links to each other with the other end of the 3rd switch, the other end of the 4th switch, and the drain electrode of the 3rd nmos device links to each other with the charge pump output node.The 3rd switch is by discharge signal DN control, and the 4th switch is by complementary signal
control of discharge signal.Discharge signal DN is the switching signal that is produced by phase frequency detector.
It is thus clear that the grid in pull-down current source links to each other with the grid of current mirror, constitute common gate structure, the pull-down current source equates with the grid terminal voltage of current mirror like this, makes the electric current in pull-down current source equate with the electric current of current mirror, thereby to current mirror bias current is provided.Drop-down controlled xtal pipe (the 3rd nmos device) had both realized that the function of pull-down current pipe (promptly through pull-down current pipe output current, can be pulled down to ground to output voltage; The function (promptly through opening and shutting off the pipe that pulls down switch, can control whether output current of pull-down current pipe, realization circuit drop-down) of pipe has realized again pulling down switch; In the discharge control switch, the 3rd switch is used to isolate the bias voltage of current mirror, and the 4th switch is used to control opening and shutting off of drop-down controlled xtal pipe (the 3rd nmos device), thereby the discharge of control charge pump plays signal controlling.
Described operational amplifier is used to adjust the voltage of output.Described operational amplifier has positive input terminal, negative input end and an output; The node place of the negative input end of described operational amplifier and pull-up circuit and pull-down circuit links together; The positive input terminal of described operational amplifier links to each other with the charge pump output node, and the output of described operational amplifier links to each other with the grid of the 3rd PMOS device, an end of first switch.Operational amplifier makes that through negative feedback the voltage difference between the operational amplifier input is minimum, thereby reduces the mismatch of pull-up current and pull-down current.
The operation principle of charge pump circuit of the present invention is following:
When charging signals UP is high; When discharge signal DN is low; First switch and the 4th switch closure, second switch and the 3rd switch break off, and then the output of the grid of the grid of the 3rd PMOS device, the 4th PMOS device and operational amplifier is connected; By operational amplifier output terminal bias voltage is provided, the 4th PMOS break-over of device; The grid of second nmos device and the 3rd nmos device grid break off, and the grid voltage of second nmos device does not influence the ground connection of the 3rd nmos device grid, and the 3rd nmos device turn-offs, and this moment, output node voltage raise.
And charging signals UP is low; When discharge signal DN is high; Second switch and the 3rd switch closure, first switch and the 4th switch break off, and then the grid of the 3rd PMOS device and the 4th PMOS device grids break off; The output voltage of operational amplifier does not influence the 4th PMOS device grids and connects supply voltage, and the 4th PMOS device turn-offs; The grid of second nmos device links to each other with the grid of first nmos device with the 3rd nmos device grid, by current mirror bias voltage is provided, the 3rd nmos device conducting, and this moment, output node voltage reduced.
When charging signals UP is low; When discharge signal DN is low; First switch and the 3rd switch break off, second switch and the 4th switch closure, and then the grid of the 3rd PMOS device and the 4th PMOS device grids break off; The output voltage of operational amplifier does not influence the 4th PMOS device grids and connects supply voltage, and the 4th PMOS device turn-offs; The grid of second nmos device and the 3rd nmos device grid break off, and the grid voltage of second nmos device does not influence the ground connection of the 3rd nmos device grid, and the 3rd nmos device turn-offs, and this moment, output node voltage remained unchanged.
When the UP signal is high; The DN signal is that high state has only the very of short duration time, first switch and the 3rd switch closure, and second switch and the 4th switch break off; This moment the 4th PMOS break-over of device; The also conducting of the 3rd nmos device needs charging current and discharging current to have excellent matching this moment, could guarantee that like this output node voltage remains unchanged.In the high speed charge pump circuit, charging and discharging currents often requires accurately equal, yet considers the restriction of some factors such as power consumption, and charging and discharging currents is generally all very little.
The Spectre analog result of circuit of the present invention shows: under the utmost point low circuit supply voltage of 0.5V, output voltage amplitude is broad still, and in 0mV～490mV scope, charging current and discharging current have good matching degree.
Compared with prior art, the present invention has following beneficial technical effects:
Because no matter in pull-up circuit still is pull-down circuit; The all shared MOS device of switching tube and tube of current (controlled xtal pipe) adopts control signal to control the grid of controlled xtal pipe, and two node sides of switching tube and tube of current are identical; Realized that switching tube is parallelly connected with tube of current; Thereby the reducing of voltage drop when being implemented in the discharging and recharging of charge pump, and providing between abundant voltage headroom makes the output voltage range that under low-voltage, can obtain broad.Simultaneously, introduce the feedback control loop that operational amplifier is formed, charge pump output impedance is increased, be not subject to output voltage influence, thereby reduced the mismatch of charging and discharging currents.Also adopt isolating switch, can under the situation that switching tube turn-offs, isolate the influence of bias voltage switching tube.
Charge pump circuit of the present invention can be operated under the utmost point low-voltage (0.5V), and output voltage charging current and discharging current in 0mV～490mV scope all have good coupling.
Description of drawings
Fig. 1 is the electrical block diagram of three kinds of conventional charge pump circuit;
Fig. 2 is the electrical block diagram of charge pump circuit of the present invention;
Fig. 3 is the Spectre analog result sketch map of charge pump circuit of the present invention.
Embodiment
Like the circuit structure of the described three kinds of traditional charge pump circuits of Fig. 1, adopt metal-oxide-semiconductor discharging and recharging as the switch controlled charge pump circuit.
Shown in Fig. 1 (a), the MOS switching tube is placed on drain electrode, and switching tube is connected with tube of current, and the output of switching tube and charge pump directly links to each other.Under very low operation voltage, power voltage insufficient to be driving two cascade metal-oxide-semiconductors, and tube of current experienced linear process to the saturation region, causes the charging and discharging currents mismatch easily.
Shown in Fig. 1 (b), the MOS switching tube is placed on source electrode, and switching tube is connected with tube of current, under very low operation voltage, exists the not enough problem of supply voltage driving force equally.
Shown in Fig. 1 (c), the MOS switching tube is placed on grid, and switching tube is parallelly connected with tube of current; But the charge pump output impedance of this kind structure is less; Receive output voltage influence easily, thereby make the charging and discharging currents mismatch, the reference that has increased on the CP-PLL output spectrum is spuious.
Charge pump of the present invention as shown in Figure 2 comprises a plurality of transistors.Transistor is the metal-oxide semiconductor (MOS) MOS transistor.As known in those skilled in the art, there is two types MOS transistor: n channel MOS transistor (NMOS) and p channel MOS transistor (PMOS).This charge pump comprises nmos pass transistor and PMOS transistor.
Charge pump of the present invention as shown in Figure 2 comprises: the cascode current mirror that is made up of a PMOS device P1, the 2nd PMOS device P2 and the first nmos device N1; The pull-up circuit of forming by the 3rd PMOS device P3, the 4th PMOS device P4, first switch S 1 and second switch S2; The pull-down circuit and the operational amplifier OP that form by the second nmos device N2, the 3rd nmos device N3, the 3rd switch S 3 and the 4th switch S 4.
The grid of the drain electrode of the one PMOS device P1, a PMOS device P1 links to each other with the grid of the 2nd PMOS device P2;
The source electrode of the source electrode of the source electrode of the source electrode of the one PMOS device P1, the 2nd PMOS device P2, the 3rd PMOS device P3, the 4th PMOS device P4 and the end of second switch S2 link to each other with supply voltage VDD;
The drain electrode of the 2nd PMOS device P2 links to each other with the grid of the drain electrode of the first nmos device N1, the first nmos device N1, the grid of the second nmos device N2 and an end of the 3rd switch S 3;
One end of the source electrode of the source electrode of the source electrode of the first nmos device N1, the second nmos device N2, the 3rd nmos device N3 and the 4th switch S 4 links to each other with ground;
The drain electrode of the second nmos device N2 links to each other with the drain electrode of the 3rd PMOS device P3 and the negative input of operational amplifier OP;
The grid of the 3rd nmos device N3 links to each other with the other end of the 3rd switch S 3, the other end of the 4th switch S 4;
The grid of the 3rd PMOS device P3 links to each other with an end of first switch S 1, the output of operational amplifier OP;
The grid of the 4th PMOS device P4 links to each other with the other end of the other end of first switch S 1, second switch S2;
The drain electrode of the drain electrode of the 3rd nmos device N3, the 4th PMOS device P4 and the positive input of operational amplifier OP link to each other with output node Vout.
The size of above-mentioned metal-oxide-semiconductor size is confirmed by the experiment of Spectre analog simulation, selects the metal-oxide-semiconductor size under the charging and discharging currents mismatch minimum in the analog simulation experiment for use.All PMOS pipes and the NMOS pipe used among the present invention all are to adopt four common port organizations, are respectively source electrode (S), drain electrode (D), grid (G) and body end (B).The body end of above-mentioned PMOS pipe P1～P4 all meets supply voltage VDD and leaks to reduce electric current, and the body end of above-mentioned NMOS pipe N1～N3 all ground connection leaks to reduce electric current.
Operation principle: charging signals UP and discharge signal DN are respectively the switching signals that is produced by phase frequency detector; When charging signals UP is high; When discharge signal DN is low; First switch S 1 and the 4th switch S 4 closures, second switch S2 and the 3rd switch S 3 are broken off, and then the output of the grid of the grid of the 3rd PMOS device P3, the 4th PMOS device P4 and operational amplifier OP is connected; By operational amplifier OP output bias voltage is provided, as the 4th PMOS break-over of device of pull-up current pipe and last drag switch pipe; The grid of the second nmos device N2 and the 3rd nmos device N3 grid break off; The grid voltage of the second nmos device N2 does not influence the ground connection of the 3rd nmos device N3 grid; Close as pull-down current pipe and the 3rd nmos device of the pipe that pulls down switch, this moment, output node Vout voltage raise.
And charging signals UP is low; When discharge signal DN is high; Second switch S2 and the 3rd switch S 3 closures, first switch S 1 and the 4th switch S 4 are broken off, and then the grid of the 3rd PMOS device P3 and the 4th PMOS device P4 grid break off; The output voltage of operational amplifier OP does not influence the 4th PMOS device P4 grid and meets supply voltage VDD, as the 4th PMOS device shuts off of pull-up current pipe and last drag switch pipe; The grid of the second nmos device N2 links to each other with the grid of the first nmos device N1 with the 3rd nmos device N3 grid, by current mirror bias voltage is provided, and as the three nmos device conducting of pull-down current pipe with the pipe that pulls down switch, this moment, output node Vout voltage reduced.
When charging signals UP is low; When discharge signal DN is low; First switch S 1 and the 3rd switch S 3 are broken off, second switch S2 and the 4th switch S 4 closures, and then the grid of the 3rd PMOS device P3 and the 4th PMOS device P4 grid break off; The output voltage of operational amplifier OP does not influence the 4th PMOS device P4 grid and meets supply voltage VDD, as the 4th PMOS device shuts off of pull-up current pipe and last drag switch pipe; The grid of the second nmos device N2 and the 3rd nmos device N3 grid break off; The grid voltage of the second nmos device N2 does not influence the ground connection of the 3rd nmos device N3 grid; Close as pull-down current pipe and the 3rd nmos device of the pipe that pulls down switch, this moment, output node Vout voltage remained unchanged.
When charging signals UP is high; Discharge signal DN is that high state has only the very of short duration time, first switch S 1 and the 3rd switch S 3 closures, and second switch S2 and the 4th switch S 4 are broken off; This moment is as the 4th PMOS break-over of device of pull-up current pipe and last drag switch pipe; As of the three nmos device also conducting of pull-down current pipe with the pipe that pulls down switch, need this moment charging current and discharging current to have excellent matching, could guarantee that like this output node Vout voltage remains unchanged.In the high speed charge pump circuit, charging and discharging currents often requires accurately equal, yet considers the restriction of some factors such as power consumption, and charging and discharging currents is generally all very little.
Shown in Figure 3 for the Spectre analog result sketch map of circuit of the present invention; Wherein abscissa is represented the excursion of output node Vout voltage; Ordinate is represented the size of output current (charge and discharge electric current), and solid line is represented the size of discharging current (Idn), and the x line is represented the size of charging current (Iup).When circuit power voltage was 0.5V, in the output voltage amplitude scope of 0mV～490mV, charging current and discharging current had good matching degree.When output voltage was 490mV, the charge and discharge electric current was 18.8uA.
Claims (3)
1. charge pump circuit that is used for phase-locked loop utmost point low voltage operating decline low current mismatch, comprising: current mirror, pull-up circuit, pull-down circuit and operational amplifier is characterized in that:
Described current mirror is made up of a PMOS device, the 2nd PMOS device and first nmos device; Wherein, the drain electrode of a PMOS device links to each other with the grid of a PMOS device, and the grid with the 2nd PMOS device links to each other again; The source electrode of the one PMOS device all links to each other with supply voltage with the source electrode of the 2nd PMOS device; The drain electrode of the 2nd PMOS device links to each other with the drain electrode of first nmos device, and the grid of first nmos device links to each other with the drain electrode of the 2nd PMOS device, and the source electrode of first nmos device links to each other with ground;
Described pull-up circuit comprises: as the 3rd PMOS device in pull-up current source, as on draw the 4th PMOS device of controlled xtal pipe and the charging control switch of forming by first switch and second switch; Wherein, the grid of the 3rd PMOS device links to each other with an end of the output of described operational amplifier, first switch, and the source electrode of the 3rd PMOS device links to each other with supply voltage, and the drain electrode of the 3rd PMOS device links to each other with the negative input end of described operational amplifier; One end of the source electrode of the 4th PMOS device and second switch all links to each other with described supply voltage, and the grid of the 4th PMOS device links to each other with the other end of first switch, the other end of second switch, and the drain electrode of the 4th PMOS device links to each other with the charge pump output node; First switch is by charging signals UP control, and second switch is by complementary signal
control of charging signals;
Described pull-down circuit comprises: as second nmos device in pull-down current source, as the 3rd nmos device of drop-down controlled xtal pipe and the discharge control switch of being made up of the 3rd switch and the 4th switch; Wherein, The grid of second nmos device links to each other with the grid of first nmos device of described current mirror and an end of the 3rd switch; The source electrode of second nmos device links to each other with ground, and the drain electrode of second nmos device links to each other with the drain terminal of the 3rd PMOS device of the negative input end of described operational amplifier and described pull-up circuit; One end of the source electrode of the 3rd nmos device, the 4th switch all links to each other with ground, and the grid of the 3rd nmos device links to each other with the other end of the 3rd switch, the other end of the 4th switch, and the drain electrode of the 3rd nmos device links to each other with the charge pump output node;
The 3rd switch is by discharge signal DN control, and the 4th switch is by complementary signal
control of discharge signal;
Described operational amplifier has positive input terminal, negative input end and an output; Wherein, The node place of the negative input end of described operational amplifier and described pull-up circuit and pull-down circuit links together; The positive input terminal of described operational amplifier links to each other with the charge pump output node, and the output of described operational amplifier links to each other with the grid of the 3rd PMOS device, an end of first switch.
2. charge pump circuit as claimed in claim 1 is characterized in that: a described PMOS device, the 2nd PMOS device, the 3rd PMOS device, the 4th PMOS device, first nmos device, second nmos device and the 3rd nmos device be have source electrode, four port organizations of drain electrode, grid and body end; Wherein, the body end of a PMOS device, the 2nd PMOS device, the 3rd PMOS device and the 4th PMOS device all connects supply voltage, the equal ground connection of body end of first nmos device, second nmos device and the 3rd nmos device.
3. charge pump circuit as claimed in claim 1 is characterized in that: a described PMOS device, the 2nd PMOS device, the 3rd PMOS device, the 4th PMOS device, first nmos device, second nmos device and the 3rd nmos device are the metal-oxide semiconductor (MOS) MOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010202381A CN101888178B (en) | 2010-06-13 | 2010-06-13 | Charge pump circuit used for reducing current mismatch at extra-low voltage in phase-locked loop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010202381A CN101888178B (en) | 2010-06-13 | 2010-06-13 | Charge pump circuit used for reducing current mismatch at extra-low voltage in phase-locked loop |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101888178A CN101888178A (en) | 2010-11-17 |
| CN101888178B true CN101888178B (en) | 2012-10-03 |
Family
ID=43073939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010202381A Expired - Fee Related CN101888178B (en) | 2010-06-13 | 2010-06-13 | Charge pump circuit used for reducing current mismatch at extra-low voltage in phase-locked loop |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101888178B (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102790409A (en) * | 2011-05-16 | 2012-11-21 | 慧荣科技股份有限公司 | Charging and discharging device |
| CN103066833B (en) * | 2012-12-31 | 2015-03-25 | 杭州士兰微电子股份有限公司 | Switching power supply converter and circuit capable of improving charge pump charge-discharge current match degree |
| CN103001489B (en) * | 2012-12-31 | 2015-01-07 | 杭州士兰微电子股份有限公司 | Switch power inverter and circuit for improving charging and discharging current matching degree of charge pump |
| EP2779452B1 (en) * | 2013-03-13 | 2018-08-15 | Nxp B.V. | Switchable current source circuit and method |
| CN103390998B (en) * | 2013-07-30 | 2015-06-10 | 江苏物联网研究发展中心 | High-performance charge pump circuit in low-voltage charge pump phase-locked loop |
| US9473022B2 (en) * | 2015-02-10 | 2016-10-18 | Qualcomm Incorporated | Self-biased charge pump |
| CN104935163B (en) * | 2015-06-03 | 2017-07-11 | 西安电子科技大学 | A kind of four branch road charge pumps of low charge leakage |
| CN106325352B (en) * | 2015-06-30 | 2019-01-29 | 奇景光电股份有限公司 | Output-stage circuit |
| CN107896108B (en) * | 2017-12-07 | 2020-11-17 | 西安电子科技大学 | Charge pump circuit for phase locked loop |
| CN110855274B (en) * | 2019-10-23 | 2024-05-14 | 广西师范大学 | Low-loss track-to-track dynamic latching comparator |
| CN111294045B (en) * | 2020-03-20 | 2024-01-05 | 深圳芯行科技有限公司 | Circuit and method for reducing phase noise of charge pump phase-locked loop |
| CN116736924B (en) * | 2023-08-11 | 2023-11-03 | 荣湃半导体（上海）有限公司 | Voltage stabilizing source circuit with wide input range and low power consumption and electronic equipment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6288660B1 (en) * | 1998-03-18 | 2001-09-11 | Telefonaktiebolaget Lm Ericsson | BiCMOS circuit for controlling a bipolar current source |
| CN101222226A (en) * | 2007-01-10 | 2008-07-16 | 中国科学院微电子研究所 | Self-calibration charge pump circuit applied to phase-locked loop and self-calibration feedback circuit thereof |
| CN101572481A (en) * | 2009-06-11 | 2009-11-04 | 和芯微电子(四川)有限公司 | Charge pump circuit |
| CN101710784A (en) * | 2009-12-24 | 2010-05-19 | 浙江大学 | Charge pump circuit working at extra low voltage |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4425727B2 (en) * | 2004-02-27 | 2010-03-03 | Ｎｅｃエレクトロニクス株式会社 | Power circuit |
| US7551021B2 (en) * | 2005-06-22 | 2009-06-23 | Qualcomm Incorporated | Low-leakage current sources and active circuits |
-
2010
- 2010-06-13 CN CN201010202381A patent/CN101888178B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6288660B1 (en) * | 1998-03-18 | 2001-09-11 | Telefonaktiebolaget Lm Ericsson | BiCMOS circuit for controlling a bipolar current source |
| CN101222226A (en) * | 2007-01-10 | 2008-07-16 | 中国科学院微电子研究所 | Self-calibration charge pump circuit applied to phase-locked loop and self-calibration feedback circuit thereof |
| CN101572481A (en) * | 2009-06-11 | 2009-11-04 | 和芯微电子(四川)有限公司 | Charge pump circuit |
| CN101710784A (en) * | 2009-12-24 | 2010-05-19 | 浙江大学 | Charge pump circuit working at extra low voltage |
Non-Patent Citations (1)
| Title |
|---|
| 俞宏.新型低压、高速CMOS电荷泵电路.《电子器件》.2005,第28卷(第2期), * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101888178A (en) | 2010-11-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101888178B (en) | Charge pump circuit used for reducing current mismatch at extra-low voltage in phase-locked loop | |
| US7061299B2 (en) | Bidirectional level shifter | |
| US7683668B1 (en) | Level shifter | |
| TWI433442B (en) | Buck converter | |
| CN103856205B (en) | Level shifting circuit, for driving the drive circuit of high tension apparatus and corresponding method | |
| CN104201880B (en) | The low current mismatch charge pump circuit of anti-process fluctuation under phaselocked loop low-voltage | |
| WO2017173857A1 (en) | Power-on reset circuit | |
| CN106656148B (en) | Bidirectional IO circuit for preventing current from flowing backwards | |
| CN103780212A (en) | Operational amplifiers, level switching circuit and programmable gain amplifier | |
| TWI575874B (en) | Lvds driving circuit | |
| CN105099173B (en) | Charge pump | |
| WO2020237632A1 (en) | Driving circuit, digital logic circuit, and related apparatus | |
| US7301386B2 (en) | Apparatus for improved delay voltage level shifting for large voltage differentials | |
| CN109921779B (en) | Half-bridge circuit through protection circuit | |
| CN101710784B (en) | Charge pump circuit working at extra low voltage | |
| US7940108B1 (en) | Voltage level shifter | |
| CN103944556A (en) | Level transfer circuit | |
| US7133487B2 (en) | Level shifter | |
| WO2022116415A1 (en) | Level conversion circuit | |
| TWI455484B (en) | Level shifter | |
| CN107181481B (en) | Input/output receiving circuit | |
| US10833677B2 (en) | Low power logic family | |
| CN214228233U (en) | Level conversion circuit | |
| CN112751549B (en) | High-speed LVDS resistance state control circuit and control method | |
| CN115001477B (en) | Signal interface circuit for positive and negative voltage input |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121003 Termination date: 20150613 |
|
| EXPY | Termination of patent right or utility model |