CN109921779B - Half-bridge circuit through protection circuit - Google Patents

Half-bridge circuit through protection circuit Download PDF

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CN109921779B
CN109921779B CN201910149797.4A CN201910149797A CN109921779B CN 109921779 B CN109921779 B CN 109921779B CN 201910149797 A CN201910149797 A CN 201910149797A CN 109921779 B CN109921779 B CN 109921779B
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transistor
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CN109921779A (en
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周琦
程前
明鑫
施媛媛
韩晓琦
马骁勇
张宣
张波
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University of Electronic Science and Technology of China
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Abstract

The invention discloses a half-bridge circuit through protection circuit, which realizes a basic digital logic unit circuit of full GaN integration through an enhanced GaN power transistor and a GaN-based diode, namely the design of a NAND gate sub-circuit and a NOR gate sub-circuit, and further realizes the design of the half-bridge circuit through protection circuit of full GaN integration through the NAND gate sub-circuit and the NOR gate sub-circuit, thereby avoiding the through phenomenon of the half-bridge circuit when a high-side driving signal and a low-side driving signal are simultaneously high level, and laying a foundation for the digital integrated circuit of a full GaN enhanced device. In addition, the invention realizes latch design by utilizing full GaN enhancement type devices, namely enhancement type GaN power transistors and GaN-based diodes, and realizes that when input signals are changed, output signals are not easy to generate burrs due to the on/off state switching of the GaN power transistors.

Description

Half-bridge circuit through protection circuit
Technical Field
The invention belongs to the technical field of GaN power devices, and particularly relates to a design of a half-bridge circuit direct-current protection circuit.
Background
Due to the outstanding advantages of high critical breakdown electric field, high electron mobility, high two-dimensional electron gas (2DEG) concentration, good high-temperature working capacity and the like, the gallium nitride (GaN) power switch device draws wide attention in the application field of high-frequency, high-temperature and high-power-density power supply systems. With the further development of the third generation power semiconductor industry and the rise of mobile electronic products, the cost of the silicon-based GaN chip is gradually reduced, and because the GaN device can allow higher working temperature and frequency under the same condition, the high-frequency characteristic, the power density and other performances of a system power supply are improved, and the GaN device can be widely applied to the consumer electronic fields of automobiles, medical treatment and the like in the future.
The enhancement mode GaN device has three ports, gate port gate (g), drain port drain (d), and source port source(s). Assume a threshold voltage of VTHIn general VTHThe value can be designed to be 0.5V to 1.5V when the gate-source voltage V is highgs>VTHWhen the device is used, a two-dimensional electron gas channel of the device is formed, namely the drain and the source of the device start to be conducted; when the gate source voltage VgsReaches about 2V to 4V, at which time the device is fully on and the source voltage V issAbout drain voltage Vd. However, the gate-source voltage V of the enhanced GaN devicegsThe voltage can not be more than 5V, otherwise, the device is easy to damage, and the upper limit of the gate-source voltage is low, which also puts strict requirements on the driving design of the enhancement type GaN device.
However, in specific applications, even though GaN power devices have more excellent performance, after packaging, soldering and manufacturing, the excellent performance is masked by parasitic effects, so that the advantages of GaN devices are limited, and therefore, the advantages of GaN cannot be fully realized by simply replacing power core components in circuits. At this time, it becomes a key to fully exert the advantages of GaN and avoid parasitic loss caused by packaging and other factors. The most direct and objective way is to integrate GaN with the driving circuit. Related products LMG3410 and LMG5200, which are currently introduced by Texas Instruments (TI), have integrated a silicon-based driver chip of a CMOS process and a GaN power half-bridge topology, but this increases the difficulty of the process, and the performance of GaN cannot be fully developed due to the silicon-based driver. If the gate drive and enhancement mode GaN power devices are integrated together using an all-GaN based, low loss and low propagation delay can be achieved, allowing for minimal dead time, enabling optimal design of GaN based power devices.
The design of a digital circuit is designed aiming at a full GaN device driving circuit, and the basis of the digital circuit is the design of gates such as a NOT gate, a NAND gate, a NOR gate and the like. Tradition ofThe GaN digital integrated circuit adopts direct coupling field effect transistor logic to form a basic gate circuit unit of the digital integrated circuit. The conventional GaN-based NAND gate structure is shown in FIG. 1, in which the gates of enhancement-mode GaN devices E1 and E2 are the inputs of the NAND gate; the depletion mode device D1 adopts a gate-source short circuit structure, and a two-dimensional electronic air channel of the depletion mode device D1 is always conducted; when inputting signal VinAAnd VinBAt high level, two enhancement mode GaN devices E1 and E2 are turned on simultaneously, and output signal VoutIs low level; when inputting signal VinAOr VinBWhen at least one is at low level, the series circuit of the enhancement type devices E1 and E2 is broken, and the output signal VoutIs high.
The conventional GaN-based nor gate structure is shown in fig. 2, where the gates of enhancement mode GaN devices E1 and E2 are the inputs to the nor gate; the depletion mode device D1 adopts a gate-source short circuit structure, and a two-dimensional electronic air channel of the depletion mode device D1 is always conducted; when inputting signal VinAAnd VinBWhen the voltage is low, the two enhancement type GaN devices E1 and E2 are turned off simultaneously, and a signal V is outputoutIs at a high level; when inputting signal VinAOr VinBWhen at least one is at high level, at least one of the enhancement devices E1 and E2 is turned on to output a signal VoutIs low.
The conventional GaN-based NAND gate circuit and GaN-based NOR gate circuit have certain problems. The depletion type device and the enhancement type device exist at the same time, so that the difficulty of the process is increased; meanwhile, under different input voltages, due to the fact that the conduction states of the enhancement type devices E1 and E2 are changed, the output capacitors of the enhancement type devices discharge/charge through a two-dimensional electron air channel, and unstable burrs are formed on the output voltages.
Disclosure of Invention
The invention aims to provide a half-bridge circuit through-protection circuit, which realizes a NAND gate circuit and an OR gate circuit through a full GaN enhancement type device, further realizes the design of a full GaN integrated half-bridge circuit through-protection circuit, and can realize that output signals are not easy to generate burrs due to the on/off state switching of GaN power tubes when input signals are changed on the basis of effectively avoiding the through phenomenon of the half-bridge circuit when high-side drive signals and low-side drive signals are simultaneously high-level.
The technical scheme of the invention is as follows: a half-bridge circuit through protection circuit comprises 2 NAND gate sub-circuits N1 and N2 and 7 NAND gate sub-circuits N3, N4, N5, N6, N7, N8 and N9. The first input end of the NAND gate sub-circuit N1 is a first input end of a half-bridge circuit direct-connection protection circuit, the second input end of the NAND gate sub-circuit N1 is connected with the first input end of the NAND gate sub-circuit N2 to serve as a second input end of the half-bridge circuit direct-connection protection circuit, and the second input end of the NAND gate sub-circuit N2 is a third input end of the half-bridge circuit direct-connection protection circuit. An output end of the nand gate sub-circuit N1 is connected to a second input end of the nor gate sub-circuit N3 and a first input end of the nor gate sub-circuit N4, respectively, an output end of the nand gate sub-circuit N2 is connected to a second input end of the nor gate sub-circuit N4 and a first input end of the nor gate sub-circuit N5, respectively, a first input end of the nor gate sub-circuit N3 and a second input end of the nor gate sub-circuit N5 are both connected to the 5V high level VDD. An output end of the nor gate sub-circuit N3 is connected with a first input end of the nor gate sub-circuit N6, an output end of the nor gate sub-circuit N4 is connected with a second input end of the nor gate sub-circuit N6, a first input end of the nor gate sub-circuit N7, a second input end of the nor gate sub-circuit N8 and a first input end of the nor gate sub-circuit N9, an output end of the nor gate sub-circuit N5 is connected with a second input end of the nor gate sub-circuit N7, an output end of the nor gate sub-circuit N6 is connected with a first input end of the nor gate sub-circuit N8, an output end of the nor gate sub-circuit N7 is connected with a second input end of the nor gate sub-circuit N9, an output end of the nor gate sub-circuit N8 is a first output end of the half-bridge circuit direct-pass protection circuit, and an output end of the nor gate sub-circuit N9 is a second.
Preferably, the nand gate sub-circuits N1 and N2 are structurally identical, and each include 5 transistors E1, E2, E3, E4 and E5, 2 diodes D1 and D2, 2 resistors R1 and R2, and 2 capacitors C1 and C2. A gate of the transistor E3 is a first input terminal of the nand gate sub-circuit, a source thereof is connected to a drain of the transistor E4, a gate of the transistor E4 is a second input terminal of the nand gate sub-circuit, sources thereof are respectively connected to one end of the resistor R2 and a gate of the transistor E2, the other end of the resistor R2 is connected to a drain of the transistor E5, a gate of the transistor E5 is respectively connected to a cathode of the diode D2 and one end of the capacitor C2, and the other end of the capacitor C2, the source of the transistor E5 and the source of the transistor E2 are all grounded. A drain of the transistor E2 is connected to a source of the transistor E1 and one end of the capacitor C1, respectively, and serves as an output terminal of the nand gate sub-circuit, a gate of the transistor E1 is connected to the other end of the capacitor C1 and a cathode of the diode D1, a drain of the transistor E1 is connected to one end of the resistor R1, and an anode of the diode D2, a drain of the transistor E3, an anode of the diode D1, and the other end of the resistor R1 are connected to the 5V high level VDD.
Preferably, the 5 transistors E1, E2, E3, E4, and E5 are all enhancement mode GaN power transistors, and the 2 diodes D1 and D2 are all GaN based diodes.
Preferably, the transistors E3, E4 and E5, the diode D2, the capacitor C2 and the resistor R2 together form an input stage of the nand gate sub-circuit, and the transistors E1 and E2, the diode D1, the capacitor C1 and the resistor R1 together form an output stage of the nand gate sub-circuit.
Preferably, the nor sub-circuits N3, N4, N5, N6, N7, N8 and N9 are identical in structure and each include 5 transistors E6, E7, E8, E9 and E10, 2 diodes D3 and D4, 2 resistors R3 and R4, and 2 capacitors C3 and C4. The gate of the transistor E8 is a first input terminal of the nor sub-circuit, the source of the transistor E8 is connected to the source of the transistor E9, the gate of the transistor E7 and one end of the resistor R4, the gate of the transistor E9 is a second input terminal of the nor sub-circuit, the other end of the resistor R4 is connected to the drain of the transistor E10, the gate of the transistor E10 is connected to the cathode of the diode D4 and one end of the capacitor C4, and the other end of the capacitor C4, the source of the transistor E10 and the source of the transistor E7 are all grounded. A drain of the transistor E7 is connected to a source of the transistor E6 and one end of the capacitor C3, respectively, and serves as an output terminal of the nor sub-circuit, a gate of the transistor E6 is connected to the other end of the capacitor C3 and a cathode of the diode D3, a drain of the transistor E6 is connected to one end of the resistor R3, and an anode of the diode D4, a drain of the transistor E8, a drain of the transistor E9, an anode of the diode D3, and the other end of the resistor R3 are connected to the 5V high level VDD.
Preferably, the 5 transistors E6, E7, E8, E9, and E10 are all enhancement mode GaN power transistors, and the 2 diodes D3 and D4 are all GaN based diodes.
Preferably, the transistors E8, E9 and E10, the diode D4, the capacitor C4 and the resistor R4 together form an input stage of the nor gate sub-circuit, and the transistors E6 and E7, the diode D3, the capacitor C3 and the resistor R3 together form an output stage of the nor gate sub-circuit.
Preferably, the first input terminal of the half-bridge circuit direct-current protection circuit and the high-side driving gate source signal V of the half-bridge circuitgsHA second input end of the second switch is connected with an enable signal EN, and a third input end of the third switch is connected with a low-side driving grid source signal of the half-bridge circuit to be VgsLAnd a first output end and a second output end of the half-bridge circuit are connected with the half-bridge circuit.
Preferably, the half-bridge circuit comprises transistors M1 and M2, the source of the transistor M1 is connected to the drain of the transistor M2, the gate thereof is connected to the first output terminal of the half-bridge circuit direct current protection circuit, and the drain thereof is connected to the positive electrode of the power supply; the source of the transistor M2 is connected to ground, and its gate is connected to the second output terminal of the half-bridge pass protection circuit.
Preferably, transistors M1 and M2 are both enhancement mode GaN power transistors.
The invention has the beneficial effects that:
(1) the invention realizes the design of a basic digital logic unit circuit of full GaN integration through an enhanced GaN power transistor and a GaN-based diode, namely a NAND gate sub-circuit and a NOR gate sub-circuit, and further realizes the design of a half-bridge circuit through protection circuit of full GaN integration through the NAND gate sub-circuit and the NOR gate sub-circuit, thereby avoiding the through phenomenon of the half-bridge circuit when a high-side driving signal and a low-side driving signal are simultaneously high levels, and laying a foundation for the digital integrated circuit of a full GaN enhanced device.
(2) The invention realizes latch design by using full GaN enhancement type devices, namely an enhancement type GaN power transistor and a GaN-based diode, and realizes that when an input signal is changed, an output signal is not easy to generate burrs due to the on/off state switching of the GaN power transistor.
Drawings
FIG. 1 is a schematic diagram of a conventional GaN-based NAND gate structure.
FIG. 2 is a schematic diagram of a conventional GaN-based NOR gate structure.
Fig. 3 is a schematic diagram of a half-bridge circuit dc protection circuit according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a nand gate sub-circuit according to an embodiment of the invention.
Fig. 5 is a schematic diagram of a nor sub-circuit structure according to an embodiment of the invention.
Detailed Description
Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It is to be understood that the embodiments shown and described in the drawings are merely exemplary and are intended to illustrate the principles and spirit of the invention, not to limit the scope of the invention.
An embodiment of the present invention provides a half-bridge pass protection circuit, as shown in fig. 3, including 2 nand gate sub-circuits N1 and N2, and 7 nor gate sub-circuits N3, N4, N5, N6, N7, N8, and N9.
The first input end of the NAND gate sub-circuit N1 is a first input end of a half-bridge circuit direct-connection protection circuit, the second input end of the NAND gate sub-circuit N1 is connected with the first input end of the NAND gate sub-circuit N2 and serves as a second input end of the half-bridge circuit direct-connection protection circuit, and the second input end of the NAND gate sub-circuit N2 is a third input end of the half-bridge circuit direct-connection protection circuit.
In the embodiment of the invention, as shown in fig. 3, the first input terminal of the half-bridge circuit pass-through protection circuit and the high-side driving gate-source signal V of the half-bridge circuitgsHA second input end of the second switch is connected with an enable signal EN, and a third input end of the third switch is connected with a low-side driving grid source signal of the half-bridge circuit to be VgsLAnd (4) connecting.
An output end of the nand gate sub-circuit N1 is connected to a second input end of the nor gate sub-circuit N3 and a first input end of the nor gate sub-circuit N4, respectively, an output end of the nand gate sub-circuit N2 is connected to a second input end of the nor gate sub-circuit N4 and a first input end of the nor gate sub-circuit N5, respectively, a first input end of the nor gate sub-circuit N3 and a second input end of the nor gate sub-circuit N5 are both connected to the 5V high level VDD.
An output end of the nor gate sub-circuit N3 is connected with a first input end of the nor gate sub-circuit N6, an output end of the nor gate sub-circuit N4 is connected with a second input end of the nor gate sub-circuit N6, a first input end of the nor gate sub-circuit N7, a second input end of the nor gate sub-circuit N8 and a first input end of the nor gate sub-circuit N9, an output end of the nor gate sub-circuit N5 is connected with a second input end of the nor gate sub-circuit N7, an output end of the nor gate sub-circuit N6 is connected with a first input end of the nor gate sub-circuit N8, an output end of the nor gate sub-circuit N7 is connected with a second input end of the nor gate sub-circuit N9, an output end of the nor gate sub-circuit N8 is a first output end of the half-bridge circuit direct-pass protection circuit, and an output end of the nor gate sub-circuit N9 is a second.
In the embodiment of the present invention, as shown in fig. 3, the first output terminal and the second output terminal of the half-bridge circuit dc protection circuit are both connected to the half-bridge circuit. The half-bridge circuit comprises transistors M1 and M2, wherein the source electrode of the transistor M1 is connected with the drain electrode of the transistor M2, the grid electrode of the transistor M1 is connected with the first output end of the half-bridge circuit direct-current protection circuit, and the drain electrode of the transistor M is connected with the positive electrode of the power supply; the source of the transistor M2 is connected to ground, and its gate is connected to the second output terminal of the half-bridge pass protection circuit. Transistors M1 and M2 are both enhancement mode GaN power transistors.
As shown in fig. 4, each of the nand gate sub-circuits N1 and N2 has the same structure and includes 5 transistors E1, E2, E3, E4, and E5, 2 diodes D1 and D2, 2 resistors R1 and R2, and 2 capacitors C1 and C2. In the embodiment of the invention, 5 transistors E1, E2, E3, E4 and E5 are all enhancement-type GaN power transistors, and 2 diodes D1 and D2 are all GaN-based diodes.
The gate of the transistor E3 is the first input terminal V of the NAND gate sub-circuitinAA source connected to the drain of the transistor E4, and a gate of the transistor E4Second input terminal V of NAND gate sub-circuitinBThe source of the resistor R2 is connected to one end of the resistor R2 and the gate of the transistor E2, the other end of the resistor R2 is connected to the drain of the transistor E5, the gate of the transistor E5 is connected to the cathode of the diode D2 and one end of the capacitor C2, and the other end of the capacitor C2, the source of the transistor E5 and the source of the transistor E2 are all grounded.
The drain of the transistor E2 is connected to the source of the transistor E1 and one end of the capacitor C1, respectively, and serves as the output terminal V of the NAND gate circuitoutThe gate of the transistor E1 is connected to the other end of the capacitor C1 and the cathode of the diode D1, the drain of the transistor E1 is connected to one end of the resistor R1, and the anode of the diode D2, the drain of the transistor E3, the anode of the diode D1, and the other end of the resistor R1 are connected to the 5V high level VDD.
Transistors E3, E4 and E5, diode D2, capacitor C2 and resistor R2 together form the input stage of the nand gate sub-circuit, and transistors E1 and E2, diode D1, capacitor C1 and resistor R1 together form the output stage of the nand gate sub-circuit.
In the embodiment of the invention, two input levels V are avoidedinAAnd VinBResults in a change of state of the two enhancement mode GaN power transistors in the output stage, which in turn affects the output level VoutThe coupling of the input level to the output level is represented by only one enhancement mode GaN power transistor E2.
The width-to-length ratio W/L of the enhancement GaN power transistor E1 is 5, the width-to-length ratio W/L of the enhancement GaN power transistor E2 is 25, the width-to-length ratios W/L of the enhancement GaN power transistors E3 and E4 are 10, the width-to-length ratio W/L of the enhancement GaN power transistor E5 is 5, the turn-on voltages of the diodes D1 and D2 are about 0.8V, the high level 5V is VDD, and the low level 0V is 0.
When the input level is (1) VinA＝VinB0 or (2) VinA0 and VinBVDD, or (3) VinAVDD and VinBWhen equal to 0, i.e. VinAOr VinBAt least one of the two transistors E3 or E4 is at low level, and at least one of the two transistors E3+ E4 is at off stateThe connecting branch is broken. The diode D2 being turned on makes the gate potential V of the transistor E5G5＝(VDD-VD2) Approximately 4.5V, transistor E5 is turned on, then VDThe potential is pulled down to 0 potential by the turned on E5, so that the transistor E2 is in an off state. At this time, the transistor E1 is turned on through the diode D1, and V is turned onoutThe potential becomes the high potential VDD through the conductive E1.
When the three conditions are switched with each other, when the transistors E3 and E4 are switched between an off state and an on state, and the output capacitor transfers charges through a two-dimensional electron air channel, it may happen that a current flows between E3 and E4 at the same time at a certain moment, and the on resistances of the two devices are reduced at the same time, at this moment, the transistors E3, E4, E5 and the resistor R2 bear the VDD voltage of 5V in common, but due to the design of the transistors E3, E4, E5 and the current limiting resistor R2, V is enabled to be equal to V, and the output capacitor is enabled to beDThe potential is in this case always less than the threshold voltage V of the transistor E2TH2Ensuring that E2 remains off.
When the input level VinA＝VinBWhen transistors E3 and E4 are turned on at the same time at VDD, VC＝(VinA-VTH3)≈4.2V，VD＝(VinB-VTH4) About 4.2V, due to VDGreater than the threshold voltage V of transistor E2TH2E2 is opened, so that VoutThe low is pulled to be 0, and the normal work of the NAND gate is realized.
As shown in fig. 5, nor sub-circuits N3, N4, N5, N6, N7, N8, and N9 have the same structure, and each include 5 transistors E6, E7, E8, E9, and E10, 2 diodes D3 and D4, 2 resistors R3 and R4, and 2 capacitors C3 and C4. In the embodiment of the invention, 5 transistors E6, E7, E8, E9 and E10 are all enhancement-type GaN power transistors, and 2 diodes D3 and D4 are all GaN-based diodes.
The gate of the transistor E8 is the first input terminal V of the NOR sub-circuitinAA source of the transistor E9 is connected to the source of the transistor E9, the gate of the transistor E7 and one end of the resistor R4, and a gate of the transistor E9 is the second input terminal V of the NOR sub-circuitinBThe other end of the resistor R4 is connected to the drain of the transistor E10, and the gates of the transistors E10 and the diodeThe negative electrode of D4 is connected to one end of the capacitor C4, and the other end of the capacitor C4, the source of the transistor E10, and the source of the transistor E7 are all grounded.
The drain of the transistor E7 is connected to the source of the transistor E6 and one end of the capacitor C3, respectively, and serves as the output terminal V of the NOR circuitoutThe gate of the transistor E6 is connected to the other end of the capacitor C3 and the cathode of the diode D3, the drain of the transistor E6 is connected to one end of the resistor R3, and the anode of the diode D4, the drain of the transistor E8, the drain of the transistor E9, the anode of the diode D3, and the other end of the resistor R3 are all connected to the 5V high level VDD.
Transistors E8, E9 and E10, diode D4, capacitor C4 and resistor R4 together form the input stage of the nor sub-gate circuit, and transistors E6 and E7, diode D3, capacitor C3 and resistor R3 together form the output stage of the nor sub-gate circuit.
In the embodiment of the invention, two input levels V are avoidedinAAnd VinBResults in a change of state of the two enhancement mode GaN power transistors in the output stage, which in turn affects the output level VoutThe coupling of the input level to the output level is represented by only one enhancement mode GaN power transistor E7.
The width-to-length ratio W/L of the enhancement GaN power transistor E6 is 5, the width-to-length ratio W/L of the enhancement GaN power transistor E7 is 25, the width-to-length ratios W/L of the enhancement GaN power transistors E8 and E9 are 10, the width-to-length ratio W/L of the enhancement GaN power transistor E10 is 5, and the turn-on voltages of the diodes D3 and D4 are about 0.8V.
When the input level VinA＝VinBWhen the potential is equal to 0, the transistors E8 and E9 are turned off at the same time, and the diode D4 which is turned on makes the gate potential V of the device E10G10＝(VDD-VD4) Approximately 4.5V, transistor E10 is turned on, then VDThe potential is pulled down to 0 potential by the turned on E10, so that the transistor E7 is in an off state. At this time, the transistor E6 is turned on through the diode D3, and V is turned onoutThe potential becomes the high potential VDD through the conductive E6.
When the input level is (1) VinA＝VinBVDD, or (2) VinA＝0And V isinBVDD, or (3) VinAVDD and VinBWhen equal to 0, i.e. VinAOr VinBAt least one of the two devices E8 or E9 is in an on state when at least one is at high level VDD, and at least one path of the parallel branch of E8 and E9 is conducted, so that V isDE8 or E9, which is turned on, is pulled high to VDD, so that the transistor E7 is in the on state, and V isoutThe potential becomes low potential 0 through conducting E7. When the three conditions are switched, the transistors E8 or E9 are switched due to the off/on state, but the parallel branch of E8 and E9 can always ensure that V is enabledDThe potential is high potential VDD, so that glitches are not caused in the low level output.
The working principle and process of the half-bridge circuit dc-dc protection circuit provided by the embodiment of the present invention are described in detail below with reference to fig. 3:
the embodiment of the invention realizes the design of a digital logic NAND gate and a NOR gate circuit by using the enhanced GaN power transistor, and further realizes a half-bridge circuit direct-connection protection circuit. The half-bridge circuit generates a shoot-through phenomenon when the high-side drive signal and the low-side drive signal are simultaneously high level, and at this time, the upper tube M1 and the lower tube M2 are simultaneously conducted to form a short circuit, so that the drive signals need to be controlled. The half-bridge circuit direct-connection protection circuit is a digital module circuit of an all-GaN-based drive circuit.
As shown in fig. 3, the half-bridge circuit through protection circuit needs to input a high-side driving gate source signal and a low-side driving gate source signal of the half-bridge circuit, and input an enable signal, and when the enable signal is at a high level of 5V, the protection circuit outputs a driving signal for realizing a protection function after passing through a series of logic gate circuits, so that M1 and M2 operate normally; when the enable signal is at low level 0V, after the protection circuit passes through a series of logic gate circuits, AH and AL output potentials are two low level signals, and two transistors M1 and M2 of the half-bridge circuit are directly turned off.
Let the high side driving gate source signal be VgsHLow side driving grid source signal is VgsLThe enable signal is EN, 1 represents a high level 5V, and 0 represents a low level 0V; a represents the inversion of the A level, (A)X + Y) represents two input levels of the logic gate, where X, Y take either 0 or 1.
In fig. 3, a 1-a 7, AH and AL are 9 intermediate nodes, then:
(1) when the enable signal EN is equal to 1, a1 is (V)gsH) A2 is (. about.V)gsL) The method comprises the following steps:
(1a) if VgsH＝VgsLWhen the half-bridge circuit is turned on, i.e. the half-bridge circuit is turned on, a1 is a2 is VgsH＝～VgsL0; according to the nor gate principle, the relevant inputs of A3 and a5 are (0+1), the output is A3 ═ a5 ═ 0, and the input of a4 is (0+0), and the output is a4 ═ 1; according to the nor gate principle, the relevant inputs of a6 and a7 are (0+1), and the output is a6 ═ a7 ═ 0; according to the nor gate principle, if the relevant inputs of AH and AL are (1+0), the output is AH-AL-0, and finally the turn-off of M1 and M2 is realized.
(1b) If VgsHAnd VgsLNot simultaneously 1, i.e. the half-bridge circuit does not exhibit shoot-through, a1 ═ VgsH)，A2＝(～VgsL) (ii) a According to the NOR gate principle, the A3 correlation input is (V)gsH+1), the output is a3 ═ V (V)gsH) The A5 correlation input is (V)gsL+1), the output is a5 ═ V (V)gsL) The A4 related input is (V)gsH+VgsL) And not (0+0), the output is a4 ═ 0; according to the NOR gate principle, the relevant input of A6 is (V)gsH+0), the output is a6 ═ V (V ═ V)gsH) The A7 related input is (V)gsL+0), the output is a7 ═ V (V ═ V)gsL) (ii) a According to the NOR gate principle, the AH related input is (— V)gsH+0), the output is AH ═ V (V)gsH) With AL dependent input of (V)gsL+0), the output is AL ═ V (V)gsL) And final drive control is realized.
(2) When the enable signal EN is equal to 0, no matter what the input is, a1 is 1, a2 is 1, and according to the nor gate principle, the relevant inputs of A3 and a5 are (1+1), the output is A3 equal to a5 equal to (0), and the input of a4 is (1+1), and the output is a4 equal to (0); according to the nor gate principle, the relevant inputs of a6 and a7 are (0+0), and the output is a6 ═ a7 ═ 1; according to the nor gate principle, if the relevant inputs of AH and AL are (1+0), the output is AH-AL-0, and finally it is ensured that when the enable signal EN is 0, no matter what the input is, M1 and M2 are turned off.
The above description may be represented in tabular form as follows:
Figure BDA0001981194820000081
it will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.

Claims (5)

1. A half-bridge circuit through protection circuit is characterized by comprising 2 NAND gate subcircuits N1 and N2, and 7 NAND gate subcircuits N3, N4, N5, N6, N7, N8 and N9;
a first input end of the NAND gate sub-circuit N1 is a first input end of a half-bridge circuit direct-connection protection circuit, a second input end of the NAND gate sub-circuit N1 is connected with a first input end of the NAND gate sub-circuit N2 and serves as a second input end of the half-bridge circuit direct-connection protection circuit, and a second input end of the NAND gate sub-circuit N2 is a third input end of the half-bridge circuit direct-connection protection circuit;
the output end of the nand gate sub-circuit N1 is respectively connected with the second input end of the nor gate sub-circuit N3 and the first input end of the nor gate sub-circuit N4, the output end of the nand gate sub-circuit N2 is respectively connected with the second input end of the nor gate sub-circuit N4 and the first input end of the nor gate sub-circuit N5, and the first input end of the nor gate sub-circuit N3 and the second input end of the nor gate sub-circuit N5 are both connected with a 5V high level VDD;
the output end of the NOR sub-circuit N3 is connected with the first input end of the NOR sub-circuit N6, the output end of the NOR sub-circuit N4 is respectively connected with the second input end of the NOR sub-circuit N6, the first input end of the NOR sub-circuit N7, the second input end of the NOR sub-circuit N8 and the first input end of the NOR sub-circuit N9, the output end of the NOR sub-circuit N5 is connected with the second input end of the NOR sub-circuit N7, the output end of the NOR sub-circuit N6 is connected with the first input end of the NOR sub-circuit N8, the output end of the NOR sub-circuit N7 is connected with the second input end of the NOR sub-circuit N9, the output end of the NOR sub-circuit N8 is the first output end of the half-bridge circuit direct-current protection circuit, the output end of the NOR gate sub-circuit N9 is a second output end of the half-bridge circuit direct-connection protection circuit;
the NAND gate sub-circuits N1 and N2 are identical in structure and respectively comprise 5 transistors E1, E2, E3, E4 and E5, 2 diodes D1 and D2, 2 resistors R1 and R2 and 2 capacitors C1 and C2;
the gate of the transistor E3 is a first input end of the nand gate sub-circuit, the source thereof is connected with the drain of the transistor E4, the gate of the transistor E4 is a second input end of the nand gate sub-circuit, the sources thereof are respectively connected with one end of a resistor R2 and the gate of the transistor E2, the other end of the resistor R2 is connected with the drain of the transistor E5, the gate of the transistor E5 is respectively connected with the cathode of the diode D2 and one end of a capacitor C2, and the other end of the capacitor C2, the source of the transistor E5 and the source of the transistor E2 are all grounded;
the drain of the transistor E2 is connected to the source of the transistor E1 and one end of the capacitor C1, respectively, and serves as the output end of the nand gate sub-circuit, the gate of the transistor E1 is connected to the other end of the capacitor C1 and the cathode of the diode D1, the drain of the transistor E1 is connected to one end of the resistor R1, and the anode of the diode D2, the drain of the transistor E3, the anode of the diode D1, and the other end of the resistor R1 are all connected to the 5V high-level VDD;
the 5 transistors E1, E2, E3, E4 and E5 are all enhancement mode GaN power transistors, and the 2 diodes D1 and D2 are all GaN-based diodes;
the NOR gate sub-circuits N3, N4, N5, N6, N7, N8 and N9 are identical in structure and respectively comprise 5 transistors E6, E7, E8, E9 and E10, 2 diodes D3 and D4, 2 resistors R3 and R4 and 2 capacitors C3 and C4;
the gate of the transistor E8 is a first input end of the NOR gate sub-circuit, the source of the transistor E8 is respectively connected with the source of the transistor E9, the gate of the transistor E7 and one end of the resistor R4, the gate of the transistor E9 is a second input end of the NOR gate sub-circuit, the other end of the resistor R4 is connected with the drain of the transistor E10, the gate of the transistor E10 is respectively connected with the cathode of the diode D4 and one end of the capacitor C4, and the other end of the capacitor C4, the source of the transistor E10 and the source of the transistor E7 are all grounded;
the drain of the transistor E7 is connected to the source of the transistor E6 and one end of the capacitor C3, respectively, and serves as the output end of the nor sub-circuit, the gate of the transistor E6 is connected to the other end of the capacitor C3 and the cathode of the diode D3, the drain of the transistor E6 is connected to one end of the resistor R3, and the anode of the diode D4, the drain of the transistor E8, the drain of the transistor E9, the anode of the diode D3, and the other end of the resistor R3 are all connected to the 5V high-level VDD;
the 5 transistors E6, E7, E8, E9 and E10 are all enhancement mode GaN power transistors, and the 2 diodes D3 and D4 are all GaN-based diodes;
the first input end of the half-bridge circuit direct-current protection circuit and the high-side driving grid source signal V of the half-bridge circuitgsHA second input end of the second switch is connected with an enable signal EN, and a third input end of the third switch is connected with a low-side driving grid source signal of the half-bridge circuit to be VgsLAnd a first output end and a second output end of the half-bridge circuit are connected with the half-bridge circuit.
2. The half-bridge cut-through protection circuit of claim 1, wherein the transistors E3, E4 and E5, the diode D2, the capacitor C2 and the resistor R2 together form an input stage of the NAND gate sub-circuit, and the transistors E1 and E2, the diode D1, the capacitor C1 and the resistor R1 together form an output stage of the NAND gate sub-circuit.
3. The half-bridge cut-through protection circuit of claim 1, wherein the transistors E8, E9 and E10, the diode D4, the capacitor C4 and the resistor R4 together form an input stage of the NOR gate sub-circuit, and the transistors E6 and E7, the diode D3, the capacitor C3 and the resistor R3 together form an output stage of the NOR gate sub-circuit.
4. The half-bridge pass protection circuit of claim 1, wherein the half-bridge circuit comprises transistors M1 and M2, the transistor M1 having a source connected to the drain of transistor M2, a gate connected to the first output of the half-bridge pass protection circuit, and a drain connected to the positive supply; the source of the transistor M2 is grounded, and the gate thereof is connected to the second output terminal of the half-bridge circuit dc protection circuit.
5. The half-bridge cut-through protection circuit of claim 4, wherein the transistors M1 and M2 are enhancement mode GaN power transistors.
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