CN109861503B - Driving circuit for power device - Google Patents
Driving circuit for power device Download PDFInfo
- Publication number
- CN109861503B CN109861503B CN201910153133.5A CN201910153133A CN109861503B CN 109861503 B CN109861503 B CN 109861503B CN 201910153133 A CN201910153133 A CN 201910153133A CN 109861503 B CN109861503 B CN 109861503B
- Authority
- CN
- China
- Prior art keywords
- electrode
- mnpwr
- transistor
- nmos
- tube
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 21
- 238000007599 discharging Methods 0.000 claims abstract description 8
- 238000010586 diagram Methods 0.000 description 10
- 230000001360 synchronised effect Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Abstract
The application discloses a driving circuit for a power device, which comprises a first NMOS tube MNPWR, a second NMOS tube MNPRP, a third NMOS tube MN1, a first PMOS tube MP1, an inductor L, a first diode Dpwr, a first capacitor Cboost and a resistor R1, wherein the drain electrode of the first NMOS tube MNPWR is connected with a VIN input signal, the source electrode of the first NMOS tube MNPWR is connected with a VOUT output signal through the inductor L, the source electrode of the first NMOS tube MNPWR is also connected with the cathode of the first diode Dpwr, the anode of the first diode Dpwr is grounded, the grid electrode of the first NMOS tube MNPWR is connected with the drain electrode of the third NMOS tube MN1 and the source electrode of the second NOMS tube MNPRP, and the source electrode of the first PMOS tube MP1 is connected through the resistor R1. According to the application, at the turn-on time of the power device MNPWR, the second NMOS transistor MNPRE provides main charging current for charging the MNPWR grid electrode, so that the peak current flowing through the driving stage can be reduced, and the peak discharging current and discharging charge of the Cboost can also be reduced. Accordingly, the MP1 area and Cboost capacitance may also be reduced.
Description
Technical Field
The application relates to the technical field of integrated circuits, in particular to a driving circuit for a power device.
Background
At present, the switching power supply is widely applied. Under the same condition, the on resistance of the N-type MOSFET is smaller than that of the P-type MOSFET, so that the switching power supply commonly uses an enhanced N-type MOSFET power device.
In high channel N-type MOSFET power device applications, bootstrap circuits are typically used to power the drive circuitry. FIG. 1 is a non-synchronous BUCK switching power supply circuit (non-synchronous BUCK circuit); FIG. 2 is a synchronous BUCK switching power supply circuit (synchronous BUCK circuit); fig. 3 is a simplified bootstrap drive circuit. As shown in fig. 1, the bootstrap diode D1 and the bootstrap capacitor Cboost form a bootstrap power supply circuit, so as to generate a high-channel power supply, wherein the high-potential end of the high-channel power supply is HB, and the low-potential end of the high-channel power supply is HS. The high channel power supplies power to the level shift module LEVEL SHFIT, the BUFFER stage BUFFER, and the drive output stages (MP 1 and MN 1).
The high channel control signal passes through the level shift module LEVEL SHFIT and the BUFFER stage BUFFER to generate the pre-driving signal HPRE, and the pre-driving signal HPRE passes through the driving output stages (MP 1 and MN 1) to generate the driving signal HO to drive the power device MNPWR. Fig. 3 is a simplified driving circuit of fig. 1.
The power MOS tube is a voltage control device, the grid electrode is provided with a larger input capacitance, and the grid electrode of the power MOS tube is charged to raise the grid-source voltage and turn on the power MOS tube. Fig. 12 shows the gate-source voltage versus gate charge.
In order to increase the turn-on speed of the power MOS transistor and reduce the turn-on loss of the power MOS transistor, a high peak driving current is required to reduce the turn-on time of the power MOS transistor. At the turn-on time, high driving current flows through MP1 and Cboost to charge the grid electrode of the power MOS tube; at the turn-off time, the grid electrode of the power MOS tube discharges through the MN 1.
Therefore, the on-resistance of the driving output stages MP1 and MN1 needs to be small enough so that a sufficiently large driving current can be obtained. The bootstrap capacitor Cboost needs to be large enough, so that the voltage fluctuation between the high-channel power supplies HB and HS is not large, and the normal operation of the modules powered by the high-channel power supplies, such as the level shift module LEVEL SHFIT, the BUFFER stage BUFFER, and the driving output stage (MP 1 and MN1, etc.), is not affected.
In addition, high peak drive currents have other adverse effects due to parasitic inductance and parasitic capacitance.
Disclosure of Invention
The application aims to provide a driving circuit for a power device, which solves the problem of excessively high driving current peak value.
In order to solve the technical problems, the application adopts the following technical scheme:
the driving circuit for the power device comprises a first NMOS tube MNPWR, a second NMOS tube MNPWR, a third NMOS tube MN1, a first PMOS tube MP1, an inductor L, a first diode Dpwr, a first capacitor Cboost and a resistor R1, wherein the drain electrode of the first NMOS tube MNPWR is connected with a VIN input signal, the source electrode of the first NMOS tube MNPWR is connected with a VOUT output signal through the inductor L, the source electrode of the first NMOS tube MNPWR is also connected with the cathode electrode of the first diode Dpwr, the anode electrode of the first diode Dpwr is grounded, the grid electrode of the first NMOS tube MNPWR is connected with the drain electrode of the third NMOS tube MN1 and the source electrode of the second NOMS tube MNPRE, and the source electrode of the first PMOS tube MP1 is connected through the resistor R1; the drain electrode of the second NMOS transistor MNPRE is connected to the VIN input signal, the gate electrode of the second NMOS transistor MNPRE is connected to the drain electrode of the first PMOS transistor MP1, the source electrode of the first PMOS transistor MP1 is connected to the high-potential end HB of the high-channel power supply, the source electrode of the third NMOS transistor MN1 is connected to the low-potential end HS of the high-channel power supply, and the gate electrodes of the first PMOS transistor MP1 and the third NMOS transistor MN1 are both connected to the pre-drive signal HPRE; the first capacitor Cboost is connected between the high potential terminal HB and the low potential terminal HS of the high-channel power supply.
Preferably, the drain MNPRE of the second NMOS transistor is connected to the VIN input signal through a second diode D2, the positive electrode of the second diode D2 is connected to the VIN input signal, and the negative electrode is connected to the drain of the second NMOS transistor MNPRE.
Preferably, the drain of the second NMOS transistor MNPRE is connected to the VIN input signal via a transistor QD, the base and collector of the transistor QD are both connected to the VIN signal, and the emitter of the transistor QD is connected to the drain of the second NMOS transistor MNPRE.
Preferably, the drain of the second NMOS transistor MNPRE is connected to the VIN input signal through a fifth NMOS transistor MND, the gate and the source of the fifth NMOS transistor MND are both connected to the VIN signal, and the drain of the fifth NMOS transistor MND is connected to the drain of the second NMOS transistor MNPRE.
A driving circuit for a power device, comprising a first NMOS transistor MNPWR, a second NMOS transistor MNPRE, a first bipolar transistor QN1, a second bipolar transistor QP1, an inductor L, a first diode Dpwr, a second diode D2, a first capacitor Cboost, and a resistor R1, wherein the drain of the first NMOS transistor MNPWR is connected to a VIN input signal, the source of the first NMOS transistor MNPWR is connected to a VOUT output signal through the inductor L, the source of the first NMOS transistor MNPWR is also connected to the cathode of the first diode Dpwr, the anode of the first diode Dpwr is grounded, the gate of the first NMOS transistor MNPWR is connected to the collector of the first bipolar transistor QN1 and the source of the second NMOS transistor MNPRE, and the source of the first NMOS transistor MNPWR is connected to the collector of the second bipolar transistor QP1 through the resistor R1; the drain electrode MNPRE of the second NMOS transistor is connected to the VIN input signal through a second diode D2, the gate electrode of the second NMOS transistor MNPRE is connected to the collector electrode of the second bipolar transistor QP1, the emitter electrode of the second bipolar transistor QP1 is connected to the high-potential end HB of the high-channel power supply, the emitter electrode of the first bipolar transistor QN1 is connected to the low-potential end HS of the high-channel power supply, and the base electrode of the second bipolar transistor QP1 and the base electrode of the first bipolar transistor QN1 are both connected to the pre-driving signal HPRE; the first capacitor Cboost is connected between the high potential terminal HB and the low potential terminal HS of the high-channel power supply.
A driving circuit for a power device, comprising a first NMOS transistor MNPWR, a second NMOS transistor MNPRE, a third NMOS transistor MN1, a fourth NMOS transistor MN2, a first PMOS transistor MP1, a second PMOS transistor MP2, an inductor L, a first diode Dpwr, and a first capacitor Cboost, wherein a drain of the first NMOS transistor MNPWR is connected to a VIN input signal, a source of the first NMOS transistor MNPWR is connected to a VOUT output signal through the inductor L, a source of the first NMOS transistor MNPWR is also connected to a cathode of the first diode Dpwr, a positive electrode of the first diode Dpwr is grounded, a gate of the first NMOS transistor MNPWR is connected to a drain of the fourth NMOS transistor MN2, a source of the second NMOS transistor MNPRE, a drain of the second PMOS transistor MP2 is connected to an input signal, a gate of the second NMOS transistor MNPRE is connected to a drain of the first PMOS transistor MP1 and a drain of the third NMOS transistor MN1, and a gate of the fourth NMOS transistor MN1 is connected to a high-level gate of the first PMOS transistor MN1 and a high-level transistor MN 2; the first capacitor Cboost is connected between the high potential terminal HB and the low potential terminal HS of the high-channel power supply.
Preferably, the second PMOS transistor MP2 is connected to the pre-driving signal HPRE through a second resistor R.
Preferably, the second PMOS transistor MP2 is connected to the pre-driving signal HPRE through a delay unit delay.
Compared with the prior art, the application has the beneficial effects that:
according to the application, at the turn-on time of the power device MNPWR, the second NMOS transistor MNPRE provides main charging current for charging the MNPWR grid electrode, so that the peak current flowing through the driving stage can be reduced, and the peak discharging current and discharging charge of the Cboost can also be reduced. Accordingly, the MP1 area and Cboost capacitance may also be reduced.
Drawings
Fig. 1 is a conventional asynchronous buck bootstrap driving circuit.
Fig. 2 is a schematic diagram of a conventional synchronous buck bootstrap driving circuit.
Fig. 3 is a simplified conventional bootstrap driving circuit.
Fig. 4 is a schematic diagram of a basic circuit structure of the present application.
Fig. 5 is a schematic circuit diagram of an embodiment of the present application.
Fig. 6 is a schematic circuit diagram of another embodiment of the present application.
Fig. 7 is a schematic circuit diagram of another embodiment of the present application.
Fig. 8 is a schematic circuit diagram of another embodiment of the present application.
Fig. 9 is a schematic circuit diagram of another embodiment of the present application.
Fig. 10 is a schematic circuit diagram of another embodiment of the present application.
Fig. 11 is a schematic circuit diagram of another embodiment of the present application.
Fig. 12 is a schematic diagram of other unidirectional conductive devices in accordance with other embodiments of the present application.
FIG. 13 is a graph showing the relationship between gate-source voltage and gate charge.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
Fig. 4 shows an embodiment of the present application, a driving circuit for a power device, including a first NMOS transistor MNPWR, a second NMOS transistor MNPRE, a third NMOS transistor MN1, a first PMOS transistor MP1, an inductor L, a first diode Dpwr, a first capacitor Cboost, and a resistor R1, where a drain of the first NMOS transistor MNPWR is connected to a VIN input signal, a source of the first NMOS transistor MNPWR is connected to a VOUT output signal through an inductor L, a source of the first NMOS transistor MNPWR is also connected to a cathode of the first diode Dpwr, an anode of the first diode Dpwr is grounded, a gate of the first NMOS transistor MNPWR is connected to a drain of the third NMOS transistor MN1 and a source of the second NMOS transistor MNPRE, and is connected to a drain of the first PMOS transistor MP1 through a resistor R1; the drain electrode of the second NMOS transistor MNPRE is connected to the VIN input signal, the gate electrode of the second NMOS transistor MNPRE is connected to the drain electrode of the first PMOS transistor MP1, the source electrode of the first PMOS transistor MP1 is connected to the high-potential end HB of the high-channel power supply, the source electrode of the third NMOS transistor MN1 is connected to the low-potential end HS of the high-channel power supply, and the gate electrodes of the first PMOS transistor MP1 and the third NMOS transistor MN1 are both connected to the pre-drive signal HPRE; the first capacitor Cboost is connected between the high potential terminal HB and the low potential terminal HS of the high-channel power supply.
The drain electrode MNPRE of the second NMOS transistor is connected to the VIN input signal through a second diode D2, the positive electrode of the second diode D2 is connected to the VIN input signal, and the negative electrode is connected to the drain electrode of the second NMOS transistor MNPRE. A unidirectional conduction device is added, and the function is that: when HO > VIN, D2 blocks charging current i1 from flowing to VIN, allowing charging current i1 to flow entirely into the MNPWR gate, avoiding loss of charging current i1.
The working principle in this embodiment is: when HPRE is low, MP1 is on, MN1 is off, HO1 is high. HO1 is high, charging MNPWR gate through R1, charging current i1 is limited by R1 and is small, provided by Cboost. HO1 is high, MNPRE is on, charges the MNPWR gate, and the charging current i2 is large, provided by vin. When HO > =vin, the path of the charging current i1 is Cboost, MP1, R1, and HO is continued to rise until the potential is equal to HB. When HO > VIN, D2 blocks charging current i1 from flowing to VIN, allowing charging current i1 to flow entirely into the MNPWR gate, avoiding loss of charging current i1.
When HPRE is high, MP1 is off, MN1 is on, HO1 is low. MNPWR gate charge is rapidly discharged through MN1 and thus MNPWR can be rapidly turned off. Since MNPRE is much smaller than MNPWR, very small MNPRE gate charges are also rapidly discharged through R1 and MN1, and thus MNPRE can also be rapidly turned off.
In summary, at the time when the power device MNPWR is turned on, the second NMOS transistor MNPRE provides the main charging current to charge the MNPWR gate, so that the peak current flowing through the driving stage can be reduced, and the peak discharging current and the discharging charge of the Cboost can also be reduced. Accordingly, the MP1 area and Cboost capacitance may also be reduced. Meanwhile, the turn-off speed of the power device MNPWR is not affected.
D2 may also be other devices or circuits having unidirectional conductive properties (diode-like) including, but not limited to, the device shown in fig. 12 and methods of use thereof. Fig. 10 and 11 are examples of two other device or circuit implementations using unidirectional electrical conductivity.
Fig. 10 shows another embodiment of the present application, in which the second diode D2 is replaced by a transistor QD, that is, the drain of the second NMOS transistor MNPRE is connected to the VIN input signal through the transistor QD, the base and collector of the transistor QD are both connected to the VIN signal, and the emitter of the transistor QD is connected to the drain of the second NMOS transistor MNPRE.
Fig. 11 shows another embodiment of the present application, in which the second diode D2 is replaced by a fifth NMOS transistor MND, that is, the drain of the second NMOS transistor MNPRE is connected to the VIN input signal through the fifth NMOS transistor MND, the gate and the source of the fifth NMOS transistor MND are both connected to the VIN signal, and the drain of the fifth NMOS transistor MND is connected to the drain of the second NMOS transistor MNPRE.
Fig. 6 shows an embodiment of a driving circuit implemented by using bipolar transistors, wherein the driving circuit for a power device includes a first NMOS transistor MNPWR, a second NMOS transistor MNPRE, a first bipolar transistor QN1, a second bipolar transistor QP1, an inductor L, a first diode Dpwr, a second diode D2, a first capacitor Cboost, and a resistor R1, the drain of the first NMOS transistor MNPWR is connected to a VIN input signal, the source of the first NMOS transistor MNPWR is connected to a VOUT output signal through the inductor L, the source of the first NMOS transistor MNPWR is also connected to the cathode of the first diode Dpwr, the anode of the first diode Dpwr is grounded, the gate of the first NMOS transistor MNPWR is connected to the collector of the first bipolar transistor QN1 and the source of the second NMOS transistor pre, and the gate of the first NMOS transistor MNPWR is connected to the collector of the second bipolar transistor QP1 through the resistor R1; the drain electrode MNPRE of the second NMOS transistor is connected to the VIN input signal through a second diode D2, the gate electrode of the second NMOS transistor MNPRE is connected to the collector electrode of the second bipolar transistor QP1, the emitter electrode of the second bipolar transistor QP1 is connected to the high-potential end HB of the high-channel power supply, the emitter electrode of the first bipolar transistor QN1 is connected to the low-potential end HS of the high-channel power supply, and the base electrode of the second bipolar transistor QP1 and the base electrode of the first bipolar transistor QN1 are both connected to the pre-driving signal HPRE; the first capacitor Cboost is connected between the high potential terminal HB and the low potential terminal HS of the high-channel power supply.
At the time when power device MNPWR is turned on, R1 is a limit of high-channel power supply HB (Cboost) charging current i1 to the gate of power device MNPWR. It can be realized in other ways, that is, fig. 7 adjusts the gate charge current i1 through MP2 and adjusts the gate discharge current through MN 2.
As shown in fig. 7, a driving circuit for a power device includes a first NMOS transistor MNPWR, a second NMOS transistor MNPRE, a third NMOS transistor MN1, a fourth NMOS transistor MN2, a first PMOS transistor MP1, a second PMOS transistor MP2, an inductor L, a first diode Dpwr, and a first capacitor Cboost, wherein a drain of the first NMOS transistor MNPWR is connected to a VIN input signal, a source of the first NMOS transistor MNPWR is connected to a VOUT output signal through the inductor L, a source of the first NMOS transistor MNPWR is also connected to a cathode of the first diode Dpwr, a positive electrode of the first diode Dpwr is grounded, a gate of the first NMOS transistor MNPWR is connected to a drain of the fourth NMOS transistor MN2, a source of the second NMOS transistor MNPRE, a drain of the second PMOS transistor MP2 is connected to an input signal, a gate of the second NMOS transistor MNPRE is connected to a gate of the first NMOS transistor MN1, a source of the second NMOS transistor MN1 is connected to a high-level voltage source of the first NMOS transistor MN1, and a high-level gate of the second NMOS transistor MN1 is connected to a high-level drain of the fourth NMOS transistor MN 2; the first capacitor Cboost is connected between the high potential terminal HB and the low potential terminal HS of the high-channel power supply.
Fig. 8 adds a resistor on the basis of fig. 7, that is, the second PMOS transistor MP2 is connected to the pre-driving signal HPRE through the second resistor R. In this embodiment, a resistor is connected in series to the gate of MP2, so as to implement delay turn-on of MP 2.
In fig. 9, a delay unit is added on the basis of fig. 8, that is, the second PMOS transistor MP2 is connected to the pre-driving signal HPRE through the delay unit delay. The HPRE drives MP2 through the delay unit to realize the delay turn-on of MP 2.
Reference throughout this specification to "one embodiment," "another embodiment," "an embodiment," "a preferred embodiment," etc., means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application as broadly described. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with any embodiment, it is intended that such feature, structure, or characteristic be implemented within the scope of the application.
Although the application has been described herein with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the scope and spirit of the principles of this disclosure. More specifically, various variations and modifications may be made to the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, drawings and claims. In addition to variations and modifications in the component parts and/or arrangements, other uses will be apparent to those skilled in the art.
Claims (8)
1. A drive circuit for a power device, characterized by: comprises a first NMOS tube MNPWR, a second NMOS tube MNPE, a third NMOS tube MN1, a first PMOS tube MP1, an inductor L, a first diode Dpwr, a first capacitor Cboost and a resistor R1,
the drain electrode of the first NMOS transistor MNPWR is connected to the VIN input signal, the source electrode of the first NMOS transistor MNPWR is connected to the VOUT output signal through the inductor L, the source electrode of the first NMOS transistor MNPWR is further connected to the cathode electrode of the first diode Dpwr, the anode electrode of the first diode Dpwr is grounded, the gate electrode of the first NMOS transistor MNPWR is connected to the drain electrode of the third NMOS transistor MN1 and the source electrode of the second NOMS transistor MNPRE, and is connected to the drain electrode of the first PMOS transistor MP1 through the resistor R1;
the drain electrode of the second NMOS tube MNPE is connected with the VIN input signal, the grid electrode of the second NMOS tube MNPE is connected with the drain electrode of the first PMOS tube MP1,
the source electrode of the first PMOS tube MP1 is connected with the high-potential end HB of the high-channel power supply, the source electrode of the third NMOS tube MN1 is connected with the low-potential end HS of the high-channel power supply, and the grid electrodes of the first PMOS tube MP1 and the third NMOS tube MN1 are both connected with a pre-driving signal HPRE;
the first capacitor Cboost is connected between a high potential end HB and a low potential end HS of the high-channel power supply;
at the time of switching on the power device MNPWR, the second NMOS transistor MNPRE provides a main charging current to charge the MNPWR gate, so as to reduce the peak current flowing through the driving stage, reduce the peak discharging current and discharging charge of the Cboost, and reduce the MP1 area and the Cboost capacitance.
2. The drive circuit for a power device according to claim 1, wherein: the drain electrode MNPRE of the second NMOS transistor is connected to the VIN input signal through a second diode D2, and the positive electrode of the second diode D2 is connected to the VIN input signal, and the negative electrode is connected to the drain electrode of the second NMOS transistor MNPRE.
3. The drive circuit for a power device according to claim 1, wherein: the drain electrode of the second NMOS transistor MNPRE is connected to the VIN input signal through a transistor QD, the base electrode and the collector electrode of the transistor QD are both connected to the VIN signal, and the emitter electrode of the transistor QD is connected to the drain electrode of the second NMOS transistor MNPRE.
4. The drive circuit for a power device according to claim 1, wherein: the drain electrode of the second NMOS transistor MNPRE is connected to the VIN input signal through a fifth NMOS transistor MND, and the gate electrode and the source electrode of the fifth NMOS transistor MND are both connected to the VIN signal, and the drain electrode of the fifth NMOS transistor MND is connected to the drain electrode of the second NMOS transistor MNPRE.
5. A drive circuit for a power device, characterized by: comprises a first NMOS tube MNPWR, a second NMOS tube MNPRE, a first bipolar transistor QN1, a second bipolar transistor QP1, an inductor L, a first diode Dpwr, a second diode D2, a first capacitor Cboost and a resistor R1,
the drain electrode of the first NMOS transistor MNPWR is connected to the VIN input signal, the source electrode of the first NMOS transistor MNPWR is connected to the VOUT output signal through the inductor L, the source electrode of the first NMOS transistor MNPWR is further connected to the negative electrode of the first diode Dpwr, the positive electrode of the first diode Dpwr is grounded, the gate electrode of the first NMOS transistor MNPWR is connected to the collector electrode of the first bipolar transistor QN1 and the source electrode of the second NOMS transistor MNPRE, and is connected to the collector electrode of the second bipolar transistor QP1 through the resistor R1;
the drain electrode MNPRE of the second NMOS transistor is connected to the VIN input signal through a second diode D2, the gate electrode of the second NMOS transistor MNPRE is connected to the collector electrode of the second bipolar transistor QP1,
the emitter of the second bipolar transistor QP1 is connected with the high-potential end HB of the high-channel power supply, the emitter of the first bipolar transistor QN1 is connected with the low-potential end HS of the high-channel power supply, and the base of the second bipolar transistor QP1 and the base of the first bipolar transistor QN1 are both connected with the pre-driving signal HPRE;
the first capacitor Cboost is connected between the high potential terminal HB and the low potential terminal HS of the high-channel power supply.
6. A drive circuit for a power device, characterized by: comprises a first NMOS tube MNPWR, a second NMOS tube MNPRP, a third NMOS tube MN1, a fourth NMOS tube MN2, a first PMOS tube MP1, a second PMOS tube MP2, an inductor L, a first diode Dpwr, a first capacitor Cboost and a resistor R1,
the drain electrode of the first NMOS tube MNPWR is connected with VIN input signal, the source electrode of the first NMOS tube MNPWR is connected with VOUT output signal through inductance L, the source electrode of the first NMOS tube MNPWR is also connected with the cathode electrode of a first diode Dpwr, the anode electrode of the first diode Dpwr is grounded, the grid electrode of the first NMOS tube MNPWR is connected with the drain electrode of a fourth NMOS tube MN2, the source electrode of a second NOMS tube MNPE and the drain electrode of a second PMOS tube MP2,
the drain electrode of the second NMOS tube MNPE is connected with VIN input signals, the grid electrode of the second NMOS tube MNPE is connected with the drain electrode of the first PMOS tube MP1 and the drain electrode of the third NMOS tube MN1,
the source electrode of the first PMOS tube MP1 and the source electrode of the second PMOS tube MP2 are both connected with the high-potential end HB of the high-channel power supply, the source electrode of the third NMOS tube MN1 and the source electrode of the fourth NMOS tube MN2 are both connected with the low-potential end HS of the high-channel power supply,
the grid electrode of the first PMOS tube MP1, the grid electrode of the second PMOS tube MP2, the grid electrodes of the third NMOS tube MN1 and the fourth NMOS tube MN2 are all connected with a pre-drive signal HPRE;
the first capacitor Cboost is connected between the high potential terminal HB and the low potential terminal HS of the high-channel power supply.
7. The drive circuit for a power device according to claim 6, wherein: the second PMOS MP2 is connected to the pre-driving signal HPRE through a second resistor R.
8. The drive circuit for a power device according to claim 6, wherein: the second PMOS transistor MP2 is connected to the pre-driving signal HPRE through a delay unit delay.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910153133.5A CN109861503B (en) | 2019-02-28 | 2019-02-28 | Driving circuit for power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910153133.5A CN109861503B (en) | 2019-02-28 | 2019-02-28 | Driving circuit for power device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109861503A CN109861503A (en) | 2019-06-07 |
| CN109861503B true CN109861503B (en) | 2023-11-03 |
Family
ID=66899560
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910153133.5A Active CN109861503B (en) | 2019-02-28 | 2019-02-28 | Driving circuit for power device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109861503B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005208589A (en) * | 2003-12-08 | 2005-08-04 | Toshiba Matsushita Display Technology Co Ltd | El display device |
| JP2013223265A (en) * | 2012-04-13 | 2013-10-28 | Hitachi Ltd | Driving device for semi-conductor device |
| CN103701308A (en) * | 2014-01-09 | 2014-04-02 | 帝奥微电子有限公司 | Synchronizing power tube driving and bootstrap capacitor charging circuit |
| CN103915990A (en) * | 2014-04-18 | 2014-07-09 | 电子科技大学 | Drive circuit for GaN power devices |
| CN108092651A (en) * | 2018-01-09 | 2018-05-29 | 电子科技大学 | A kind of variable slope driving circuit |
| CN109039029A (en) * | 2018-08-15 | 2018-12-18 | 电子科技大学 | A kind of bootstrap charge circuit circuit suitable for GaN power device gate drive circuit |
| CN209435101U (en) * | 2019-02-28 | 2019-09-24 | 深圳市泰德半导体有限公司 | Driving circuit for power device |
-
2019
- 2019-02-28 CN CN201910153133.5A patent/CN109861503B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005208589A (en) * | 2003-12-08 | 2005-08-04 | Toshiba Matsushita Display Technology Co Ltd | El display device |
| JP2013223265A (en) * | 2012-04-13 | 2013-10-28 | Hitachi Ltd | Driving device for semi-conductor device |
| CN103701308A (en) * | 2014-01-09 | 2014-04-02 | 帝奥微电子有限公司 | Synchronizing power tube driving and bootstrap capacitor charging circuit |
| CN103915990A (en) * | 2014-04-18 | 2014-07-09 | 电子科技大学 | Drive circuit for GaN power devices |
| CN108092651A (en) * | 2018-01-09 | 2018-05-29 | 电子科技大学 | A kind of variable slope driving circuit |
| CN109039029A (en) * | 2018-08-15 | 2018-12-18 | 电子科技大学 | A kind of bootstrap charge circuit circuit suitable for GaN power device gate drive circuit |
| CN209435101U (en) * | 2019-02-28 | 2019-09-24 | 深圳市泰德半导体有限公司 | Driving circuit for power device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109861503A (en) | 2019-06-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108809061B (en) | Switch MOS bootstrap charging circuit suitable for high-speed GaN power device grid drive | |
| EP1831998B1 (en) | Self-timed switching regulator pre-driver | |
| US20060034114A1 (en) | Gate driving circuit and gate driving method of power MOSFET | |
| WO2013071758A1 (en) | Power input load power-on slow starter | |
| JP5733627B2 (en) | Gate drive circuit | |
| US7705638B2 (en) | Switching control circuit with reduced dead time | |
| WO2021017538A1 (en) | Switch power supply, control circuit thereof and control method therefor | |
| CN116742920B (en) | NMOS power switch tube driving circuit and control method thereof | |
| JP2020053766A (en) | Driver circuit | |
| CN109921779B (en) | Half-bridge circuit through protection circuit | |
| US7626429B2 (en) | Driving circuit to drive an output stage | |
| CN107395183B (en) | Pulse high-current ignition switch circuit | |
| CN107204761B (en) | Power tube driving circuit | |
| JP2020025158A (en) | High breakdown voltage integrated circuit | |
| CN102545560B (en) | Power switch driver, IC chip, and DC-DC converter | |
| CN109861503B (en) | Driving circuit for power device | |
| CN113261201A (en) | Apparatus for optimizing turn-off of cascode amplifier | |
| CN113949260B (en) | High-speed high-voltage high-current modulation circuit | |
| CN113054828B (en) | Drive circuit and electrical power generating system of power switch tube | |
| CN115189683A (en) | Drive circuit for low-side NMOS (N-channel metal oxide semiconductor) tube and electronic equipment | |
| CN114915145A (en) | Soft turn-off circuit and method of SiC MOSFET | |
| JP2008147786A (en) | Driving circuit of insulated gate transistor | |
| CN209435101U (en) | Driving circuit for power device | |
| TWI748837B (en) | Gate drive apparatus and control method | |
| JP2020182321A (en) | Gate drive circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |