CN109039029A - A kind of bootstrap charge circuit circuit suitable for GaN power device gate drive circuit - Google Patents

Abstract

A kind of bootstrap charge circuit circuit suitable for GaN power device gate drive circuit, belongs to technical field of power management.Including bootstrap charge circuit module, low tension switch Logic control module, zero crossing detection module, high-voltage switch gear Logic control module and high voltage level displacement module, low tension switch Logic control module generates the low tension switch signal for controlling the first PMOS tube in bootstrap charge circuit module under the control of the first low side control signal, high-voltage switch gear Logic control module is in zero passage detection signal, the high-voltage switch gear signal for controlling the second PMOS tube in bootstrap charge circuit module is generated under the control of first low side control signal and the second under-voltage signal, zero passage detection signal is generated by zero crossing detection module according to the switching node signal that the second low side control signal samples gate drive circuit, high voltage level displacement module is for obtaining the high-voltage switch gear signal of suitable power source rail.The present invention can be avoided the phenomenon that negative pressure overshoots in bootstrap charge circuit, and solve the problems, such as reverse recovery loss and high frequency overcurrent performance degradation.

Description

A bootstrap charging circuit suitable for GaN power device gate drive circuit

technical field

The invention belongs to the technical field of power supply management, and in particular relates to a bootstrap charging circuit suitable for a gate drive circuit of a power device, especially suitable for a gate drive circuit of a GaN power device with high frequency and high power density.

Background technique

With the development of power electronics in recent years, the half-bridge drive circuit is developing towards high power density and high frequency, which also puts forward new requirements for the selection of power tubes and circuit design. Traditional half-bridge drive circuits mainly use silicon power transistors as the power stage. In contrast, because GaN power switching devices (such as GaN high electron mobility transistors: GaN HEMTs, the following descriptions take GaN HEMTs as an example) have high voltage resistance, no Good physical characteristics such as reverse recovery time, so the half-bridge gate drive circuit using GaN power switching devices has excellent characteristics such as high speed and high power density.

Figure 1 shows a traditional bootstrap charging circuit suitable for Si power switching devices. This circuit charges the bootstrap capacitor Cboot during the dead time and the conduction time of the lower power transistor, and charges the bootstrap capacitor _Cboot during the conduction time of the upper power transistor. The high-side drive circuit supplies power. For the half-bridge gate drive circuit, the traditional bootstrap charging circuit is no longer suitable as a floating power rail generation circuit for GaN power switching devices. First, when the traditional bootstrap charging circuit works in the state of charging the bootstrap capacitor C _boot , the potential of the upper plate of the bootstrap capacitor C _boot is approximately the internal power supply VDD of the chip, and the potential of the lower plate is the power switch node voltage SW, while When the GaNHEMT is in the off state, when the current flows from the source terminal to the drain terminal, the drain-source voltage V _DS will have a negative voltage of -2~-3V. Therefore, in the half-bridge gate drive circuit, when the GaN HEMT is used as the power tube, Due to the load pumping of the external load during the dead time, there is a situation where the power stage bias voltage V _SW is negative, and the higher the load current, the more serious the negative voltage situation, which will cause the bootstrap capacitor C _boot to be overshot to the far Higher than the internal power supply VDD of the chip, causing gate-source breakdown of GaN power switching devices (the gate-source breakdown voltage of GaN HEMT is small, requiring VGS<6V, and the best driving voltage is no more than 5.5V). Therefore, control should be added to the traditional bootstrap charging circuit to avoid charging the bootstrap capacitor _Cboot during the dead time. Second, since GaN HEMTs are mostly used in high-voltage and high-frequency application environments, the circuit has high requirements on the load capacity of the bootstrap charging circuit, and must be suitable for MHz high-frequency power supply. However, the on-chip high withstand voltage and fast recovery power Diodes are difficult to realize in the semiconductor process, and the performance of fully integrated high-voltage power diodes will be seriously degraded due to the influence of reverse recovery time and parasitic capacitance in the case of high-frequency power supply. Under the application requirements, the charge consumed on the bootstrap capacitor C _boot cannot be replenished in time, thereby affecting the voltage difference between the floating power rail BST and the switching node SW, deteriorating the performance of the high-side drive circuit and increasing the switching loss of the upper power tube , and even trigger the undervoltage protection to cause the circuit not to work normally.

Contents of the invention

When the above-mentioned traditional bootstrap charging circuit is used as the floating power supply rail generating circuit of the GaN power switching device, the bootstrap capacitor C _boot overshoots due to the negative voltage in the dead time, thereby breaking down the GaN power switching device, and at high frequency and high power Under the application requirements of density, the shortcoming that the charge consumed on the bootstrap capacitor C _boot cannot be replenished in time, the present invention proposes a bootstrap charging circuit for the power device gate drive circuit, especially suitable for GaN power devices with high frequency and high power density The gate drive circuit uses a fully integrated high-voltage switch tube Q2 to replace the bootstrap diode in the traditional bootstrap charging circuit. The switch tube Q2 is only turned on when the lower power tube is turned on, which solves the problem that the voltage at the power switch node SW is negative during the dead time. The problem of overshoot of the bootstrap capacitor C _boot , and there is no reverse recovery and reverse recovery loss, and the switch tube Q2 will not have the problem of overcurrent performance degradation under high frequency conditions.

Technical scheme of the present invention is:

A bootstrap charging circuit suitable for a GaN power device gate drive circuit, the gate drive circuit includes an upper power tube and a lower power tube, the bootstrap charging circuit includes a bootstrap charging module, a low-voltage switch logic control module, a zero-crossing Detection module, high voltage switch logic control module and high voltage level shift module;

The bootstrap charging module includes a first PMOS transistor Q1, a second PMOS transistor Q2, and a bootstrap capacitor _Cboot , wherein the first PMOS transistor Q1 is a low-voltage transistor, and the second PMOS transistor Q2 is a high-voltage transistor;

The source of the first PMOS transistor Q1 is connected to the power supply voltage V _DD , its drain is connected to the drain of the second PMOS transistor Q2 , and its gate is connected to the low voltage switching signal LV _G ;

The gate of the second PMOS transistor Q2 is connected to the high-voltage switching signal HV _G , and its source is connected to the upper plate of the bootstrap capacitor C _boot as a floating power supply rail BST;

The lower plate of the bootstrap capacitor C _boot is connected to the switch node SW of the gate drive circuit;

The low-voltage switch logic control module is enabled by the enable signal EN, and generates the low-voltage switch signal LVG under the control of the first low-side control signal _{DRVL_FB0} , and the low-voltage switch signal _LVG is related to the first low-side The side control signal DRVL_FB0 is inverted;

The enable signal EN is in phase with the first undervoltage signal UVLO, and the first undervoltage signal UVLO is an undervoltage signal of the power supply voltage _VDD ;

The zero-crossing detection module is enabled by the enable signal EN, under the control of the second low-side control signal DRVL_FB, samples the signal of the switch node SW of the gate drive circuit and generates a zero-crossing detection signal ZVS_out, when the When the signal of the switching node SW of the gate driving circuit is high voltage, the zero-crossing detection signal ZVS_out outputs a low level, and when the signal of the switching node SW of the gate driving circuit is 0, the zero-crossing detection signal ZVS_out outputs a high level ;

The first low-side control signal DRVL_FB0 and the second low-side control signal DRVL_FB are signals in phase with the gate drive signal of the lower power transistor, and the second low-side control signal DRVL_FB is the first low-side control signal DRVL_FB The control signal DRVL_FB0 is obtained after a delay;

The high-voltage switch logic control module is enabled by the enable signal EN, and is used to generate a judgment signal Ctr according to the zero-crossing detection signal ZVS_out and the first low-side control signal DRVL_FB0;

The high-voltage level shift module is used to transfer the power rail of the judgment signal Ctr from the power supply voltage V _DD to the ground from the signal at the floating power rail BST to the signal at the switch node SW;

The high-voltage switch logic control module generates the high-voltage switch signal _HVG according to the judgment signal Ctr and the second undervoltage signal UVLO_HS processed by the high-voltage level shift module, and only when the second undervoltage signal When UVLO_HS, the first low-side control signal DRVL_FB0 and the zero-crossing detection signal ZVS_out are all at high level, the high voltage switch signal HV _G is at low level; otherwise, the high voltage switch signal HV _G is at high level;

The second undervoltage signal UVLO_HS is an undervoltage signal between the floating power supply rail BST and the switching node SW.

Specifically, the zero-crossing detection module includes a first inverter INV1, a first resistor R ₁ , a second resistor R ₂ , a third resistor R ₃ , a fourth resistor R ₄ , a fifth resistor R ₅ , and a sixth resistor R ₆ , seventh resistor R ₇ , eighth resistor R ₈ , ninth resistor R ₉ , tenth resistor R ₁₀ , first NMOS transistor MN ₁ , second NMOS transistor MN ₂ , third NMOS transistor MN ₃ , fourth NMOS transistor MN ₄ , fifth NMOS transistor MN ₅ , sixth NMOS transistor MN ₆ , seventh NMOS transistor MN ₇ , eighth NMOS transistor MN ₈ , ninth NMOS transistor MN ₉ , tenth NMOS transistor MN ₁₀ , and eleventh NMOS transistor MN 10 NMOS tube MN ₁₁ , twelfth NMOS tube MN ₁₂ , thirteenth NMOS tube MN ₁₃ , fourteenth NMOS tube MN ₁₄ , fifteenth NMOS tube MN ₁₅ , sixteenth NMOS tube MN ₁₆ , seventeenth NMOS tube MN ₁₇ , eighteenth NMOS transistor MN ₁₈ , nineteenth NMOS transistor MN ₁₉ , twentieth NMOS transistor M ₁ , twenty-first NMOS transistor M ₂ , twenty-second NMOS transistor M ₃ , twenty-third NMOS transistor The tube M ₄ , the twenty-fourth NMOS tube M ₅ , the twenty-fifth NMOS tube MH1 , the first PMOS tube MP ₁ , the second PMOS tube MP ₂ , the third PMOS tube MP ₃ , the fourth PMOS tube MP ₄ , the Fifth PMOS transistor MP ₅ , sixth PMOS transistor MP ₆ , seventh PMOS transistor MP ₇ , eighth PMOS transistor MP ₈ , ninth PMOS transistor MP ₉ , tenth PMOS transistor MP ₁₀ , eleventh PMOS transistor MP ₁₁ , Twelve PMOS transistors MP ₁₂ , thirteenth PMOS transistors MP ₁₃ , fourteenth PMOS transistors MP ₁₄ , fifteenth PMOS transistors MP ₁₅ , sixteenth PMOS transistors MP ₁₆ and seventeenth PMOS transistors MP ₁₇ , of which the second Fifteen NMOS tube MH1 is a high pressure tube;

One end of the _tenth resistor R10 is connected to the switch node SW of the gate drive circuit, and the other end is connected to the drain of the twenty-fifth NMOS transistor MH1;

_The gate of the twentieth NMOS transistor M1 is connected to the gates of the twenty-fifth NMOS transistor MH1 and the twenty-first NMOS transistor _M2 and is connected to the second low-side control signal DRVL_FB, and its source is connected to the twenty-fifth The source of the NMOS transistor MH1, the drain of which is connected to the source of the twenty _- first NMOS transistor _M2 and the drain of the twenty-fourth NMOS transistor M5;

The drain of the twenty-first NMOS transistor _M2 is connected to the drain of the twenty _- third NMOS transistor M4 and outputs a sampling signal Vsense;

The gate of the twenty-second NMOS transistor M3 is connected to the gates of the twenty _{- third} NMOS transistor M4 and the twenty- _fourth NMOS transistor M5 and is connected to the inverted signal of the second low-side control signal DRVL_FB, and its drain The pole is connected to the first reference voltage RefH, and its source is connected to the source of the twenty _- third NMOS transistor M4;

_The source of the twenty-fourth NMOS transistor M5 is grounded;

The gate of the _sixteenth PMOS transistor MP16 is connected to the sampling signal Vsense, its source is connected to the source of the _seventeenth PMOS transistor MP17 and connected to the drain of the _fifth PMOS transistor MP5 after passing through the third resistor _R3 , Its drain is connected to the source of the _eighth NMOS transistor MN8 and the drain of the _ninth NMOS transistor MN9;

The gate of the _seventeenth PMOS transistor MP17 is connected to the second reference voltage RefL, and its drain is connected to the source of the _tenth NMOS transistor MN10 and the drain of the _eleventh NMOS transistor MN11;

The source of the _fifth PMOS transistor MP5 is connected to the drain of the sixth PMOS transistor _MP6 ;

The gate of the _ninth NMOS transistor MN9 is connected to the gate of the _eleventh NMOS transistor MN11;

The gate of the _eighth NMOS transistor MN8 is connected to the gate of the _tenth NMOS transistor MN10, and its drain is connected to the gate of the _twelfth NMOS transistor MN12 and connected to the gate of the _seventh PMOS transistor MP7 after passing through the _fourth resistor R4. gate and drain;

One end of the _fifth resistor R5 is connected to the gate of the _seventh PMOS transistor MP7, and the other end is connected to the drain of the _tenth NMOS transistor MN10 and the gate of the _thirteenth NMOS transistor MN13;

The gate of the _first NMOS transistor MN1 is connected to the inverse signal of the first undervoltage signal UVLO, and its drain is connected to the gate of the _third NMOS transistor MN3, the gate and drain of the _second NMOS transistor MN2, and The source of the bias signal BIAS is connected to the second NMOS transistor MN ₂ , the third NMOS transistor MN ₃ , the fifth NMOS transistor MN ₅ , the seventh NMOS transistor MN ₇ , the ninth NMOS transistor MN ₉ , and the eleventh NMOS transistor MN _11. The fifteenth NMOS transistor MN ₁₅ , the sixteenth NMOS transistor MN ₁₆ and the seventeenth NMOS transistor MN ₁₇ ;

The gate of the _second PMOS transistor MP2 is connected to the gates of the _third PMOS transistor MP3, the _fifth PMOS transistor MP5 and the _tenth PMOS transistor MP10 and the drain of the _third NMOS transistor MN3 through the _first resistor R1 Then connect the drain of the second PMOS transistor MP ₂ and the gates of the first PMOS transistor MP ₁ , the fourth PMOS transistor MP ₄ , the sixth PMOS transistor MP ₆ and the ninth PMOS transistor MP ₉ , and connect the source of the first PMOS transistor MP The drain of the tube MP ₁ ;

The drain of the _fourth PMOS transistor MP4 is connected to the source of the _third PMOS transistor MP3, and its source is connected to the _first PMOS transistor MP1, the sixth PMOS transistor _MP6 , the _seventh PMOS transistor MP7, and the eighth PMOS transistor MP _8. The sources of the ninth PMOS transistor MP ₉ , the eleventh PMOS transistor MP ₁₁ and the fourteenth PMOS transistor MP ₁₄ are connected to the power supply voltage V _DD ;

The gate of the _fourth NMOS transistor MN4 is connected to the gates of the _sixth NMOS transistor MN6 and the _fourteenth NMOS transistor MN14 and the drain of the _third PMOS transistor MP3 and connected to the fourth NMOS transistor after passing through the _second resistor R2 The drain of MN ₄ and the gates of the fifth NMOS transistor MN ₅ , the seventh NMOS transistor MN ₇ and the fifteenth NMOS transistor MN ₁₅ have their sources connected to the drain of the fifth NMOS transistor MN ₅ ;

The source of the _fourteenth NMOS transistor MN14 is connected to the drain of the _fifteenth NMOS transistor MN15, and the drain is connected to the sources of the _twelfth NMOS transistor MN12 and the _thirteenth NMOS transistor MN13;

One end of the _sixth resistor R6 is connected to the gate and drain of the _eighth PMOS transistor MP8 and one end of the seventh resistor _R7 , and the other end is connected to the drain of the _twelfth NMOS transistor MN12 and the thirteenth PMOS transistor MP ₁₃ and the gate of the eighteenth NMOS transistor MN ₁₈ ;

The gate of the _twelfth PMOS transistor MP12 is connected to the other end of the seventh resistor _R7 , the drain of the _thirteenth NMOS transistor MN13 and the gate of the _nineteenth NMOS transistor MN19, and its source is connected to the thirteenth PMOS transistor. The source of the tube MP ₁₃ and the drain of the tenth PMOS tube MP ₁₀ , the drain of which is connected to the gate and drain of the sixteenth NMOS tube MN ₁₆ and connected to the thirteenth PMOS tube MP ₁₃ after passing through the eighth resistor R ₈ and the gate of the _seventeenth NMOS transistor MN17;

The source of the _tenth PMOS transistor MP10 is connected to the drain of the _ninth PMOS transistor MP9;

The gate of the _fourteenth PMOS transistor MP14 is connected to the drain of the _eighteenth NMOS transistor MN18 and connected to the gate and drain of the _eleventh PMOS transistor MP11 and the nineteenth NMOS transistor MN through the ninth resistor _R9 The drain of ₁₉ is connected to the drain of the seventeenth NMOS transistor MN ₁₇ and the fifteenth PMOS transistor MP ₁₅ and the input terminal of the first inverter INV1;

The drain of the _sixth NMOS transistor MN6 is connected to the sources of the _eighteenth NMOS transistor MN18 and the _nineteenth NMOS transistor MN19, and the source is connected to the drain of the _seventh NMOS transistor MN7;

The gate of the _fifteenth PMOS transistor MP15 is connected to the enable signal EN, and its source is connected to the power supply voltage V _DD ;

The output terminal of the first inverter INV1 outputs the zero-crossing detection signal ZVS_out.

Work process and working principle of the present invention are:

When the power supply voltage V _DD is undervoltage, the enable signal EN outputs a low level, the low-voltage switch logic control module, the zero-crossing detection module and the high-voltage switch logic control module do not work, and the low-voltage switch signal LV _G and the high-voltage switch signal HV _G are high voltage. Turn off the first PMOS transistor Q1 and the second PMOS transistor Q2, so as to turn off the bootstrap charging path and not charge the bootstrap capacitor to C _boot t; after the power supply voltage V _DD is powered on normally, the enable signal EN outputs a high level Enable the low-voltage switch logic control module, the zero-crossing detection module and the high-voltage switch logic control module.

When the power supply voltage V _DD is powered on, the enable signal EN outputs a high level, and the lower power transistor is first unlocked, and the low-voltage switch logic control module generates a low-level signal when the first low-side control signal DRVL_FB0 is high-level The low-voltage switching signal LV _G turns on the first PMOS transistor Q1, releases the bootstrap path, and enables the bootstrap capacitor C _boot to charge slowly when the lower power transistor is turned on. According to whether there is undervoltage between the floating power rail BST and the switching node SW, the second undervoltage signal UVLO_HS is obtained. When the voltage between the floating power rail BST and the switching node SW is undervoltage, the second undervoltage signal UVLO_HS is at a low level to control the high voltage switch. The logic control module generates a high-level high-voltage switch signal HV _G to turn off the second PMOS transistor Q2. Therefore, when the power supply voltage V _DD is powered on and the voltage between the floating power rail BST and the switch node SW is undervoltage, the first PMOS transistor Q1 is turned on and the second PMOS transistor Q2 is turned off, and the body diode of the second PMOS transistor Q2 is charged with current limiting mode to charge the bootstrap capacitor C _boot .

When the power supply voltage V _DD is powered on and the connection between the floating power rail BST and the switch node SW is also powered on, the enable signal EN and the second undervoltage signal UVLO_HS are both at high level, and the low-voltage switch logic control module according to the first The low-side control signal DRVL_FB0 controls the first PMOS transistor Q1 to turn on or off, and the high-voltage switch logic control module controls the second PMOS transistor Q2 to turn on or off according to the zero-crossing detection signal ZVS_out, the first low-side control signal DRVL_FB0 and the second undervoltage signal UVLO_HS off.

When the first low-side control signal _{DRVL_FB0} is at a low level, the low-voltage switch signal LVG is at a high level to turn off the first PMOS transistor Q1, and the switch node SW is at a high voltage so that the zero-crossing detection signal ZVS_out outputs a low level to generate a high level The high voltage switch signal HV _G turns off the second PMOS transistor Q2. Therefore, the power-on of the power supply voltage V _DD is completed, and the power-on between the floating power rail BST and the switch node SW is also completed, but when a negative voltage occurs at the switch node SW, the first PMOS transistor Q1 and the second PMOS transistor Q2 are turned off, so that The back-to-back diode between the power supply voltage VDD and the bootstrap capacitor C _boot blocks the path between the power supply voltage VDD and the bootstrap capacitor C _boot , preventing the bootstrap capacitor C _boot from being charged when the voltage at the switch node SW enters a negative voltage .

When the first low-side control signal _{DRVL_FB0} is at a high level, the low-voltage switching signal LVG is at a low level to turn on the first PMOS transistor Q1, and the voltage drop at the switch node SW is 0, so that the zero-crossing detection signal ZVS_out outputs a high level to generate a low voltage. The flat high-voltage switching signal HV _G turns on the second PMOS transistor Q2. Therefore, when the power supply voltage V _DD is powered on, the connection between the floating power rail BST and the switch node SW is also powered on, and the voltage at the switch node SW is 0, the first PMOS transistor Q1 and the second PMOS transistor Q2 are turned on, and the bootstrap The charging circuit works normally, and the charging speed of the bootstrap capacitor C _boot is determined by the sum of the on-resistance Rds_on of the first PMOS transistor Q1 and the second PMOS transistor Q2 and the RC time constant of the bootstrap capacitor C _boot .

The truth table of the circuit state corresponding to each logic signal is as follows:

The beneficial effects of the present invention are: the bootstrap charging circuit provided by the present invention adopts a double switch mode to prevent negative pressure problems and charges the bootstrap capacitor C boot in a high-voltage switch mode, and charges the bootstrap capacitor C _boot when and only when the power tube is turned on. _Boot charging avoids the phenomenon of negative voltage overshoot; the second switching tube Q2 replaces the bootstrap diode, so there will be no misoperation caused by the voltage crosstalk at the switch node SW, and the reverse recovery loss and high frequency of the bootstrap diode are eliminated. Over-current performance degradation issues, especially for powering floating power rails for high-frequency high-power-density GaN gate drives.

Description of drawings

Figure 1 is a topology diagram of a bootstrap charging circuit using a bootstrap diode in a traditional half-bridge drive circuit.

FIG. 2 is a topological diagram of an embodiment of a bootstrap charging circuit suitable for a GaN power device gate drive circuit proposed by the present invention.

FIG. 3 is a circuit realization diagram of the zero-crossing detection module in an embodiment of the present invention.

FIG. 4 is a working control waveform diagram of a bootstrap charging circuit suitable for a GaN power device gate drive circuit proposed by the present invention.

FIG. 5 is a structural diagram of a circuit for obtaining the second undervoltage signal UVLO_HS in the present invention.

Detailed ways

The technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

The bootstrap charging circuit proposed by the present invention can be applied to the gate drive circuit of GaN power devices or Si power devices, including a bootstrap charging module, a low-voltage switch logic control module, a zero-crossing detection module, a high-voltage switch logic control module and a high-voltage level The displacement module, wherein the bootstrap charging module includes a first PMOS transistor Q1, a second PMOS transistor Q2 and a bootstrap capacitor C _boot , the source of the first PMOS transistor Q1 is connected to the power supply voltage V _DD , and its drain is connected to the second PMOS transistor Q2 The drain of the second PMOS transistor Q2 is connected to the low-voltage switching signal LV _G ; the gate of the second PMOS transistor Q2 is connected to the high-voltage switching signal HV _G , and its source is connected to the upper plate of the bootstrap capacitor C _boot and used as a floating power supply rail BST; The lower plate of the lifting capacitor C _boot is connected to the switching node SW of the gate driving circuit. The first PMOS transistor Q1 is a low-voltage transistor, which is used to disconnect the power supply path from the power supply voltage V _DD to the bootstrap capacitor C _boot when a negative voltage appears; the second PMOS transistor Q2 is a high-voltage transistor, and the second PMOS transistor Q2 can use a P-type For high-voltage LDMOS transistors, when PLDMOS is used as a high-voltage switch, the source of PLDMOS can only be connected to the floating power rail BST because the body diode of the LDMOS channel is pinched off and needs to withstand reverse voltage, so the gate signal needs to be referenced to the switch node SW , so the range of the PLDMOS gate signal is between BST-SW, and will not be subject to the problem of misoperation caused by the dv/dt crosstalk of the voltage Vsw at the power switch node SW; and since the bootstrap diode is replaced with only the low-side power transistor The high-voltage switch that is turned on when it is turned on, this bootstrap charging method will not have the problem of overshoot of the bootstrap capacitor C _boot caused by the negative voltage of the power switch node SW during the dead time, and also eliminates the diode reverse recovery loss and High-frequency over-current performance degradation problem, suitable for floating power rail power supply of high-frequency GaN gate drive.

The enable signal EN is in phase with the first undervoltage signal UVLO, and the first undervoltage signal UVLO is an undervoltage signal of the power supply voltage V _DD . When the power supply voltage V _DD is undervoltage, the first undervoltage signal UVLO outputs a low level, and the power supply voltage V After the _DD is powered on, the first undervoltage signal UVLO outputs a high level. As shown in Figure 2, the first undervoltage signal UVLO can be ANDed with the reference establishment enable signal Bias_ok to generate the enable signal EN, so that when the power supply voltage V _DD is undervoltage, the enable signal EN outputs a low level to turn off the bootstrap charging Circuit, after the power supply voltage V _DD is powered on, the enable signal EN outputs a high level to turn on the bootstrap charging circuit, wherein the reference establishment enable signal Bias_ok is the enable signal for the system to establish each reference signal.

The low-voltage switch logic control module is enabled by the enable signal EN, works when the enable signal EN is at a high level, and generates a low-voltage switch signal LVG under the control of the first low-side control signal _{DRVL_FB0} , and the low-voltage switch signal _LVG and the second A low-side control signal DRVL_FB0 is inverted, as shown in FIG. 2 , which provides a circuit implementation form of the low-voltage switch logic control module.

The zero-crossing detection module is enabled by the enable signal EN, works when the enable signal EN is at a high level, and samples the signal of the switching node SW of the gate drive circuit under the control of the second low-side control signal DRVL_FB and generates zero-crossing detection Signal ZVS_out, when the lower power transistor is turned off, the first low-side control signal DRVL_FB0 and the second low-side control signal DRVL_FB are at low level, the signal of the switching node SW of the gate drive circuit is at high voltage, and the zero-crossing detection signal ZVS_out outputs a low level Level; when the lower power transistor is turned on, the first low-side control signal DRVL_FB0 and the second low-side control signal DRVL_FB are at high level, the signal at the switch node SW of the gate drive circuit is 0, and the zero-crossing detection signal ZVS_out outputs high level.

As shown in Figure 3, a circuit implementation form of the zero-crossing detection module is given. The zero-crossing detection module is composed of a SW detection circuit and a high-speed comparator, wherein the high-speed comparator is a multi-level comparator, the first level and the second level It is a low-gain stage, the third stage adopts a high-gain stage structure, and the third stage performs single-ended to double-ended processing so that the output stage becomes a push-pull push-pull structure to improve response speed.

The maximum output voltage of the comparator is:

V _OH = VDD (1)

The minimum output voltage is:

V _OL = VSS (2)

The small signal gain of the comparator is:

A _v (0)＝g _m,MP16 g _m,MN13 ·[R ₅ ||(r _o,MN10 +r _o,MN11 )]·[R ₇ ||r _o,MN13 ]·[(g _m,MP13 R ₈ +g _{m, MN19} R ₉ )](3)

Among them, g _m represents the transconductance of the MOS tube, and r _o represents the output resistance of the MOS tube. The accuracy of the comparator is expressed as:

From expressions (3) and (4), it can be seen that by reasonably designing the values of the fifth resistor R ₅ , the seventh resistor R ₇ , the eighth resistor R ₈ and the ninth resistor R ₉ , the high-speed comparator can be The low frequency gain is relatively high, and the accuracy of the comparator is also high. The propagation delay of the comparator is expressed as:

SR is the slew rate of the comparator. The third stage of the comparator in this embodiment adopts a single-ended to double-ended structure, so that the output stage becomes a push-pull structure, which greatly reduces the transmission delay of the entire comparator.

The first NMOS transistor MN ₁ and the fifteenth PMOS transistor MP ₁₅ are power-on enabling transistors, and the zero-crossing detection module does not work when the chip is powered on until it is under-voltage unlocked. After the chip works normally, the first NMOS transistor MN ₁ and the fifteenth PMOS transistor MP ₁₅ are turned off. The seventh PMOS transistor MP ₇ , the eighth PMOS transistor MP ₈ , the sixteenth NMOS transistor MN ₁₆ , and the eleventh PMOS transistor MP ₁₁ are used to set the input common-mode levels of circuits at all levels. The SW detection circuit consists of the twenty-fifth NMOS tube MH1 of the high-voltage tube and the twenty-fifth NMOS tube M1 of the low-voltage tube, the twenty- _first NMOS tube _M2 , the twenty-second NMOS tube M3, and the twenty _{- third} NMOS tube M4 and the twenty-fourth NMOS tube M5: the twenty- _fifth NMOS tube MH1 can be an LDMOS tube, and the drain terminal is connected to the voltage V _SW at the power switch node SW to prevent high voltage; the twenty-fourth NMOS tube M1 and the twenty _- fourth NMOS tube The tube _M5 is a negative pressure absorbing circuit, which prevents the internal circuit from being affected by the voltage V _SW at the power switch node SW entering the negative pressure during the dead time period; the twenty-first NMOS tube _M2 , the twenty _- second NMOS tube M3 and The twenty _- third NMOS transistor M4 is used to prevent the signal of the latch at the source of the twenty-first NMOS transistor _M2 , the sampling signal Vsense and the first reference voltage RefH from influencing each other.

Both the first low-side control signal DRVL_FB0 and the second low-side control signal DRVL_FB are signals in phase with the gate drive signal of the lower power transistor, and the second low-side control signal DRVL_FB is obtained by delaying the first low-side control signal DRVL_FB0 , this is because when the voltage at the switch node SW has increased from a low voltage to a high voltage, the zero-crossing detection module still needs a certain response delay before it can output logic information including that the voltage at the switch node SW and the floating power rail BST has increased. This delay will cause the second PMOS transistor Q2 of the high-voltage tube to fail to turn off in time when the voltage of the switch node SW and the floating power rail BST has risen, resulting in the inability to block the high voltage from being applied to the first PMOS transistor Q1 of the low-voltage tube in time, resulting in The first PMOS transistor Q1 breaks down and leaks electricity to the power supply voltage VDD. Therefore, the zero-crossing detection module is controlled by the second low-side control signal DRVL_FB, and the second PMOS transistor Q2 is directly turned off by the first low-side control signal DRVL_FB0 after a certain delay of the second low-side control signal DRVL_FB.

The high-voltage switch logic control module is enabled by the enable signal EN, works when the enable signal EN is at a high level, and generates a judgment signal Ctr according to the zero-crossing detection signal ZVS_out and the first low-side control signal DRVL_FB0; due to the power of the judgment signal Ctr The rail is the power supply voltage V _DD to ground, so a high-voltage level shift module is required to transfer the judgment signal Ctr from the low-side power rail of the power supply voltage V _DD to ground to the high side of the signal at the floating power rail BST to the signal at the switch node SW Floating power supply rail; the signal after being transferred to the high-side floating power supply rail and the second high-side undervoltage signal UVLO_HS together generate a high-voltage switching signal HV _G , because the second undervoltage signal UVLO_HS is between the floating power supply rail BST and the switching node SW The supply rail is also the high-side supply rail for the signal at floating supply rail BST to the signal at switching node SW. As shown in Figure 2, a circuit implementation form of the high-voltage switch logic control module is given. The high-voltage level shift module in this embodiment is also used to invert the judgment signal Ctr and output it. Only when the second undervoltage signal When UVLO_HS, the first low-side control signal DRVL_FB0 and the zero-crossing detection signal ZVS_out are all at high level, the output high-voltage switch signal HV _G is at low level to turn on the second PMOS transistor Q2; otherwise, the output high-voltage switch signal HV _G is at high level to turn off Turn off the second PMOS transistor Q2.

When the bootstrap charging circuit proposed by the present invention is charging normally, the first PMOS transistor Q1 and the second PMOS transistor Q2 are turned on, and the charging speed of the bootstrap capacitor and C _boot is determined by the on-resistance of the first PMOS transistor Q1 and the second PMOS transistor Q2 The sum of Rds_on is determined by the RC time constant of the bootstrap capacitor C _boot ; when the bootstrap capacitor C _boot is powered on, the first PMOS transistor Q1 is selected to be turned on, the second PMOS transistor Q2 is turned off, and the second PMOS transistor Q2 is used for the high voltage tube Diodes limit the charging current mode; when negative voltage occurs, the first PMOS transistor Q1 and the second PMOS transistor Q2 are disconnected, and the back-to-back diode is between the power supply voltage VDD and the bootstrap capacitor C _boot , blocking the power supply voltage VDD and the bootstrap capacitor. The path between the capacitors C _boot prevents the bootstrap capacitor C _boot from being charged when the voltage at the power switch node SW enters a negative voltage.

The undervoltage signal of the power supply voltage V _DD is the control signal with the highest enable priority in the chip. When the power supply of the chip is abnormal, that is, when the power supply voltage V _DD is undervoltage, all modules of the chip should be turned off through the enable signal EN, thereby shutting down The upper and lower power tubes disconnect the bootstrap power supply path. When the power supply voltage V _DD undervoltage is over, unlock the lower power transistor first, release the bootstrap path, so that the bootstrap capacitor _Cboot can be slowly charged when the lower power transistor is turned on; when the high-side power rail voltage difference BST-SW is undervoltage, Lock the upper power tube to ensure the smooth progress of bootstrap charging; after the end of the high-side power rail voltage drop, the BST-SW stabilizes at the working voltage, and then unlock the upper power tube.

After the power supply voltage V _DD and bias are powered on, the enable signal EN turns high to unlock the first PMOS transistor Q1. When the enable signal EN is the second undervoltage signal UVLO_HS is low, the first PMOS transistor Q1 is turned on by the first The low-side control signal DRVL_FB0 is controlled. When the first low-side control signal DRVL_FB0 is high, the first PMOS transistor Q1 is turned on. When the first low-side control signal DRVL_FB0 is low, the first PMOS transistor Q1 is turned off. When the first PMOS transistor Q1 is turned on, it is The second PMOS transistor Q2 charges the bootstrap capacitor C _boot in the body diode current limiting charging mode. After the high-side power rail voltage difference BST-SW is powered on, the second undervoltage signal UVLO_HS turns high to unlock the second PMOS transistor Q2,

When both the enable signal EN and the second undervoltage signal UVLO_HS are high, both the first PMOS transistor Q1 and the second PMOS transistor Q2 are unlocked, and the opening of the first PMOS transistor Q1 is also controlled by the first low-side control signal DRVL_FB0, and the second The opening of the PMOS transistor Q2 is controlled by the first low-side control signal DRVL_FB0 and the zero-crossing detection signal ZVS_out. When the second undervoltage signal UVLO_HS, the first low-side control signal DRVL_FB0 and the zero-crossing detection signal ZVS_out are all high, the second PMOS When the tube Q2 is turned on, the charging speed of the bootstrap capacitor C _boot is the RC time constant determined by (R _{ds_on-Q1} +R _{ds_on-Q2} )*Cboot.

As shown in Figure 5, it is a circuit realization structure diagram of driving the second undervoltage signal UVLO_HS according to the voltage between the floating power supply rail BST and the switching node SW. The second undervoltage signal UVLO_HS is at a low level, and the second undervoltage signal UVLO_HS output when the power-on between the floating power rail BST and the switch node SW is completed is at a high level.

In summary, according to the physical characteristics of the bootstrap diode in the traditional bootstrap scheme, the present invention designs a dual-switch bootstrap charging scheme. When the supply voltage V _DD is undervoltage, each module of the bootstrap charging circuit is turned off, and the bootstrap charging circuit is switched off. The capacitor C _boot is not charged; after the power supply voltage V _DD is powered on normally, when the BST-SW is undervoltage, turn on the first PMOS transistor Q1 and turn off the second PMOS transistor Q2, and use the current limiting charging mode to charge the bootstrap capacitor C _boot ; the power supply After the voltage V _DD and BST-SW are powered on normally, if the switch node SW is at high voltage, turn off the first PMOS transistor Q1 and the second PMOS transistor Q2, and if the voltage at the switch node SW is approximately 0, turn on the first PMOS transistor Q1 and the second PMOS tube Q2, the bootstrap charging circuit works normally. The bootstrap charging circuit of the present invention charges the bootstrap capacitor _Cboot when the lower power tube is turned on, avoiding the phenomenon of negative voltage overshoot; the first PMOS transistor Q1 is used to disconnect the power supply voltage V _DD to the bootstrap capacitor when the negative voltage appears. C _boot power supply path; the second switching tube Q2 replaces the bootstrap diode, and there will be no misoperation caused by voltage crosstalk at the switch node SW, eliminating the reverse recovery loss of the bootstrap diode and the degradation of high-frequency overcurrent performance question.

It is worth noting that the system control method and specific circuit design used in the present invention can also be applied to the driving circuits of Si power switching devices and other wide bandgap semiconductor switching devices (such as SiC power switching devices), specifically, for Si In the gate drive circuit of the power switching device, the body diode of the power transistor freewheels during the dead time, and the voltage at the switch node SW will drop to a negative voltage of -0.7V during the dead time, even under extremely heavy load conditions, the Si power The gate drive circuit of the switching device will also reduce the SW to a very negative negative voltage due to the body resistance of its own body diode. The invention is equally applicable to this application.

Those skilled in the art can make various other specific modifications and combinations based on the technical revelations disclosed in the present invention without departing from the essence of the present invention, and these modifications and combinations are still within the protection scope of the present invention.

Claims (2)

1. a kind of bootstrap charge circuit circuit suitable for GaN power device gate drive circuit, the gate drive circuit include upper power Pipe and lower power tube, which is characterized in that the bootstrap charge circuit circuit includes bootstrap charge circuit module, low tension switch logic control mould Block, zero crossing detection module, high-voltage switch gear Logic control module and high voltage level displacement module；

The bootstrap charge circuit module includes the first PMOS tube (Q1), the second PMOS tube (Q2) and bootstrap capacitor (C_boot), wherein first PMOS tube (Q1) is low-voltage tube, and the second PMOS tube (Q2) is high-voltage tube；

The source electrode of first PMOS tube (Q1) connects supply voltage (V_DD), the drain electrode of drain electrode connection the second PMOS tube (Q2), grid Pole connects low tension switch signal (LV_G)；

The grid of second PMOS tube (Q2) connects high-voltage switch gear signal (HV_G), source electrode connects bootstrap capacitor (C_boot) top crown And as floating power supply rail (BST)；

Bootstrap capacitor (C_boot) bottom crown connect the switching node (SW) of the gate drive circuit；

The low tension switch Logic control module is enabled by the enable signal (EN), in the first low side control signal (DRVL_ FB0 the low tension switch signal (LV is generated under control)_G), the low tension switch signal (LV_G) controlled with first downside Signal (DRVL_FB0) reverse phase；

The enable signal (EN) and the first same phase of under-voltage signal (UVLO), the first under-voltage signal (UVLO) are the power supply Voltage (V_DD) under-voltage signal；

The zero crossing detection module is enabled by the enable signal (EN), in the control of the second low side control signal (DRVL_FB) The signal of the switching node (SW) of gate drive circuit described in down-sampling simultaneously generates zero passage detection signal (ZVS_out), when the grid The signal of the switching node (SW) of driving circuit zero passage detection signal (ZVS_out) output low level when being high pressure, works as institute The signal for stating the switching node (SW) of gate drive circuit zero passage detection signal (ZVS_out) output high level when being 0；

First low side control signal (DRVL_FB0) and the second low side control signal (DRVL_FB) are and the lower power tube Gate drive signal with phase signal, and second low side control signal (DRVL_FB) be first downside control letter Number (DRVL_FB0) is obtained by delay；

The high-voltage switch gear Logic control module is enabled by the enable signal (EN), for according to the zero passage detection signal (ZVS_out) and the first low side control signal (DRVL_FB0) generation judges signal (Ctr)；

The high voltage level displacement module is used for the power rail by judgement signal (Ctr) from supply voltage (V_DD) shifted to ground For signal signal at the switching node (SW) at the floating power supply rail (BST)；

The high-voltage switch gear Logic control module is according to by the high voltage level displacement module treated the judgement signal (Ctr) and the second under-voltage signal (UVLO_HS) generates the high-voltage switch gear signal (HV_G), only when the described second under-voltage signal (UVLO_HS), it is described when the first low side control signal (DRVL_FB0) and zero passage detection signal (ZVS_out) are high level High-voltage switch gear signal (HV_G) it is low level；Otherwise the high-voltage switch gear signal (HV_G) it is high level；

Under-voltage letter of the second under-voltage signal (UVLO_HS) between the floating power supply rail (BST) and switching node (SW) Number.

2. the bootstrap charge circuit circuit according to claim 1 suitable for GaN power device gate drive circuit, feature exist In the zero crossing detection module includes the first phase inverter (INV1), first resistor (R₁), second resistance (R₂), 3rd resistor (R₃), the 4th resistance (R₄), the 5th resistance (R₅), the 6th resistance (R₆), the 7th resistance (R₇), the 8th resistance (R₈), the 9th resistance (R₉), the tenth resistance (R₁₀), the first NMOS tube (MN₁), the second NMOS tube (MN₂), third NMOS tube (MN₃), the 4th NMOS tube (MN₄), the 5th NMOS tube (MN₅), the 6th NMOS tube (MN₆), the 7th NMOS tube (MN₇), the 8th NMOS tube (MN₈), the 9th NMOS Manage (MN₉), the tenth NMOS tube (MN₁₀), the 11st NMOS tube (MN₁₁), the 12nd NMOS tube (MN₁₂), the 13rd NMOS tube (MN₁₃), the 14th NMOS tube (MN₁₄), the 15th NMOS tube (MN₁₅), the 16th NMOS tube (MN₁₆), the 17th NMOS tube (MN₁₇), the 18th NMOS tube (MN₁₈), the 19th NMOS tube (MN₁₉), the 20th NMOS tube (M₁), the 21st NMOS tube (M₂), the 22nd NMOS tube (M₃), the 23rd NMOS tube (M₄), the 24th NMOS tube (M₅), the 25th NMOS tube (MH1), the first PMOS tube (MP₁), the second PMOS tube (MP₂), third PMOS tube (MP₃), the 4th PMOS tube (MP₄), the 5th PMOS Manage (MP₅), the 6th PMOS tube (MP₆), the 7th PMOS tube (MP₇), the 8th PMOS tube (MP₈), the 9th PMOS tube (MP₉), the tenth PMOS tube (MP₁₀), the 11st PMOS tube (MP₁₁), the 12nd PMOS tube (MP₁₂), the 13rd PMOS tube (MP₁₃), the 14th PMOS Manage (MP₁₄), the 15th PMOS tube (MP₁₅), the 16th PMOS tube (MP₁₆) and the 17th PMOS tube (MP₁₇), wherein the 25th NMOS tube (MH1) is high-voltage tube；

Tenth resistance (R₁₀) one end connects the switching node (SW) of the gate drive circuit, the other end connects the 25th NMOS tube (MH1) drain electrode；

20th NMOS tube (M₁) grid connect the 25th NMOS tube (MH1) and the 21st NMOS tube (M₂) grid simultaneously Second low side control signal (DRVL_FB) is connected, source electrode connects the source electrode of the 25th NMOS tube (MH1), drain electrode Connect the 21st NMOS tube (M₂) source electrode and the 24th NMOS tube (M₅) drain electrode；

21st NMOS tube (M₂) drain electrode connect the 23rd NMOS tube (M₄) drain electrode and export sampled signal (Vsense)；

22nd NMOS tube (M₃) grid connect the 23rd NMOS tube (M₄) and the 24th NMOS tube (M₅) grid simultaneously Connect the inversion signal of second low side control signal (DRVL_FB), drain electrode connection the first reference voltage (RefH), source Pole connects the 23rd NMOS tube (M₄) source electrode；

24th NMOS tube (M₅) source electrode ground connection；

16th PMOS tube (MP₁₆) grid connect the sampled signal (Vsense), source electrode connects the 17th PMOS tube (MP₁₇) source electrode and pass through 3rd resistor (R₃) the 5th PMOS tube (MP is connected afterwards₅) drain electrode, drain electrode connection the 8th NMOS tube (MN₈) source electrode and the 9th NMOS tube (MN₉) drain electrode；

17th PMOS tube (MP₁₇) grid connect the second reference voltage (RefL), drain electrode connection the tenth NMOS tube (MN₁₀) Source electrode and the 11st NMOS tube (MN₁₁) drain electrode；

5th PMOS tube (MP₅) source electrode connect the 6th PMOS tube (MP₆) drain electrode；

9th NMOS tube (MN₉) grid connect the 11st NMOS tube (MN₁₁) grid；

8th NMOS tube (MN₈) grid connect the tenth NMOS tube (MN₁₀) grid, drain electrode connection the 12nd NMOS tube (MN₁₂) grid and pass through the 4th resistance (R₄) the 7th PMOS tube (MP is connected afterwards₇) grid and drain electrode；

5th resistance (R₅) one end connect the 7th PMOS tube (MP₇) grid, the other end connect the tenth NMOS tube (MN₁₀) leakage Pole and the 13rd NMOS tube (MN₁₃) grid；

First NMOS tube (MN₁) grid connect the inversion signal of the first under-voltage signal (UVLO), drain electrode connection third NMOS tube (MN₃) grid, the second NMOS tube (MN₂) grid and drain electrode and offset signal (BIAS), source electrode connection second NMOS tube (MN₂), third NMOS tube (MN₃), the 5th NMOS tube (MN₅), the 7th NMOS tube (MN₇), the 9th NMOS tube (MN₉), 11 NMOS tube (MN₁₁), the 15th NMOS tube (MN₁₅), the 16th NMOS tube (MN₁₆) and the 17th NMOS tube (MN₁₇)；

Second PMOS tube (MP₂) grid connect third PMOS tube (MP₃), the 5th PMOS tube (MP₅) and the tenth PMOS tube (MP₁₀) Grid and third NMOS tube (MN₃) drain electrode and pass through first resistor (R₁) the second PMOS tube (MP is connected afterwards₂) drain electrode with And the first PMOS tube (MP₁), the 4th PMOS tube (MP₄), the 6th PMOS tube (MP₆) and the 9th PMOS tube (MP₉) grid, source Pole connects the first PMOS tube (MP₁) drain electrode；

4th PMOS tube (MP₄) drain electrode connect third PMOS tube (MP₃) source electrode, source electrode connect the first PMOS tube (MP₁)、 6th PMOS tube (MP₆), the 7th PMOS tube (MP₇), the 8th PMOS tube (MP₈), the 9th PMOS tube (MP₉), the 11st PMOS tube (MP₁₁) and the 14th PMOS tube (MP₁₄) source electrode and connect supply voltage (V_DD)；

4th NMOS tube (MN₄) grid connect the 6th NMOS tube (MN₆) and the 14th NMOS tube (MN₁₄) grid and third PMOS tube (MP₃) drain electrode and pass through second resistance (R₂) the 4th NMOS tube (MN is connected afterwards₄) drain electrode and the 5th NMOS tube (MN₅), the 7th NMOS tube (MN₇) and the 15th NMOS tube (MN₁₅) grid, source electrode connect the 5th NMOS tube (MN₅) leakage Pole；

14th NMOS tube (MN₁₄) source electrode connect the 15th NMOS tube (MN₁₅) drain electrode, drain electrode connection the 12nd NMOS tube (MN₁₂) and the 13rd NMOS tube (MN₁₃) source electrode；

6th resistance (R₆) one end connect the 8th PMOS tube (MP₈) grid and drain electrode and the 7th resistance (R₇) one end, The other end connects the 12nd NMOS tube (MN₁₂) drain electrode and the 13rd PMOS tube (MP₁₃) and the 18th NMOS tube (MN₁₈) Grid；

12nd PMOS tube (MP₁₂) grid connect the 7th resistance (R₇) the other end, the 13rd NMOS tube (MN₁₃) drain electrode and 19th NMOS tube (MN₁₉) grid, source electrode connect the 13rd PMOS tube (MP₁₃) source electrode and the tenth PMOS tube (MP₁₀) Drain electrode, the 16th NMOS tube (MN of drain electrode connection₁₆) grid and drain and pass through the 8th resistance (R₈) the 13rd is connected afterwards PMOS tube (MP₁₃) drain electrode and the 17th NMOS tube (MN₁₇) grid；

Tenth PMOS tube (MP₁₀) source electrode connect the 9th PMOS tube (MP₉) drain electrode；

14th PMOS tube (MP₁₄) grid connect the 18th NMOS tube (MN₁₈) drain electrode and pass through the 9th resistance (R₉) after connect Meet the 11st PMOS tube (MP₁₁) grid and drain electrode and the 19th NMOS tube (MN₁₉) drain electrode, drain electrode connection the 17th NMOS tube (MN₁₇) and the 15th PMOS tube (MP₁₅) drain electrode and the first phase inverter (INV1) input terminal；

6th NMOS tube (MN₆) drain electrode connect the 18th NMOS tube (MN₁₈) and the 19th NMOS tube (MN₁₉) source electrode, source Pole connects the 7th NMOS tube (MN₇) drain electrode；

15th PMOS tube (MP₁₅) grid connect the enable signal (EN), source electrode connects supply voltage (V_DD)；

The output end of first phase inverter (INV1) exports the zero passage detection signal (ZVS_out).