CN109039029A - A kind of bootstrap charge circuit circuit suitable for GaN power device gate drive circuit - Google Patents

A kind of bootstrap charge circuit circuit suitable for GaN power device gate drive circuit Download PDF

Info

Publication number
CN109039029A
CN109039029A CN201810925805.5A CN201810925805A CN109039029A CN 109039029 A CN109039029 A CN 109039029A CN 201810925805 A CN201810925805 A CN 201810925805A CN 109039029 A CN109039029 A CN 109039029A
Authority
CN
China
Prior art keywords
tube
nmos tube
signal
pmos tube
pmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201810925805.5A
Other languages
Chinese (zh)
Other versions
CN109039029B (en
Inventor
明鑫
胡黎
张宣
潘溯
张春奇
秦尧
张志文
王卓
张波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Electronic Science and Technology of China
Original Assignee
University of Electronic Science and Technology of China
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Electronic Science and Technology of China filed Critical University of Electronic Science and Technology of China
Priority to CN201810925805.5A priority Critical patent/CN109039029B/en
Publication of CN109039029A publication Critical patent/CN109039029A/en
Priority to US16/455,803 priority patent/US10673426B2/en
Application granted granted Critical
Publication of CN109039029B publication Critical patent/CN109039029B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)

Abstract

A kind of bootstrap charge circuit circuit suitable for GaN power device gate drive circuit, belongs to technical field of power management.Including bootstrap charge circuit module, low tension switch Logic control module, zero crossing detection module, high-voltage switch gear Logic control module and high voltage level displacement module, low tension switch Logic control module generates the low tension switch signal for controlling the first PMOS tube in bootstrap charge circuit module under the control of the first low side control signal, high-voltage switch gear Logic control module is in zero passage detection signal, the high-voltage switch gear signal for controlling the second PMOS tube in bootstrap charge circuit module is generated under the control of first low side control signal and the second under-voltage signal, zero passage detection signal is generated by zero crossing detection module according to the switching node signal that the second low side control signal samples gate drive circuit, high voltage level displacement module is for obtaining the high-voltage switch gear signal of suitable power source rail.The present invention can be avoided the phenomenon that negative pressure overshoots in bootstrap charge circuit, and solve the problems, such as reverse recovery loss and high frequency overcurrent performance degradation.

Description

A kind of bootstrap charge circuit circuit suitable for GaN power device gate drive circuit
Technical field
The invention belongs to technical field of power management, and in particular to a kind of bootstrapping suitable for power device gate drive circuit Charging circuit is particularly suitable for the GaN power device gate drive circuit of high-frequency high-power density.
Background technique
With the development of power electronic in recent years, half-bridge drive circuit just develops towards the direction of high power density, high frequency, This also puts forward new requirements the design of the selection of power tube and circuit.Traditional half-bridge drive circuit mainly chooses silicon power Pipe is as power stage, in contrast, due to GaN device for power switching (such as GaN high electron mobility transistor: GaN HEMT, with Lower elaboration is by taking GaN HEMT as an example) have it is high pressure resistant, without the good physical characteristic such as reverse recovery time, therefore use GaN function The half-bridge gate drive circuit of rate switching device possesses the good characteristics such as high speed, high power density.
If Fig. 1 is traditional bootstrap charge circuit circuit suitable for Si device for power switching, the circuit is in dead time under To bootstrap capacitor C on time of power tubebootIt charges, is supplied in upper on time of power tube to high side drive circuit Electricity.For half-bridge gate drive circuit, traditional bootstrap charge circuit circuit has been not suitable as the floating of GaN device for power switching Power rail generation circuit.First, bootstrap capacitor C is being given in the work of traditional bootstrap charging circuitbootWhen the state of charging, bootstrapping electricity Hold CbootTop crown current potential be approximately chip interior power vd D, bottom crown current potential is power switch node voltage SW, and GaN HEMT in the off case, when electric current flows to drain terminal from source, drain-source voltage VDSThe negative pressure of -2~-3V is had, therefore in half-bridge In gate drive circuit, when GaN HEMT makees lower power tube, since the pumping of external load carries in dead time, it is inclined that there are power stages Set voltage VSWThe case where being negative, and load current is higher, negative pressure condition is more serious, therefore will lead to bootstrap capacitor CbootIt is overshooted To chip interior power vd D is much higher than, so that GaN device for power switching occurs grid source and punctures (the grid source breakdown potential of GaN HEMT It presses smaller, it is desirable that VGS < 6V, optimal drive voltage are no more than 5.5V).Therefore, traditional bootstrap charging circuit should add control, It avoids in dead time to bootstrap capacitor CbootCharging.Second, since GaN HEMT is applied to the application ring of high pressure, high frequency more Border, circuit are very high to the load capacity requirement of bootstrap charge circuit circuit, and must be adapted for the high frequency electric power thus supplied of MHz, however piece Upper high voltage is restored power diode fastly and is difficult to realize in semiconductor processes, and fully integrated high voltage power diode is supplied in high frequency Performance can seriously be degenerated due to the influence of reverse recovery time and parasitic capacitance in electric situation, so that traditional bootstrap charging circuit exists High frequency, high power density application requirement under, bootstrap capacitor C cannot be filled in timebootOn the charge that is consumed, to influence floating Dynamic pressure difference of the power rail BST relative to switching node SW increases high side drive circuit degradation, upper power tube switching loss Greatly, or even triggering under-voltage protection leads to circuit cisco unity malfunction.
Summary of the invention
When floating power supply rail generation circuit for above-mentioned traditional bootstrap charging circuit as GaN device for power switching, by Lead to bootstrap capacitor C in the negative pressure in dead timebootIt overshoots to puncture GaN device for power switching, and in high-frequency high-power Bootstrap capacitor C cannot be filled under the application requirement of density in timebootOn be consumed charge the shortcomings that, the present invention proposes a kind of function The bootstrap charge circuit circuit of rate device gate drive circuit is particularly suitable for the GaN power device grid driving electricity of high-frequency high-power density Road, using the bootstrap diode in fully integrated injectron Q2 replacement traditional bootstrap charging circuit, switching tube Q2 is only in lower function Rate pipe is connected when opening, and solves bootstrap capacitor C caused by voltage is negative at power switching node SW in dead timebootOvershoot The problem of, and without Reverse recovery and reverse recovery loss, Simultaneous Switching pipe Q2 there will not be overcurrent performance degradation under high frequency situations The problem of.
The technical solution of the present invention is as follows:
A kind of bootstrap charge circuit circuit suitable for GaN power device gate drive circuit, the gate drive circuit include upper function Rate pipe and lower power tube, the bootstrap charge circuit circuit include bootstrap charge circuit module, low tension switch Logic control module, zero passage detection Module, high-voltage switch gear Logic control module and high voltage level displacement module；
The bootstrap charge circuit module includes the first PMOS tube Q1, the second PMOS tube Q2 and bootstrap capacitor Cboot, wherein first PMOS tube Q1 is low-voltage tube, and the second PMOS tube Q2 is high-voltage tube；
The source electrode of first PMOS tube Q1 connects supply voltage VDD, the drain electrode of the second PMOS tube Q2 of drain electrode connection, grid Connect low tension switch signal LVG；
The grid of second PMOS tube Q2 connects high-voltage switch gear signal HVG, source electrode connection bootstrap capacitor CbootTop crown simultaneously As floating power supply rail BST；
Bootstrap capacitor CbootBottom crown connect the switching node SW of the gate drive circuit；
The low tension switch Logic control module is enabled by the enable signal EN, in the first low side control signal DRVL_ The low tension switch signal LV is generated under the control of FB0G, the low tension switch signal LVGWith first low side control signal DRVL_FB0 reverse phase；
The enable signal EN and the first under-voltage same phase of signal UVLO, the first under-voltage signal UVLO are the power supply electricity Press VDDUnder-voltage signal；
The zero crossing detection module is enabled by the enable signal EN, in the control of the second low side control signal DRVL_FB The signal of the switching node SW of gate drive circuit described in down-sampling simultaneously generates zero passage detection signal ZVS_out, when the grid drive The signal of the switching node SW of circuit zero passage detection signal ZVS_out output low level when being high pressure, when the grid drive The signal of the switching node SW of circuit zero passage detection signal ZVS_out output high level when being 0；
The first low side control signal DRVL_FB0 and the second low side control signal DRVL_FB be and the lower power tube Gate drive signal with phase signal, and the second low side control signal DRVL_FB be first low side control signal DRVL_FB0 is obtained by delay；
The high-voltage switch gear Logic control module is enabled by the enable signal EN, for according to the zero passage detection signal ZVS_out and the first low side control signal DRVL_FB0 generation judges signal Ctr；
The high voltage level displacement module is used for the power rail by the judgement signal Ctr from supply voltage VDDIt is shifted to ground For signal signal at the switching node SW at the floating power supply rail BST；
The high-voltage switch gear Logic control module is according to by the high voltage level displacement module treated the judgement Signal Ctr and second is under-voltage, and signal UVLO_HS generates the high-voltage switch gear signal HVG, only as the described second under-voltage signal UVLO_ When HS, the first low side control signal DRVL_FB0 and zero passage detection signal ZVS_out are high level, the high-voltage switch gear signal HVGFor low level；Otherwise the high-voltage switch gear signal HVGFor high level；
Under-voltage signal of the second under-voltage signal UVLO_HS between the floating power supply rail BST and switching node SW.
Specifically, the zero crossing detection module includes the first phase inverter INV1, first resistor R1, second resistance R2, third electricity Hinder R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7, the 8th resistance R8, the 9th resistance R9, the tenth resistance R10, the first NMOS tube MN1, the second NMOS tube MN2, third NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8, the 9th NMOS tube MN9, the tenth NMOS tube MN10, the 11st NMOS tube MN11, the 12nd NMOS tube MN12, the 13rd NMOS tube MN13, the 14th NMOS tube MN14, the 15th NMOS tube MN15, the 16th NMOS tube MN16, the 17th NMOS tube MN17, the 18th NMOS tube MN18, the 19th NMOS tube MN19, the 20th NMOS tube M1, 21 NMOS tube M2, the 22nd NMOS tube M3, the 23rd NMOS tube M4, the 24th NMOS tube M5, the 25th NMOS Pipe MH1, the first PMOS tube MP1, the second PMOS tube MP2, third PMOS tube MP3, the 4th PMOS tube MP4, the 5th PMOS tube MP5, Six PMOS tube MP6, the 7th PMOS tube MP7, the 8th PMOS tube MP8, the 9th PMOS tube MP9, the tenth PMOS tube MP10, the 11st PMOS Pipe MP11, the 12nd PMOS tube MP12, the 13rd PMOS tube MP13, the 14th PMOS tube MP14, the 15th PMOS tube MP15, the tenth Six PMOS tube MP16With the 17th PMOS tube MP17, wherein the 25th NMOS tube MH1 is high-voltage tube；
Tenth resistance R10One end connects the switching node SW of the gate drive circuit, and the other end connects the 25th NMOS tube The drain electrode of MH1；
20th NMOS tube M1Grid connect the 25th NMOS tube MH1 and the 21st NMOS tube M2Grid and company Meet the second low side control signal DRVL_FB, source electrode connects the source electrode of the 25th NMOS tube MH1, drain electrode connection the 21 NMOS tube M2Source electrode and the 24th NMOS tube M5Drain electrode；
21st NMOS tube M2Drain electrode connect the 23rd NMOS tube M4Drain electrode and export sampled signal Vsense；
22nd NMOS tube M3Grid connect the 23rd NMOS tube M4With the 24th NMOS tube M5Grid and company Connect the inversion signal of the second low side control signal DRVL_FB, drain electrode the first reference voltage RefH of connection, source electrode connection 23rd NMOS tube M4Source electrode；
24th NMOS tube M5Source electrode ground connection；
16th PMOS tube MP16Grid connect the sampled signal Vsense, source electrode connects the 17th PMOS tube MP17Source electrode and pass through 3rd resistor R3The 5th PMOS tube MP is connected afterwards5Drain electrode, drain electrode connection the 8th NMOS tube MN8Source Pole and the 9th NMOS tube MN9Drain electrode；
17th PMOS tube MP17Grid connect the second reference voltage RefL, drain electrode connection the tenth NMOS tube MN10's Source electrode and the 11st NMOS tube MN11Drain electrode；
5th PMOS tube MP5Source electrode connect the 6th PMOS tube MP6Drain electrode；
9th NMOS tube MN9Grid connect the 11st NMOS tube MN11Grid；
8th NMOS tube MN8Grid connect the tenth NMOS tube MN10Grid, drain electrode connection the 12nd NMOS tube MN12 Grid and pass through the 4th resistance R4The 7th PMOS tube MP is connected afterwards7Grid and drain electrode；
5th resistance R5One end connect the 7th PMOS tube MP7Grid, the other end connect the tenth NMOS tube MN10Drain electrode With the 13rd NMOS tube MN13Grid；
First NMOS tube MN1Grid connect the inversion signal of the described first under-voltage signal UVLO, drain electrode connection third NMOS tube MN3Grid, the second NMOS tube MN2Grid and drain electrode and offset signal BIAS, source electrode connects the second NMOS tube MN2, third NMOS tube MN3, the 5th NMOS tube MN5, the 7th NMOS tube MN7, the 9th NMOS tube MN9, the 11st NMOS tube MN11, 15 NMOS tube MN15, the 16th NMOS tube MN16With the 17th NMOS tube MN17；
Second PMOS tube MP2Grid connect third PMOS tube MP3, the 5th PMOS tube MP5With the tenth PMOS tube MP10Grid Pole and third NMOS tube MN3Drain electrode and pass through first resistor R1After connect the second PMOS tube MP2Drain electrode and the first PMOS Pipe MP1, the 4th PMOS tube MP4, the 6th PMOS tube MP6With the 9th PMOS tube MP9Grid, source electrode connect the first PMOS tube MP1 Drain electrode；
4th PMOS tube MP4Drain electrode connect third PMOS tube MP3Source electrode, source electrode connect the first PMOS tube MP1, Six PMOS tube MP6, the 7th PMOS tube MP7, the 8th PMOS tube MP8, the 9th PMOS tube MP9, the 11st PMOS tube MP11With the 14th PMOS tube MP14Source electrode and connect supply voltage VDD；
4th NMOS tube MN4Grid connect the 6th NMOS tube MN6With the 14th NMOS tube MN14Grid and third PMOS tube MP3Drain electrode and pass through second resistance R2The 4th NMOS tube MN is connected afterwards4Drain electrode and the 5th NMOS tube MN5, the 7th NMOS tube MN7With the 15th NMOS tube MN15Grid, source electrode connect the 5th NMOS tube MN5Drain electrode；
14th NMOS tube MN14Source electrode connect the 15th NMOS tube MN15Drain electrode, drain electrode connection the 12nd NMOS Pipe MN12With the 13rd NMOS tube MN13Source electrode；
6th resistance R6One end connect the 8th PMOS tube MP8Grid and drain electrode and the 7th resistance R7One end, it is another One end connects the 12nd NMOS tube MN12Drain electrode and the 13rd PMOS tube MP13With the 18th NMOS tube MN18Grid；
12nd PMOS tube MP12Grid connect the 7th resistance R7The other end, the 13rd NMOS tube MN13Drain electrode and 19 NMOS tube MN19Grid, source electrode connect the 13rd PMOS tube MP13Source electrode and the tenth PMOS tube MP10Drain electrode, The 16th NMOS tube MN of drain electrode connection16Grid and drain and pass through the 8th resistance R8The 13rd PMOS tube MP is connected afterwards13Leakage Pole and the 17th NMOS tube MN17Grid；
Tenth PMOS tube MP10Source electrode connect the 9th PMOS tube MP9Drain electrode；
14th PMOS tube MP14Grid connect the 18th NMOS tube MN18Drain electrode and pass through the 9th resistance R9After connect 11st PMOS tube MP11Grid and drain electrode and the 19th NMOS tube MN19Drain electrode, drain electrode connection the 17th NMOS tube MN17With the 15th PMOS tube MP15Drain electrode and the first phase inverter INV1 input terminal；
6th NMOS tube MN6Drain electrode connect the 18th NMOS tube MN18With the 19th NMOS tube MN19Source electrode, source electrode Connect the 7th NMOS tube MN7Drain electrode；
15th PMOS tube MP15Grid connect the enable signal EN, source electrode connects supply voltage VDD；
The output end of first phase inverter INV1 exports the zero passage detection signal ZVS_out.
The course of work and working principle of the invention are as follows:
Supply voltage VDDWhen under-voltage, enable signal EN exports low level, low tension switch Logic control module, zero passage detection mould Block and high-voltage switch gear Logic control module do not work, low tension switch signal LVGWith high-voltage switch gear signal HVGFor high level shutdown the One PMOS tube Q1 and the second PMOS tube Q2, to turn off bootstrap charge circuit access not to bootstrap capacitor to CbootT charges；Power supply Voltage VDDNormally power on after, enable signal EN export high level enable low tension switch Logic control module, zero crossing detection module and High-voltage switch gear Logic control module.
As supply voltage VDDAfter the completion of powering on, enable signal EN exports high level, unlocks lower power tube, low tension switch first Logic control module generates low level low tension switch letter in the case where the first low side control signal DRVL_FB0 is high level Number LVGThe first PMOS tube Q1 is opened, bootstrapping access is decontroled, makes bootstrap capacitor CbootIt can slowly charge when lower power tube is opened.Again Whether under-voltage the second under-voltage signal UVLO_HS, floating power supply rail are obtained according between floating power supply rail BST and switching node SW The second under-voltage signal UVLO_HS is low level when under-voltage between BST and switching node SW, controls high-voltage switch gear Logic control module Generate the high-voltage switch gear signal HV of high levelGTurn off the second PMOS tube Q2.So in supply voltage VDDPower on completion and the electricity that floats When under-voltage between source rail BST and switching node SW, open the first PMOS tube Q1 and turn off the second PMOS tube Q2, with the second PMOS tube Q2 Body diode current-limiting charge mode give bootstrap capacitor CbootCharging.
As supply voltage VDDIt powers on after the completion of also being powered between completion and floating power supply rail BST and switching node SW, enables Signal EN and second is under-voltage, and signal UVLO_HS is high level, and low tension switch Logic control module is controlled according to the first downside to be believed Number DRVL_FB0 controls the first PMOS tube Q1 and is turned on and off, and high-voltage switch gear Logic control module is according to zero passage detection signal ZVS_ Out, the first low side control signal DRVL_FB0 and second is under-voltage, and the second PMOS tube Q2 of signal UVLO_HS control is turned on and off.
The low tension switch signal LV when the first low side control signal DRVL_FB0 is low levelGFor high level shutdown first Zero passage detection signal ZVS_out is made to export low level to generate high level for high pressure at PMOS tube Q1, switching node SW High-voltage switch gear signal HVGTurn off the second PMOS tube Q2.So in supply voltage VDDPower on completion, floating power supply rail BST and switch When also powering on completion between node SW, but negative pressure occurring at switching node SW, the first PMOS tube Q1 and the second PMOS tube Q2 is turned off, So that supply voltage VDD to bootstrap capacitor CbootBetween be back to back diode, blocked supply voltage VDD and bootstrap capacitor CbootBetween access, prevent when voltage enters negative pressure at switching node SW to bootstrap capacitor CbootIt charges.
The low tension switch signal LV when the first low side control signal DRVL_FB0 is high levelGFirst is opened for low level Voltage is reduced to 0 and makes zero passage detection signal ZVS_out output high level to generating low level at PMOS tube Q1, switching node SW High-voltage switch gear signal HVGOpen the second PMOS tube Q2.So in supply voltage VDDIt powers on completion, floating power supply rail BST and opens Also completion is powered between artis SW, and at switching node SW voltage be 0 when, the first PMOS tube Q1 and the second PMOS tube Q2 are opened It opens, bootstrap charge circuit circuit works normally, bootstrap capacitor CbootCharging rate is led by the first PMOS tube Q1's and the second PMOS tube Q2 Be powered the sum of resistance Rds_on and bootstrap capacitor CbootRC time constant determine.
The truth table of the corresponding circuit state of each logical signal is as follows:
The invention has the benefit that bootstrap charge circuit circuit provided by the invention, prevents negative pressure from asking using biswitch mode It inscribes and gives bootstrap capacitor C in a manner of high-voltage switch gearbootCharging gives bootstrap capacitor C when lower power tube is openedbootCharging, The phenomenon that avoiding negative pressure from overshooting；Second switch Q2 replaces bootstrap diode, is not in due to by electric at switching node SW The problem of pressing crosstalk to cause malfunction eliminates the problem of bootstrap diode reverse recovery loss is with high frequency overcurrent performance degradation, It is particularly suitable for the floating power supply rail power supply driven for high-frequency high-power density GaN grid.
Detailed description of the invention
Fig. 1 is the bootstrap charge circuit circuit topology figure that bootstrap diode is used in traditional half-bridge drive circuit.
Fig. 2 is that a kind of bootstrap charge circuit circuit suitable for GaN power device gate drive circuit proposed by the present invention is being implemented Topological diagram in example.
Fig. 3 is that a kind of circuit of zero crossing detection module in embodiment in the present invention realizes figure.
Fig. 4 is a kind of work of the bootstrap charge circuit circuit suitable for GaN power device gate drive circuit proposed by the present invention Control waveform diagram.
Fig. 5 is a kind of circuit realization structure chart that the second under-voltage signal UVLO_HS is obtained in the present invention.
Specific embodiment
The technical schemes of the invention are described in detail in the following with reference to the drawings and specific embodiments.
Bootstrap charge circuit circuit proposed by the present invention can be adapted for the grid driving electricity of GaN power device or Si power device Road, including bootstrap charge circuit module, low tension switch Logic control module, zero crossing detection module, high-voltage switch gear Logic control module and High voltage level displacement module, wherein bootstrap charge circuit module includes the first PMOS tube Q1, the second PMOS tube Q2 and bootstrap capacitor Cboot, The source electrode of first PMOS tube Q1 connects supply voltage VDD, the drain electrode of the second PMOS tube Q2 of drain electrode connection, grid connection low pressure Switching signal LVG；The grid of second PMOS tube Q2 connects high-voltage switch gear signal HVG, source electrode connection bootstrap capacitor CbootUpper pole Plate and as floating power supply rail BST；Bootstrap capacitor CbootBottom crown connection gate drive circuit switching node SW.First PMOS Pipe Q1 is low-voltage tube, for disconnecting supply voltage V when negative pressure occursDDTo bootstrap capacitor CbootThe access of power supply；2nd PMOS Pipe Q2 is high-voltage tube, and p-type high-voltage LDMOS pipe can be used in the second PMOS tube Q2, when using PLDMOS as high-voltage switch gear, due to Body diode needs reverse withstand voltage after LDMOS channel pinch off, therefore the source electrode of PLDMOS can only connect in floating power supply rail BST, therefore Its grid signal needs to refer to switching node SW, therefore the range of PLDMOS grid signal not will receive between BST-SW The dv/dt crosstalk of voltage Vsw causes the problem of malfunction at power switch node SW；And since bootstrap diode being replaced with only The high-voltage switch gear be connected when lowside power pipe is opened, the mode of this bootstrap charge circuit do not have in dead time by power switch Node SW voltage is negative the bootstrap capacitor C of introducingbootOvershooting problem also eliminates diode reverse recovery losses and high frequency overcurrent Performance degradation problem, the floating power supply rail power supply suitable for the driving of high frequency GaN grid.
Enable signal EN and the first under-voltage same phase of signal UVLO, the first under-voltage signal UVLO are supply voltage VDDUnder-voltage letter Number, supply voltage VDDFirst under-voltage signal UVLO exports low level, supply voltage V when under-voltageDDFirst under-voltage letter after the completion of powering on Number UVLO exports high level.As shown in Fig. 2, the first under-voltage signal UVLO can be established with benchmark enable signal Bias_ok phase with Enable signal EN is generated afterwards, so that supply voltage VDDEnable signal EN exports low level and turns off bootstrap charge circuit circuit, electricity when under-voltage Source voltage VDDEnable signal EN exports high level and opens bootstrap charge circuit circuit after the completion of powering on, and wherein benchmark establishes enable signal Bias_ok is the enable signal that system establishes each reference signal.
Low tension switch Logic control module is enabled by enable signal EN, is worked when enable signal EN is high level, and Low tension switch signal LV is generated under the control of first low side control signal DRVL_FB0G, low tension switch signal LVGWith the first downside Signal DRVL_FB0 reverse phase is controlled, gives a kind of circuit implementation of low tension switch Logic control module as shown in Figure 2.
Zero crossing detection module is enabled by enable signal EN, is worked when enable signal EN is high level, and in the second downside It controls the signal of the switching node SW of the control down-sampling gate drive circuit of signal DRVL_FB and generates zero passage detection signal ZVS_ Out, when power tube turns off instantly, the first low side control signal DRVL_FB0 and the second low side control signal DRVL_FB are low electricity Flat, the signal of the switching node SW of gate drive circuit is high pressure, and zero passage detection signal ZVS_out exports low level；Instantly power When pipe is opened, the first low side control signal DRVL_FB0 and the second low side control signal DRVL_FB are high level, gate drive circuit Switching node SW signal be 0, zero passage detection signal ZVS_out export high level.
A kind of circuit implementation of zero crossing detection module is given as shown in Figure 3, and zero crossing detection module detects electricity by SW Road and high-speed comparator are constituted, and wherein high-speed comparator is multilevel comparator, and the first order and the second level are low gain stage, third Grade use high-gain stage structure, the third level do the single-ended processing for turning both-end to make output stage become push-pull push-pull configuration, Improve response speed.
The maximum output voltage of comparator are as follows:
VOH=VDD (1)
Minimum output voltage are as follows:
VOL=VSS (2)
The small-signal gain of comparator are as follows:
Av(0)=gm,MP16gm,MN13·[R5||(ro,MN10+ro,MN11)]·[R7||ro,MN13]·[(gm,MP13R8+gm, MN19R9)](3)
Wherein, gmIndicate the mutual conductance of metal-oxide-semiconductor, roIndicate the output resistance of metal-oxide-semiconductor.The accuracy representing of comparator are as follows:
From expression formula (3) and (4) as can be seen that by rationally designing the 5th resistance R5, the 7th resistance R7, the 8th resistance R8 With the 9th resistance R9Value, the low-frequency gain of the high-speed comparator can be made relatively high, the precision of comparator is also higher.Than Transmission delay compared with device indicates are as follows:
SR is the Slew Rate of comparator.The comparator third level in the present embodiment using it is single-ended turn double-ended structure make output stage at The transmission delay of entire comparator is substantially reduced for push-pull push-pull configuration.
First NMOS tube MN1With the 15th PMOS tube MP15To power on enabled pipe, before chip is power-up to under-voltage unlock, Zero crossing detection module does not work.After chip works normally, the first NMOS tube MN1With the 15th PMOS tube MP15Shutdown.7th PMOS Pipe MP7, the 8th PMOS tube MP8, the 16th NMOS tube MN16And the 11st PMOS tube MP11For the input of circuits at different levels to be arranged Common mode electrical level.SW detection circuit is by high-voltage tube the 25th NMOS tube MH1 and the 20th NMOS tube M of low-voltage tube1, the 21st NMOS tube M2, the 22nd NMOS tube M3, the 23rd NMOS tube M4With the 24th NMOS tube M5Composition: the 25th NMOS Pipe MH1 can manage for LDMOS, and drain terminal meets voltage V at power switch node SWSWAnti- high pressure；20th NMOS tube M1With the 20th Four NMOS tube M5For negative pressure absorbing circuit, voltage V at power switching node SW is prevented in dead timeSWTo inside after into negative pressure Circuit impacts；21st NMOS tube M2, the 22nd NMOS tube M3With the 23rd NMOS tube M4For preventing the 20th One NMOS tube M2The signal of latch, sampled signal Vsense and the first reference voltage RefH influence each other at source electrode.
First low side control signal DRVL_FB0 and the second low side control signal DRVL_FB is the grid with lower power tube Driving signal is with the signal of phase, and the second low side control signal DRVL_FB is the first low side control signal DRVL_FB0 by prolonging When obtain, this is because voltage is leapt high from low pressure to high pressure at the switching node SW, zero crossing detection module still needs centainly Operating lag can just export comprising the logical message raised of voltage at switching node SW and at floating power supply rail BST, This section of delay will cause high-voltage tube the second PMOS tube Q2 when the voltage of switching node SW and floating power supply rail BST have been raised without Method turns off in time, leads to not that high pressure is blocked to be applied on the first PMOS tube of low-voltage tube Q1 in time, the first PMOS tube Q1 is caused to hit It wears and leaks electricity to supply voltage VDD.Therefore zero crossing detection module is controlled using the second low side control signal DRVL_FB, and second PMOS tube Q2 using first low side control signal DRVL_FB0 of the second low side control signal DRVL_FB after centainly postponing come Directly turn off.
High-voltage switch gear Logic control module is enabled by enable signal EN, is worked when enable signal EN is high level, and root Signal Ctr is judged according to zero passage detection signal ZVS_out and the first low side control signal DRVL_FB0 generation；Due to judging signal The power rail of Ctr is supply voltage VDDTo ground, thus need high voltage level displacement module will judge signal Ctr from supply voltage VDDLow side power rail transfer to ground is the high side floating power supply of signal signal at switching node SW at floating power supply rail BST Rail；Transfer generates height with the second under-voltage signal UVLO_HS of high side again for the signal after high side floating power supply rail jointly and presses off OFF signal HVG, due to under-voltage signal of the second under-voltage signal UVLO_HS between floating power supply rail BST and switching node SW, Power rail is also the high side power rail of signal signal at switching node SW at floating power supply rail BST.Height is given as shown in Figure 2 Compress switch a kind of circuit implementation of Logic control module, and the high voltage level displacement module in the present embodiment is also used to judge It is exported after signal Ctr reverse phase, only when the second under-voltage signal UVLO_HS, the first low side control signal DRVL_FB0 and zero passage detection When signal ZVS_out is high level, high-voltage switch gear signal HV is exportedGThe second PMOS tube Q2 is opened for low level；Otherwise it exports High-voltage switch gear signal HVGThe second PMOS tube Q2 is turned off for high level.
When bootstrap charge circuit circuit proposed by the present invention charges normal, the first PMOS tube Q1 and the second PMOS tube Q2 are opened, from Lift capacitor and CbootCharging rate by the sum of conducting resistance Rds_on of the first PMOS tube Q1 and the second PMOS tube Q2 and bootstrapping Capacitor CbootRC time constant determine；Bootstrap capacitor CbootWhen powering on, the first PMOS tube Q1 is opened in selection, the second PMOS tube Q2 shutdown, is limited with the diode pair charging current mode of the second PMOS tube of high-voltage tube Q2；When negative pressure occurs, the first PMOS Pipe Q1 and the second PMOS tube Q2 is disconnected, supply voltage VDD to bootstrap capacitor CbootBetween be back to back diode, block power supply electricity Press VDD and bootstrap capacitor CbootBetween access, prevent when voltage enters negative pressure at power switch node SW to bootstrap capacitor Cboot It charges.
Supply voltage VDDUnder-voltage signal as in chip enable highest priority control signal, should power in chip Abnormal i.e. supply voltage VDDAll modules of chip are turned off when occurring under-voltage by enable signal EN, to turn off power up and down Pipe disconnects bootstrapping supply access.As supply voltage VDDAfter under-voltage, lower power tube is unlocked first, is decontroled bootstrapping access, is made certainly Lift capacitor CbootIt can slowly charge when lower power tube is opened；When high side power rail pressure difference BST-SW is under-voltage, upper power tube is locked, Guarantee that bootstrap charge circuit is gone on smoothly；After high side power rail pressure difference is under-voltage, BST-SW stablizes in operating voltage, and solution is locked at this time Power tube.
Supply voltage VDDAfter the completion of powering on biasing, enable signal EN turns over high unlock the first PMOS tube Q1, enable signal EN When for the second under-voltage signal UVLO_HS being low, the unlatching of the first PMOS tube Q1 is controlled by the first low side control signal DRVL_FB0, First PMOS tube Q1 is opened when first low side control signal DRVL_FB0 is high, when the first low side control signal DRVL_FB0 is low First PMOS tube Q1 shutdown gives bootstrapping electricity when the first PMOS tube Q1 is opened with the second PMOS tube Q2 body diode current-limiting charge mode Hold CbootCharging.The second under-voltage signal UVLO_HS turns over the 2nd PMOS of high unlock after the completion of high side power rail pressure difference BST-SW is powered on Pipe Q2,
When enable signal EN and second is under-voltage signal UVLO_HS is high, the first PMOS tube Q1 and the second PMOS tube Q2 are equal Unlock, the unlatching of the first PMOS tube Q1 are equally controlled by the first low side control signal DRVL_FB0, the unlatching of the second PMOS tube Q2 It is controlled by the first low side control signal DRVL_FB0 and zero passage detection signal ZVS_out, as the second under-voltage signal UVLO_HS, The second PMOS tube Q2 is opened when one low side control signal DRVL_FB0 and zero passage detection signal ZVS_out is high level, at this time Bootstrap capacitor CbootCharging rate is (Rds_on-Q1+Rds_on-Q2) * Cboot determine RC time constant.
It is that the second under-voltage signal is driven according to the voltage between floating power supply rail BST and switching node SW as shown in Figure 5 A kind of circuit of UVLO_HS realizes structure chart, and second exported when under-voltage between floating power supply rail BST and switching node SW is under-voltage Signal UVLO_HS is low level, and the under-voltage signal of second exported when completion is powered between floating power supply rail BST and switching node SW UVLO_HS is high level.
In conclusion physical characteristic of the present invention according to traditional bootstrap scheme bootstrap diode, devises a kind of biswitch Bootstrap charge circuit scheme, supply voltage VDDBootstrap charge circuit circuit modules, bootstrap capacitor C are turned off when under-voltagebootIt does not charge； Supply voltage VDDAfter normally powering on, when BST-SW is under-voltage, opens the first PMOS tube Q1 and turn off the second PMOS tube Q2, filled using current limliting Power mode is bootstrap capacitor CbootCharging；Supply voltage VDDAfter normally being powered on BST-SW, if at switching node SW being high pressure, The first PMOS tube Q1 and the second PMOS tube Q2 are turned off, if voltage is approximately 0 at switching node SW, opens the first PMOS tube Q1 and the Two PMOS tube Q2, bootstrap charge circuit circuit work normally.Bootstrap charge circuit circuit of the invention gives bootstrapping electricity when lower power tube is opened Hold CbootThe phenomenon that charging, negative pressure avoided to overshoot；First PMOS tube Q1 is used to disconnect supply voltage V when negative pressure occursDDTo certainly Lift capacitor CbootThe access of power supply；Second switch Q2 replaces bootstrap diode, is not in due at by switching node SW Voltage crosstalk causes the problem of malfunction, eliminates asking for bootstrap diode reverse recovery loss and high frequency overcurrent performance degradation Topic.
It is worth noting that system control mode and the physical circuit design that the present invention uses can also be applied to Si power and opens In the driving circuit for closing device and other wide bandgap semiconductor switching devices (such as SiC device for power switching), specifically, being directed to The gate drive circuit of Si device for power switching, lower power tube body diode afterflow in dead time, voltage exists at switching node SW The negative pressure of -0.7V can be dropped in dead time, or even extremely in the case where heavy duty, Si device for power switching gate drive circuit It can be since the effect of itself body diode bulk resistor be so that SW is reduced to very negative negative pressure.The present disclosure applies equally to this kinds to answer With.
Those skilled in the art disclosed the technical disclosures can make various do not depart from originally according to the present invention Various other specific variations and combinations of essence are invented, these variations and combinations are still within the scope of the present invention.

Claims (2)

1. a kind of bootstrap charge circuit circuit suitable for GaN power device gate drive circuit, the gate drive circuit include upper power Pipe and lower power tube, which is characterized in that the bootstrap charge circuit circuit includes bootstrap charge circuit module, low tension switch logic control mould Block, zero crossing detection module, high-voltage switch gear Logic control module and high voltage level displacement module；
The bootstrap charge circuit module includes the first PMOS tube (Q1), the second PMOS tube (Q2) and bootstrap capacitor (Cboot), wherein first PMOS tube (Q1) is low-voltage tube, and the second PMOS tube (Q2) is high-voltage tube；
The source electrode of first PMOS tube (Q1) connects supply voltage (VDD), the drain electrode of drain electrode connection the second PMOS tube (Q2), grid Pole connects low tension switch signal (LVG)；
The grid of second PMOS tube (Q2) connects high-voltage switch gear signal (HVG), source electrode connects bootstrap capacitor (Cboot) top crown And as floating power supply rail (BST)；
Bootstrap capacitor (Cboot) bottom crown connect the switching node (SW) of the gate drive circuit；
The low tension switch Logic control module is enabled by the enable signal (EN), in the first low side control signal (DRVL_ FB0 the low tension switch signal (LV is generated under control)G), the low tension switch signal (LVG) controlled with first downside Signal (DRVL_FB0) reverse phase；
The enable signal (EN) and the first same phase of under-voltage signal (UVLO), the first under-voltage signal (UVLO) are the power supply Voltage (VDD) under-voltage signal；
The zero crossing detection module is enabled by the enable signal (EN), in the control of the second low side control signal (DRVL_FB) The signal of the switching node (SW) of gate drive circuit described in down-sampling simultaneously generates zero passage detection signal (ZVS_out), when the grid The signal of the switching node (SW) of driving circuit zero passage detection signal (ZVS_out) output low level when being high pressure, works as institute The signal for stating the switching node (SW) of gate drive circuit zero passage detection signal (ZVS_out) output high level when being 0；
First low side control signal (DRVL_FB0) and the second low side control signal (DRVL_FB) are and the lower power tube Gate drive signal with phase signal, and second low side control signal (DRVL_FB) be first downside control letter Number (DRVL_FB0) is obtained by delay；
The high-voltage switch gear Logic control module is enabled by the enable signal (EN), for according to the zero passage detection signal (ZVS_out) and the first low side control signal (DRVL_FB0) generation judges signal (Ctr)；
The high voltage level displacement module is used for the power rail by judgement signal (Ctr) from supply voltage (VDD) shifted to ground For signal signal at the switching node (SW) at the floating power supply rail (BST)；
The high-voltage switch gear Logic control module is according to by the high voltage level displacement module treated the judgement signal (Ctr) and the second under-voltage signal (UVLO_HS) generates the high-voltage switch gear signal (HVG), only when the described second under-voltage signal (UVLO_HS), it is described when the first low side control signal (DRVL_FB0) and zero passage detection signal (ZVS_out) are high level High-voltage switch gear signal (HVG) it is low level；Otherwise the high-voltage switch gear signal (HVG) it is high level；
Under-voltage letter of the second under-voltage signal (UVLO_HS) between the floating power supply rail (BST) and switching node (SW) Number.
2. the bootstrap charge circuit circuit according to claim 1 suitable for GaN power device gate drive circuit, feature exist In the zero crossing detection module includes the first phase inverter (INV1), first resistor (R1), second resistance (R2), 3rd resistor (R3), the 4th resistance (R4), the 5th resistance (R5), the 6th resistance (R6), the 7th resistance (R7), the 8th resistance (R8), the 9th resistance (R9), the tenth resistance (R10), the first NMOS tube (MN1), the second NMOS tube (MN2), third NMOS tube (MN3), the 4th NMOS tube (MN4), the 5th NMOS tube (MN5), the 6th NMOS tube (MN6), the 7th NMOS tube (MN7), the 8th NMOS tube (MN8), the 9th NMOS Manage (MN9), the tenth NMOS tube (MN10), the 11st NMOS tube (MN11), the 12nd NMOS tube (MN12), the 13rd NMOS tube (MN13), the 14th NMOS tube (MN14), the 15th NMOS tube (MN15), the 16th NMOS tube (MN16), the 17th NMOS tube (MN17), the 18th NMOS tube (MN18), the 19th NMOS tube (MN19), the 20th NMOS tube (M1), the 21st NMOS tube (M2), the 22nd NMOS tube (M3), the 23rd NMOS tube (M4), the 24th NMOS tube (M5), the 25th NMOS tube (MH1), the first PMOS tube (MP1), the second PMOS tube (MP2), third PMOS tube (MP3), the 4th PMOS tube (MP4), the 5th PMOS Manage (MP5), the 6th PMOS tube (MP6), the 7th PMOS tube (MP7), the 8th PMOS tube (MP8), the 9th PMOS tube (MP9), the tenth PMOS tube (MP10), the 11st PMOS tube (MP11), the 12nd PMOS tube (MP12), the 13rd PMOS tube (MP13), the 14th PMOS Manage (MP14), the 15th PMOS tube (MP15), the 16th PMOS tube (MP16) and the 17th PMOS tube (MP17), wherein the 25th NMOS tube (MH1) is high-voltage tube；
Tenth resistance (R10) one end connects the switching node (SW) of the gate drive circuit, the other end connects the 25th NMOS tube (MH1) drain electrode；
20th NMOS tube (M1) grid connect the 25th NMOS tube (MH1) and the 21st NMOS tube (M2) grid simultaneously Second low side control signal (DRVL_FB) is connected, source electrode connects the source electrode of the 25th NMOS tube (MH1), drain electrode Connect the 21st NMOS tube (M2) source electrode and the 24th NMOS tube (M5) drain electrode；
21st NMOS tube (M2) drain electrode connect the 23rd NMOS tube (M4) drain electrode and export sampled signal (Vsense)；
22nd NMOS tube (M3) grid connect the 23rd NMOS tube (M4) and the 24th NMOS tube (M5) grid simultaneously Connect the inversion signal of second low side control signal (DRVL_FB), drain electrode connection the first reference voltage (RefH), source Pole connects the 23rd NMOS tube (M4) source electrode；
24th NMOS tube (M5) source electrode ground connection；
16th PMOS tube (MP16) grid connect the sampled signal (Vsense), source electrode connects the 17th PMOS tube (MP17) source electrode and pass through 3rd resistor (R3) the 5th PMOS tube (MP is connected afterwards5) drain electrode, drain electrode connection the 8th NMOS tube (MN8) source electrode and the 9th NMOS tube (MN9) drain electrode；
17th PMOS tube (MP17) grid connect the second reference voltage (RefL), drain electrode connection the tenth NMOS tube (MN10) Source electrode and the 11st NMOS tube (MN11) drain electrode；
5th PMOS tube (MP5) source electrode connect the 6th PMOS tube (MP6) drain electrode；
9th NMOS tube (MN9) grid connect the 11st NMOS tube (MN11) grid；
8th NMOS tube (MN8) grid connect the tenth NMOS tube (MN10) grid, drain electrode connection the 12nd NMOS tube (MN12) grid and pass through the 4th resistance (R4) the 7th PMOS tube (MP is connected afterwards7) grid and drain electrode；
5th resistance (R5) one end connect the 7th PMOS tube (MP7) grid, the other end connect the tenth NMOS tube (MN10) leakage Pole and the 13rd NMOS tube (MN13) grid；
First NMOS tube (MN1) grid connect the inversion signal of the first under-voltage signal (UVLO), drain electrode connection third NMOS tube (MN3) grid, the second NMOS tube (MN2) grid and drain electrode and offset signal (BIAS), source electrode connection second NMOS tube (MN2), third NMOS tube (MN3), the 5th NMOS tube (MN5), the 7th NMOS tube (MN7), the 9th NMOS tube (MN9), 11 NMOS tube (MN11), the 15th NMOS tube (MN15), the 16th NMOS tube (MN16) and the 17th NMOS tube (MN17)；
Second PMOS tube (MP2) grid connect third PMOS tube (MP3), the 5th PMOS tube (MP5) and the tenth PMOS tube (MP10) Grid and third NMOS tube (MN3) drain electrode and pass through first resistor (R1) the second PMOS tube (MP is connected afterwards2) drain electrode with And the first PMOS tube (MP1), the 4th PMOS tube (MP4), the 6th PMOS tube (MP6) and the 9th PMOS tube (MP9) grid, source Pole connects the first PMOS tube (MP1) drain electrode；
4th PMOS tube (MP4) drain electrode connect third PMOS tube (MP3) source electrode, source electrode connect the first PMOS tube (MP1)、 6th PMOS tube (MP6), the 7th PMOS tube (MP7), the 8th PMOS tube (MP8), the 9th PMOS tube (MP9), the 11st PMOS tube (MP11) and the 14th PMOS tube (MP14) source electrode and connect supply voltage (VDD)；
4th NMOS tube (MN4) grid connect the 6th NMOS tube (MN6) and the 14th NMOS tube (MN14) grid and third PMOS tube (MP3) drain electrode and pass through second resistance (R2) the 4th NMOS tube (MN is connected afterwards4) drain electrode and the 5th NMOS tube (MN5), the 7th NMOS tube (MN7) and the 15th NMOS tube (MN15) grid, source electrode connect the 5th NMOS tube (MN5) leakage Pole；
14th NMOS tube (MN14) source electrode connect the 15th NMOS tube (MN15) drain electrode, drain electrode connection the 12nd NMOS tube (MN12) and the 13rd NMOS tube (MN13) source electrode；
6th resistance (R6) one end connect the 8th PMOS tube (MP8) grid and drain electrode and the 7th resistance (R7) one end, The other end connects the 12nd NMOS tube (MN12) drain electrode and the 13rd PMOS tube (MP13) and the 18th NMOS tube (MN18) Grid；
12nd PMOS tube (MP12) grid connect the 7th resistance (R7) the other end, the 13rd NMOS tube (MN13) drain electrode and 19th NMOS tube (MN19) grid, source electrode connect the 13rd PMOS tube (MP13) source electrode and the tenth PMOS tube (MP10) Drain electrode, the 16th NMOS tube (MN of drain electrode connection16) grid and drain and pass through the 8th resistance (R8) the 13rd is connected afterwards PMOS tube (MP13) drain electrode and the 17th NMOS tube (MN17) grid；
Tenth PMOS tube (MP10) source electrode connect the 9th PMOS tube (MP9) drain electrode；
14th PMOS tube (MP14) grid connect the 18th NMOS tube (MN18) drain electrode and pass through the 9th resistance (R9) after connect Meet the 11st PMOS tube (MP11) grid and drain electrode and the 19th NMOS tube (MN19) drain electrode, drain electrode connection the 17th NMOS tube (MN17) and the 15th PMOS tube (MP15) drain electrode and the first phase inverter (INV1) input terminal；
6th NMOS tube (MN6) drain electrode connect the 18th NMOS tube (MN18) and the 19th NMOS tube (MN19) source electrode, source Pole connects the 7th NMOS tube (MN7) drain electrode；
15th PMOS tube (MP15) grid connect the enable signal (EN), source electrode connects supply voltage (VDD)；
The output end of first phase inverter (INV1) exports the zero passage detection signal (ZVS_out).
CN201810925805.5A 2018-08-08 2018-08-15 Bootstrap charging circuit suitable for GaN power device gate drive circuit Expired - Fee Related CN109039029B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201810925805.5A CN109039029B (en) 2018-08-15 2018-08-15 Bootstrap charging circuit suitable for GaN power device gate drive circuit
US16/455,803 US10673426B2 (en) 2018-08-08 2019-06-28 Switch bootstrap charging circuit suitable for gate drive circuit of GaN power device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810925805.5A CN109039029B (en) 2018-08-15 2018-08-15 Bootstrap charging circuit suitable for GaN power device gate drive circuit

Publications (2)

Publication Number Publication Date
CN109039029A true CN109039029A (en) 2018-12-18
CN109039029B CN109039029B (en) 2020-02-04

Family

ID=64631202

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810925805.5A Expired - Fee Related CN109039029B (en) 2018-08-08 2018-08-15 Bootstrap charging circuit suitable for GaN power device gate drive circuit

Country Status (1)

Country Link
CN (1) CN109039029B (en)

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109327197A (en) * 2018-11-28 2019-02-12 电子科技大学 A kind of control circuit of depletion type GaN-HEMT power amplifier
CN109861503A (en) * 2019-02-28 2019-06-07 深圳市泰德半导体有限公司 Driving circuit for power device
CN109951178A (en) * 2019-04-03 2019-06-28 电子科技大学 A kind of system protection method of GaN gate drive circuit
CN110176858A (en) * 2018-02-21 2019-08-27 纳维达斯半导体公司 Utilize the circuit for power conversion of one or more semiconductor devices based on GaN
CN110208673A (en) * 2019-06-12 2019-09-06 电子科技大学 A kind of power tube gate source voltage undervoltage detection circuit suitable for DC-DC converter
CN111293862A (en) * 2020-02-27 2020-06-16 电子科技大学 High-reliability self-adaptive dead time grid driving circuit
CN111654178A (en) * 2020-06-24 2020-09-11 华源智信半导体(深圳)有限公司 GaN power tube driving circuit, driving method and corresponding electronic device
CN111799992A (en) * 2019-04-04 2020-10-20 纳维达斯半导体公司 GaN half-bridge circuit and GaN bootstrap power supply voltage generator circuit
CN112290782A (en) * 2020-12-21 2021-01-29 上海芯龙半导体技术股份有限公司南京分公司 Drive signal control circuit and switching power supply chip
CN113193732A (en) * 2021-04-27 2021-07-30 成都稳海半导体有限公司 Self-adaptive charging bootstrap power supply
CN113241933A (en) * 2021-05-24 2021-08-10 电子科技大学 Dead time control circuit suitable for GaN half-bridge grid driving system
CN113258764A (en) * 2021-06-22 2021-08-13 浙江大学 High-voltage driving circuit and power module
CN113541453A (en) * 2021-07-05 2021-10-22 无锡安趋电子有限公司 High-side bootstrap power supply control system in GaN power tube half-bridge drive
CN113595389A (en) * 2020-04-30 2021-11-02 圣邦微电子（北京）股份有限公司 High-side tube control signal potential translation improved circuit for preventing electric penetration on Buck circuit
CN113849025A (en) * 2021-09-27 2021-12-28 电子科技大学 Power rail generating circuit
CN114552976A (en) * 2022-03-02 2022-05-27 电子科技大学 full-GaN gate drive circuit with high conversion rate
CN115955085A (en) * 2023-03-10 2023-04-11 晶艺半导体有限公司 Drive circuit, drive method thereof, control circuit and power supply chip
CN116819166A (en) * 2023-08-31 2023-09-29 苏州贝克微电子股份有限公司 High-voltage end undervoltage detection circuit

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5969964A (en) * 1997-04-23 1999-10-19 International Rectifier Corporation Resistor in series with bootstrap diode for monolithic gate driver device
CN103915990A (en) * 2014-04-18 2014-07-09 电子科技大学 Drive circuit for GaN power devices
CN104170254A (en) * 2012-03-16 2014-11-26 德克萨斯仪器股份有限公司 System and apparatus for driver circuit for protection of gates of GaN FETs
JP2015208111A (en) * 2014-04-21 2015-11-19 ニチコン株式会社 gate drive circuit
CN107359787A (en) * 2017-09-08 2017-11-17 电子科技大学 A kind of gate driving circuit of adaptive dead zone time

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5969964A (en) * 1997-04-23 1999-10-19 International Rectifier Corporation Resistor in series with bootstrap diode for monolithic gate driver device
CN104170254A (en) * 2012-03-16 2014-11-26 德克萨斯仪器股份有限公司 System and apparatus for driver circuit for protection of gates of GaN FETs
CN103915990A (en) * 2014-04-18 2014-07-09 电子科技大学 Drive circuit for GaN power devices
JP2015208111A (en) * 2014-04-21 2015-11-19 ニチコン株式会社 gate drive circuit
CN107359787A (en) * 2017-09-08 2017-11-17 电子科技大学 A kind of gate driving circuit of adaptive dead zone time

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
张弘等: "GaN功率开关器件驱动技术的研究与发展", 《电力电子技术》 *

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110176858A (en) * 2018-02-21 2019-08-27 纳维达斯半导体公司 Utilize the circuit for power conversion of one or more semiconductor devices based on GaN
CN109327197B (en) * 2018-11-28 2021-08-17 电子科技大学 Control circuit of depletion type GaN-HEMT power amplifier
CN109327197A (en) * 2018-11-28 2019-02-12 电子科技大学 A kind of control circuit of depletion type GaN-HEMT power amplifier
CN109861503A (en) * 2019-02-28 2019-06-07 深圳市泰德半导体有限公司 Driving circuit for power device
CN109861503B (en) * 2019-02-28 2023-11-03 深圳市泰德半导体有限公司 Driving circuit for power device
CN109951178A (en) * 2019-04-03 2019-06-28 电子科技大学 A kind of system protection method of GaN gate drive circuit
CN111799992A (en) * 2019-04-04 2020-10-20 纳维达斯半导体公司 GaN half-bridge circuit and GaN bootstrap power supply voltage generator circuit
CN110208673A (en) * 2019-06-12 2019-09-06 电子科技大学 A kind of power tube gate source voltage undervoltage detection circuit suitable for DC-DC converter
CN110208673B (en) * 2019-06-12 2021-04-23 电子科技大学 Power tube grid source voltage under-voltage detection circuit suitable for DC-DC converter
CN111293862B (en) * 2020-02-27 2021-07-02 电子科技大学 High-reliability self-adaptive dead time grid driving circuit
CN111293862A (en) * 2020-02-27 2020-06-16 电子科技大学 High-reliability self-adaptive dead time grid driving circuit
CN113595389A (en) * 2020-04-30 2021-11-02 圣邦微电子（北京）股份有限公司 High-side tube control signal potential translation improved circuit for preventing electric penetration on Buck circuit
CN113595389B (en) * 2020-04-30 2023-04-11 圣邦微电子（北京）股份有限公司 High-side tube control signal potential translation improved circuit for preventing electric penetration on Buck circuit
CN111654178A (en) * 2020-06-24 2020-09-11 华源智信半导体(深圳)有限公司 GaN power tube driving circuit, driving method and corresponding electronic device
CN112290782A (en) * 2020-12-21 2021-01-29 上海芯龙半导体技术股份有限公司南京分公司 Drive signal control circuit and switching power supply chip
CN113193732A (en) * 2021-04-27 2021-07-30 成都稳海半导体有限公司 Self-adaptive charging bootstrap power supply
CN113241933A (en) * 2021-05-24 2021-08-10 电子科技大学 Dead time control circuit suitable for GaN half-bridge grid driving system
CN113258764A (en) * 2021-06-22 2021-08-13 浙江大学 High-voltage driving circuit and power module
CN113541453B (en) * 2021-07-05 2023-02-03 无锡安趋电子有限公司 High-side bootstrap power supply control system in GaN power tube half-bridge drive
CN113541453A (en) * 2021-07-05 2021-10-22 无锡安趋电子有限公司 High-side bootstrap power supply control system in GaN power tube half-bridge drive
CN113849025A (en) * 2021-09-27 2021-12-28 电子科技大学 Power rail generating circuit
CN113849025B (en) * 2021-09-27 2022-10-04 电子科技大学 Power rail generating circuit
CN114552976A (en) * 2022-03-02 2022-05-27 电子科技大学 full-GaN gate drive circuit with high conversion rate
CN115955085A (en) * 2023-03-10 2023-04-11 晶艺半导体有限公司 Drive circuit, drive method thereof, control circuit and power supply chip
CN116819166A (en) * 2023-08-31 2023-09-29 苏州贝克微电子股份有限公司 High-voltage end undervoltage detection circuit
CN116819166B (en) * 2023-08-31 2023-11-03 苏州贝克微电子股份有限公司 High-voltage end undervoltage detection circuit

Also Published As

Publication number Publication date
CN109039029B (en) 2020-02-04

Similar Documents

Publication Publication Date Title
CN109039029A (en) A kind of bootstrap charge circuit circuit suitable for GaN power device gate drive circuit
US10673426B2 (en) Switch bootstrap charging circuit suitable for gate drive circuit of GaN power device
CN110739950B (en) Power transistor control signal gating
CN107005163B (en) GaN circuit drivers for GaN circuit loads
CN111799992B (en) GaN half-bridge circuit and GaN bootstrap power supply voltage generator circuit
CN113037273B (en) Capacitive coupling type level shifter
CN109004820B (en) Switch bootstrap charging circuit suitable for high-speed grid driving of GaN power device
CN111193395A (en) Resonant converter control based on zero current detection
US7755395B2 (en) Inverter circuit
CN113422509B (en) Power conversion circuit utilizing one or more GaN-based semiconductor devices
US6940317B2 (en) Level-shifter circuit properly operable with low voltage input
CN111049100B (en) Bootstrap circuit with clamping function
CN116742920B (en) NMOS power switch tube driving circuit and control method thereof
CN117938135B (en) Direct drive circuit structure based on depletion type power field effect transistor device
Zheng et al. A High-Speed Level Shifter with dV s/dt Noise Immunity Enhancement Structure for 200V Monolithic GaN Power IC
CN118041327A (en) Integrated bootstrap switching circuit suitable for high-voltage GaN half-bridge gate driving chip
EP0068892B1 (en) Inverter circuit
CN115167598A (en) Power supply voltage selection circuit
CN114552968A (en) Self-adaptive bootstrap charging circuit suitable for GaN driving chip
US8928368B2 (en) Gate driving circuit
Zhang et al. A 600V Half-Bridge Power Stage Fully Integrated with 25V Gate-Drivers in SiC CMOS Technology
CN110545047A (en) Small-power on-chip rectifier bridge circuit
TWI853557B (en) Drive device
Hung et al. A High Common-Mode Transient Immunity GaN-on-SOI Gate Driver With Quad-Drive Control Technique for High dV/dt 1700-V SiC Power Switch
TWI846201B (en) Control device for power conversion apparatus

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20200204

CF01 Termination of patent right due to non-payment of annual fee