CN108155903B - High-speed high-voltage level conversion circuit applied to GaN grid drive - Google Patents

High-speed high-voltage level conversion circuit applied to GaN grid drive Download PDF

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CN108155903B
CN108155903B CN201711175450.4A CN201711175450A CN108155903B CN 108155903 B CN108155903 B CN 108155903B CN 201711175450 A CN201711175450 A CN 201711175450A CN 108155903 B CN108155903 B CN 108155903B
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pmos transistor
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nmos transistor
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CN108155903A (en
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郭建平
张弘
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Tuoer Microelectronics Co ltd
Xi'an Tuoer Microelectronics Co ltd
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Sun Yat Sen University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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    • H03K19/017509—Interface arrangements

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Abstract

The invention discloses a high-speed high-voltage level conversion circuit applied to GaN grid drive, which comprises: the input circuit, the first PMOS transistor, the level conversion circuit and the shaping circuit; the first end of the input circuit is connected to the first end of the level conversion circuit at a first node, the second end of the input circuit is connected to the drain electrode of the first PMOS transistor at a second node, the grid electrode of the first PMOS transistor is connected to the first power line, the source electrode of the first PMOS transistor is connected to the second end of the level conversion circuit at a third node, the level conversion circuit is connected to the second power line, the second end of the level conversion circuit is connected to the input end of the shaping circuit at the third node, the shaping circuit is connected to the first power line and the second power line, the output end of the shaping circuit is connected to the first end of the power device at a fourth node, and the power device is connected to the.

Description

High-speed high-voltage level conversion circuit applied to GaN grid drive
Technical Field
The invention belongs to the field of integrated circuit design, and particularly relates to a high-speed high-voltage level conversion circuit applied to GaN gate drive.
Background
The traditional power electronic power device based on silicon material has gradually approached its theoretical limit, and it is difficult to meet the development requirements of high frequency and high power density of power electronic technology. Compared with the traditional Si device, the GaN device shows the advantages of the GaN device in on-resistance and grid charge, and can enable the power converter to achieve smaller volume, higher frequency and higher efficiency, thereby having wide application prospects in the fields of automobiles, communication, industry and the like. The increase of the switching frequency not only can effectively reduce the sizes of a capacitor, an inductor and a transformer in a system circuit, but also can inhibit interference, reduce ripples and improve the unit gain bandwidth of a power supply system so as to improve the dynamic response performance of the power supply system. And the high-speed grid driving circuit is used for driving the GaN power device, so that the whole power converter achieves high efficiency, the circuit area is reduced, and the cost is saved.
Fig. 1 shows a block diagram of a typical GaN half-bridge driving circuit according to the prior art. As shown in fig. 1, a typical GaN half-bridge driving circuit is divided into two high-side and low-side channels, and two low-voltage input channels are connected in a bootstrap boosting manner. During the conduction period of the low-side power GaN device, the switch node (SW) is pulled down to the ground, and VDD charges the bootstrap capacitor through the bootstrap diode so that the voltage difference between the two ends of the bootstrap capacitor approaches VDD. When the lower end tube is closed, the high end input signal turns on the high end tube, and the voltage of the switch node rises to VINI.e. VSW rises to VIN. Since the voltage across the bootstrap capacitor is constant,the bootstrap voltage rail HB is bootstrapped to VSW + VDD. The high-side circuit always keeps VHB-VSW ≈ VDD. When HB is bootstrapped by the bootstrap capacitor, the cathode voltage of the bootstrap diode is high and higher than the anode voltage VDD, so that the bootstrap diode is reversely biased off.
Due to the bootstrap boosting feature of GaN driving, in order to control the on and off of the high-side GaN power device, a level shifter is required to convert a low-voltage input control signal into a high-voltage floating level signal. The level conversion circuit is a key part in the grid drive circuit, converts an input low-voltage control signal into a high-voltage floating control signal, and controls the on and off of the power device after passing through the cascade buffer.
Most of the level conversion circuits are applied in low voltage circuits and are used for conversion, for example, a periodic square wave signal with a low voltage input signal of 1.2V and a low voltage input signal of 0V is converted into a periodic square wave signal with an output signal of 1.8V and a low voltage input signal of 0V. Such level shifting circuit types are numerous, but most are not suitable for high voltage floating level shifting circuits, and the transmission delay is large. The high-voltage floating level conversion circuit integrally 'transfers' the low-voltage input signal to the high-voltage rail instead of converting the low-voltage input signal into a periodic square wave signal with the high and low levels of 5V and 0V respectively, for example, the periodic square wave signal with the high and low levels of 35V and 30V respectively is converted into the periodic square wave signal with the high and low levels of the output signal. "floating" means that the low potential of the level shift output is not fixed ground but a high voltage potential that varies as the external switch node floats. The high-voltage floating level conversion circuit applied to half-bridge driving is relatively few, and transmission delay is large, so that the application of the driving circuit is limited, and particularly when an external power device adopts GaN, the power converter is often applied to a high-frequency switching frequency in order to exert the advantage of high-speed GaN, so that the switching cycle time is short, extremely small level conversion time is needed, and otherwise, switching logic errors can be caused. And the smaller the level conversion time is, the higher the switching frequency of the power converter can be, so that the size, the area and the cost of peripheral passive devices are reduced.
The traditional transistor gate driving circuit is mainly aimed at a Si MOS power tube or an IGBT, and the frequency environment of the power device is usually not high (hundreds of kHz switching frequency), so that the transmission delay is large. When a GaN power device is selected, the GaN power device is generally used at a high-frequency switching frequency (above MHz), and particularly after the switching frequency reaches 10MHz, a large delay (tens of nanoseconds) of a conventional gate drive accounts for an excessively large proportion of a switching period, even logic errors are caused, and the switching frequency is limited from increasing.
Reducing the propagation delay to within a few nanoseconds is a prerequisite for gate drives that can operate at high frequency switching frequencies. Since the high side path has one more level shifter than the low side path, the delay of the high side path is usually larger than that of the low side path, and a delay matching circuit needs to be added to the low side path to equalize the delays of the high side path and the low side path. In other words, the delay of the driving circuit is determined by the delay of the high-side path, which depends on the delay of the level shifter, so reducing the delay of the level shifter is the first challenge to solve the high frequency application of the GaN driving circuit. The conventional high voltage floating level shifter has two kinds of cross-coupled structure and current mirror structure, as shown in fig. 2 and 4, respectively.
Fig. 2 shows a cross-coupled configuration high voltage level shifting circuit according to the prior art. As shown in FIG. 2, M1 and M2 are low voltage PMOS in cross-coupled structure, and Mdep1And Mdep2The high-voltage DEPMOS is used for bearing high voltage in the circuit and also plays a role in isolating the high-voltage circuit from the low-voltage circuit. And VSSHTo Mdep1And Mdep2The grid of (2) is used as the low potential of the high-voltage output signal, corresponding to VDDHIs a high potential of the high voltage output. Mid1And Mid2Is a high pressure input pipe. When V isINWhen the potential changes from low to high, Mid1On, Mid2Off, node VdIs pulled down, and then the grid of the M2 is pulled down, so that the M2 is conducted, and the V is pulled upOUTDue to VOUTThe rise turns off M1, i.e., for M2 gate, the pull-up capability is reduced, helping M2 pull V highOUTAnd (6) carrying out the process. For VOUTIn other words, M is due toid2Is turned off, thus VOUTIs turned off, contributing to VOUTPull up to this point VOUTIs at a high potential. When V isINWhen switching from high to low, Mid1Off, Mid2Conduction, VOUTPulled down to low, M1 turns on the gate voltage of pull-up M2, causing M2 to turn off, and for VOUTWith respect to the node, the pull-up current reduction contributes to VOUTProcess of being pulled down, to this point VOUTIs pulled down to a low potential. Fig. 3 shows a waveform schematic diagram of a cross-coupled high voltage level shifter according to the prior art. As shown in FIG. 3, the conventional cross-coupled high voltage level shifter has a node V with high impedancedSo that a large saturation current (I)d) Cannot be maintained for a long time. While reducing IdIn turn, will slow the "latching" of M1/M2, resulting in VOUTThe transmission delay is large during the level conversion process.
Fig. 4 shows a current mirror structured high voltage level shifter circuit according to the prior art. As shown in FIG. 4, M1 and M2 form a current mirror structure for low voltage PMOS, Mid1And Mid2Is a high-pressure input pipe, MdepThe DEPMOS circuit bears high voltage in the circuit and also plays a role in isolating the high-voltage circuit from the low-voltage circuit. And VSSHTo MdepThe grid of (2) is used as the low potential of the high-voltage output signal, corresponding to VDDHIs a high potential of the high voltage output. When V isINWhen the low point is converted into the high level, Mid1On, Mid2Off, node VdIs pulled down due to Mid1And M1 are both turned on, so that the left branch has larger saturation current IdIs mirrored to the right branch as VOUTDue to Mid2Turn off so that the pull-down current is zero, VOUTIs quickly pulled up to a high potential. When V isINWhen switching from high to low, Mid1Off, Mid2On, so that the left branch is off and has no current, so that the current mirror has no mirror current, VOUTIs pulled down to a low potential without a pull-up current. The traditional current mirror structure high-voltage level converter has small transmission delay but large power consumption. FIG. 5 shows a diagram according to the prior artThe waveform of the high-voltage level conversion circuit with the current mirror structure is shown schematically. As shown in FIG. 5, the level shifter of the current mirror structure has a low impedance node VdLarge saturation current IdCan be mirrored to an output node to increase VOUTThe slew rate of. However, there is an unnecessary consumption of ground current after the level conversion is completed, for example, when VINWhen the high level is kept, the left ground circuit is continuously conducted and I is continuously consumeddThe current to ground causes larger current consumption.
Therefore, there is a need to provide a novel high-speed and high-voltage level conversion circuit structure, which reduces transmission delay and simultaneously keeps low current consumption to ground.
Disclosure of Invention
The invention aims to reduce the transmission delay of a level conversion circuit, so that the size of the peripheral devices of the whole circuit of a power converter is reduced, and meanwhile, the ground current power consumption is kept low.
According to an aspect of the present invention, a high-speed high-voltage level shifter circuit applied to GaN gate driving is provided, including: the input circuit, the first PMOS transistor, the level conversion circuit and the shaping circuit;
the input circuit first end is connected to the level conversion circuit first end at a first node, the second end is connected to the drain electrode of a first PMOS transistor at a second node, the grid electrode of the first PMOS transistor is connected to the first power line, the source electrode of the first PMOS transistor is connected to the level conversion circuit second end at a third node, the level conversion circuit is connected to a second power line, the level conversion circuit second end is connected to the input end of the shaping circuit at the third node, the shaping circuit is connected to the first power line and the second power line, the output end of the shaping circuit is connected to the first end of the power device at a fourth node, and the power device is connected to the first power line and the third power line.
Preferably, the input circuit includes:
a first NMOS transistor having a gate for receiving an input signal and a drain connected to the first node;
a second NMOS transistor, a gate of the second NMOS transistor for receiving the inverted input signal, a drain of the second NMOS transistor connected to a drain of the first PMOS transistor, a source of the second NMOS transistor connected to ground potential;
a third NMOS transistor, a gate of the third NMOS transistor being configured to receive the inverted input signal, a drain of the third NMOS transistor being connected to a source of the first NMOS transistor, and a source of the third NMOS transistor being connected to a ground potential;
and one end of the capacitor is connected to the source electrode of the first NMOS transistor, and the other end of the capacitor is connected to the ground potential.
Preferably, the input circuit further comprises a zener diode, an anode of the zener diode being connected to the first node, and a cathode thereof being connected to a second power supply line.
Preferably, the input circuit includes:
a first NMOS transistor, a gate of the first NMOS transistor for receiving an input signal, a source of the first NMOS transistor connected to a ground potential;
a second NMOS transistor having a gate for receiving the inverted input signal and a source connected to a ground potential;
a third NMOS transistor, a gate of the third NMOS transistor being connected to a fourth power line, a source of the third NMOS transistor being connected to a drain of the first NMOS transistor;
a fourth NMOS transistor, a gate of which is connected to a fourth power line, a source of which is connected to a drain of the second NMOS transistor, and a drain of which is connected to a drain of the first PMOS transistor;
a gate of the eighth PMOS transistor is connected to a first power line, a drain of the eighth PMOS transistor is connected to a drain of the third NMOS transistor, and a source of the eighth PMOS transistor is connected to the first node.
Preferably, the level shift circuit includes a cross-coupling module and a pull-up module, the cross-coupling module is used for level shift, and the pull-up module is used for accelerating the level shift process.
Preferably, the cross-coupling module includes:
a second PMOS transistor having a source terminal connected to a second power line, a drain terminal connected to the third node, and a gate terminal connected to the first node;
a third PMOS transistor having a source terminal connected to a second power line, a drain terminal connected to the first node, and a gate terminal connected to the third node.
Preferably, the pull-up module comprises:
a fourth PMOS transistor having a gate terminal and a drain terminal connected to the first node;
a fifth PMOS transistor, wherein a source terminal of the fifth PMOS transistor is connected to a second power line, a gate terminal of the fifth PMOS transistor is connected to the third node, and a drain terminal of the fifth PMOS transistor is connected to a source terminal of the fourth PMOS transistor;
a sixth PMOS transistor having a gate terminal and a drain terminal connected to the third node;
a seventh PMOS transistor having a source terminal connected to a second power line, a gate terminal connected to the first node, and a drain terminal connected to the source terminal of the sixth PMOS transistor.
Preferably, the first terminal of the input circuit is a drain terminal of the first NMOS transistor, the second terminal of the input circuit is a drain terminal of the second NMOS transistor, the first terminal of the level shift circuit is a drain terminal of the third PMOS transistor, and the second terminal of the level shift circuit is a drain terminal of the second PMOS transistor.
Preferably, the first terminal of the input circuit is a source terminal of the eighth PMOS transistor, the second terminal of the input circuit is a drain terminal of the fourth NMOS transistor, the first terminal of the level shift circuit is a drain terminal of the third PMOS transistor, and the second terminal of the level shift circuit is a drain terminal of the second PMOS transistor.
Preferably, the first power line is a low potential for potential conversion, the second power line is a high potential for potential conversion, the third power line is a high voltage input of the power converter, and the fourth power line is a bias voltage.
The invention has the beneficial effects that: the high-speed high-voltage level conversion circuit provided by the invention has sub-ns transmission delay, can realize high speed and high frequency, and can work under the switching frequency of 30MHz, so that the size of peripheral devices of the whole circuit of the power converter is reduced, the area is further reduced, the cost is saved, and meanwhile, the lower power consumption of the ground current is kept.
Additional features and advantages of the invention will be set forth in the detailed description which follows.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent by describing in more detail exemplary embodiments thereof with reference to the attached drawings, in which like reference numerals generally represent like parts throughout.
Fig. 1 shows a block diagram of a typical GaN half-bridge driving circuit according to the prior art.
Fig. 2 shows a cross-coupled configuration high voltage level shifting circuit according to the prior art.
Fig. 3 shows a waveform schematic diagram of a cross-coupled high voltage level shifter according to the prior art.
Fig. 4 shows a current mirror structured high voltage level shifter circuit according to the prior art.
Fig. 5 shows a waveform diagram of a current mirror structure high voltage level shifter circuit according to the prior art.
Fig. 6 shows a high-speed high-voltage level shifter circuit applied to GaN driving according to a first embodiment of the present invention.
Fig. 7 shows simulation waveforms of the level shift circuit according to the first embodiment of the present invention.
Fig. 8 shows a high-speed high-voltage level shifter circuit applied to GaN driving according to a second embodiment of the present invention.
Detailed Description
Preferred embodiments of the present invention will be described in more detail below. While the following describes preferred embodiments of the present invention, it should be understood that the present invention may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
Example 1
Fig. 6 shows a high-speed high-voltage level shifter circuit applied to GaN driving according to a first embodiment of the present invention.
As shown in fig. 6, the present invention provides a high-speed high-voltage level shifter circuit applied to GaN gate driving, comprising: an input circuit 601, a first PMOS transistor 602 (i.e., MP1 in fig. 6), a level conversion circuit 603, and a shaping circuit 604; the first terminal of the input circuit 601 is connected to the first terminal of the level shifter circuit 603 at a first node NH, the second terminal is connected to the drain of the first PMOS transistor 602 at a second node a, the gate of the first PMOS transistor 602 is connected to the first power line, the source of the first PMOS transistor 602 is connected to the second terminal of the level shifter circuit 603 at a third node NL, the level shifter circuit 603 is connected to the second power line, the second terminal of the level shifter circuit 603 is connected to the input terminal of the shaping circuit 604 at the third node NL, the shaping circuit 604 is connected to the first power line and the second power line, the output terminal thereof is connected to the first terminal of the power device 605 at a fourth node B, and the power device 605 is connected to the first power line and the third power line.
The purpose of the embodiment is to reduce the transmission delay of the level conversion circuit to be less than 1ns, so that the size of the peripheral devices of the whole circuit of the power converter is reduced, and simultaneously, the ground current power consumption is kept low.
Preferably, the input circuit 601 includes:
a first NMOS transistor MN1, a gate of the first NMOS transistor MN1 for receiving an input signal, a drain of the first NMOS transistor MN1 connected to the first node NH;
a second NMOS transistor MN2, a gate of the second NMOS transistor MN2 for receiving the inverted input signal, a drain of the second NMOS transistor MN2 connected to the drain of the first PMOS transistor 602, a source of the second NMOS transistor MN2 connected to the ground potential;
a third NMOS transistor MN3, a gate of the third NMOS transistor MN3 for receiving an inverted input signal, a drain of the third NMOS transistor MN3 connected to the source of the first NMOS transistor MN1, a source of the third NMOS transistor MN3 connected to ground potential;
the capacitor C1 and the capacitor C1 have one end connected to the source of the first NMOS transistor MN1 and the other end connected to the ground potential.
Preferably, the input circuit 601 further includes a zener diode Z1, an anode of the zener diode Z1 is connected to the first node NH, and a cathode thereof is connected to the second power line.
Specifically, the diode Z1 is a zener diode for clamping the low voltage level of the first node NH and preventing the first node NH from being pulled down too low to exceed the gate-source withstand voltage of the second PMOS transistor MP2 during high voltage transition, which results in the breakdown of the second PMOS transistor MP2
Preferably, the level shifter 603 includes a cross-coupling module and a pull-up module, the cross-coupling module is used for level shifting, and the pull-up module is used for accelerating the level shifting process.
Preferably, the cross-coupling module includes:
a second PMOS transistor MP2, a source terminal of the second PMOS transistor MP2 being connected to the second power supply line, a drain terminal of the second PMOS transistor MP2 being connected to the third node NL, a gate terminal of the second PMOS transistor MP2 being connected to the first node NH;
a source terminal of the third PMOS transistor MP3, a drain terminal of the third PMOS transistor MP3 is connected to the second power line, a drain terminal of the third PMOS transistor MP3 is connected to the first node NH, and a gate terminal of the third PMOS transistor MP3 is connected to the third node NL.
Preferably, the pull-up module comprises:
a fourth PMOS transistor MP4, a gate terminal and a drain terminal of the fourth PMOS transistor MP4 being connected to the first node NH;
a fifth PMOS transistor MP5, a source terminal of the fifth PMOS transistor MP5 being connected to the second power line, a gate terminal of the fifth PMOS transistor MP5 being connected to the third node NL, a drain terminal of the fifth PMOS transistor MP5 being connected to a source terminal of the fourth PMOS transistor MP 4;
a sixth PMOS transistor MP6, a gate terminal and a drain terminal of the sixth PMOS transistor MP6 being connected to the third node NL;
a seventh PMOS transistor MP7, a source terminal of the seventh PMOS transistor MP7 is connected to the second power line, a gate terminal of the seventh PMOS transistor MP7 is connected to the first node NH, and a drain terminal of the seventh PMOS transistor MP7 is connected to a source terminal of the sixth PMOS transistor MP 6.
Preferably, the first terminal of the input circuit 601 is a drain terminal of the first NMOS transistor MN1, the second terminal of the input circuit 601 is a drain terminal of the second NMOS transistor MN2, the first terminal of the level shifter 603 is a drain terminal of the third PMOS transistor MP3, and the second terminal of the level shifter 603 is a drain terminal of the second PMOS transistor MP 2.
Preferably, the first power line is a low potential VSW at which the potential is changed, and the second power line is a high potential V at which the potential is changedBOOTThe third power line is the high-voltage input V of the power converterDDH。
The output end of the shaping circuit 604 is the output of the level shifter, and it needs to pass through the cascade buffer buf when controlling the on and off of the power device 605, and controls the on and off of the power device GaN after passing through the cascade buffer buf.
The technical scheme adopted by the embodiment is based on the traditional cross-coupled level converter, high-impedance nodes are eliminated, a pull-up structure is introduced to accelerate the level conversion speed, and a capacitor C1 and a switch tube MN3 are introduced to realize lower ground current power consumption.
Conventional cross-coupled high voltage level shifters remove Mdep1After a high-voltage tube is connected, a high-impedance node is eliminated, a Zener diode Z1 is used for clamping the low potential of NH, the situation that NH is pulled down too low during high-voltage conversion and exceeds the gate-source voltage resistance value of MP2 to cause MP2 breakdown is avoided, and meanwhile, pull-up modules MP4-7 are introduced to accelerate the pull-up process of NH and NL respectively, and further accelerate the level conversion process. And adding capacitors C1 and MN3 under MN1 to make the voltage at VINWhen the voltage is high level, the pull-down ground current of the original left branch circuit is changed into the charging current of the capacitor C1, and at the moment, the MN3 is switched off, the ground current is not formed, and further the overall power consumption of the ground current is reduced.
Low voltage input signal VINThe high and low levels of (1) are respectively 5V and 0V. VDDLThe low-voltage power supply voltage is 5V. And VDDHThe high voltage input (30V) of the power converter is VSW, which is connected to the grid of MP1 as a switch node and serves as a low potential for potential conversion. VDDHAs a high potential for high voltage conversion for bootstrap voltage, and VBOOTVSW is always kept constant at 5V. When GaN is turned on, VSW ≈ VDDHAnd then V isBOOTVSW + 5V. MN1 and MN2 are input transistors, wherein MN1, MN2 and MP1 are high-voltage MOS transistors to bear high voltage drop in the circuit. VHO is the output of level shifter, controls the switching on and off of power device GaN after cascade buffer Buf.
The level shift circuit level shifter applied to GaN half-bridge driving in the embodiment accords with high-speed high-voltage floating application. 3 high-voltage tubes (MN1, MN2 and MP1) are adopted to bear the high-voltage part, wherein MN1 and MN2 are high-voltage low-resistance MOS (metal oxide semiconductor) which are used as input tubes, so that the channel resistance is reduced, and the transmission delay is further reduced. The cross-coupled structure of MP2 and MP3 performs level conversion and connects floating ground SW to the gate of MP1, so that the whole level conversion circuit can shift the input signals 0-5V to the maximum 30-35V output, and realize high-voltage floating level conversion. The Pull-up structure is composed of MP4-7, the transmission delay is less than 1ns in the process of accelerating the Pull-up, and high-speed level conversion is realized. The method can be applied to GaN half-bridge drive to realize level conversion in a high-frequency (30MHz) environment.
When V is shown in FIG. 6INAt high MN1 is on and MN2 and MN3 are off. Since MN1 turns on pull-down NH, at this time, MP2 and MP7 turn on, two branches pull up NL at the same time, NL is high, MP3 and MP5 are turned off, and pull-down of NH is accelerated, and during this period, MN1 and MP3, MP4 and MP5 turn on momentarily at the same time, and since the pull-down capability of MN1 is much stronger than the pull-up capabilities of two branches MP3 and MP5, NH is pulled down to low potential. In the process, the MP4 connected in a diode mode also plays a role in limiting current so as to further ensure that the pull-up capability of NH is weaker than the pull-down capability at the moment. The on current of MN1 charges capacitor C1, which shifts the current to ground of MN1, while MN3 and MN2 turn off, thus reducing the total power consumption of current to ground. And since NL is pulled up to a high potential, VHO is output after being shaped by two inverters, and the GaN power device is turned on after passing through the cascade buffer Buf. When VSW is VDDHAnd V isBOOTIs bootstrapped to VSW + 5V.
When V isINAt low, MN1 is off, MN2, MN3 are on, and capacitor C1 discharges through MN 3. Since MN2 turns on pull-down NL to a low potential, i.e., close to VSW, and MP3 and MP5 turn on to pull up NH to a high potential, and then MP2 and MP7 are turned off, reducing the ability of NL to be pulled up and speeding up the pull-down process. And NL is pulled down to a low potential, VHO is output to the low potential after shaping by the two inverters, and the GaN power device is turned off after Buf of the cascade buffer.
Fig. 7 shows simulation waveforms of the level shift circuit according to the first embodiment of the present invention. Fig. 7 shows a level shift circuit designed to shift an input low voltage periodic square wave (30MHz) signal 0-5V to a simulated waveform on a high voltage floating voltage rail of 30-35V. The conduction transmission delay is input signal VINThe time from 10% at the time of the low potential to high potential transition to 10% at the time of the level shift circuit output VHO from the low potential to high potential. And the turn-off delay is the input signal VINThe time from 90% when the high potential is converted to the low potential to 90% when the level conversion circuit outputs VHO from the low potential to the high potential. Rise time as output VHO is 10% to 90% of the time of the level transition from low potential to high potential. The fall time is a time for which the output VHO is 90% to 10% of the level transition from the high potential to the low potential. Therefore, the simulation waveform shows that the on transmission delay 684ps and the off transmission delay 800 ps. Rise time 241ps and fall time 266 ps. Average current to ground 37.01uA (average value of current to ground over a period). High-speed high-voltage level conversion of sub-ns transmission delay is realized, and low current power consumption is ensured. The output signal is used for controlling a high-end GaN power tube after passing through the Buffer.
The high-speed high-voltage level conversion circuit provided by the embodiment has sub-ns transmission delay, can realize high speed and high frequency, and can work under the switching frequency of 30MHz, so that the size of peripheral devices of the whole circuit of the power converter is reduced, the area is reduced, the cost is saved, and meanwhile, the lower power consumption of the ground current is kept.
Example 2
Fig. 8 shows a high-speed high-voltage level shifter circuit applied to GaN driving according to a second embodiment of the present invention.
As shown in fig. 8, the present invention provides a high-speed high-voltage level shifter 803 applied to GaN gate driving, comprising: an input circuit 801, a first PMOS transistor 802 (i.e., MP1 in fig. 8), a level conversion circuit 803, and a shaping circuit 804; the first terminal of the input circuit 801 is connected to the first terminal of the level shifter circuit 803 at a first node NH, the second terminal is connected to the drain of the first PMOS transistor 802 at a first node a, the gate of the first PMOS transistor 802 is connected to a first power line, the source of the first PMOS transistor 802 is connected to the second terminal of the level shifter circuit 803 at a third node NL, the level shifter circuit 803 is connected to a second power line, the second terminal of the level shifter circuit 803 is connected to the input terminal of the shaping circuit 804 at the third node NL, the shaping circuit 804 is connected to the first power line and the second power line, the output terminal thereof is connected to the first terminal of the power device 805 at a fourth node B, and the power device 805 is connected to the first power line and the third power line.
Preferably, the input circuit 801 includes:
a first NMOS transistor MN1, a gate of the first NMOS transistor MN1 for receiving an input signal, a source of the first NMOS transistor MN1 connected to ground potential;
a second NMOS transistor MN2, a gate of the second NMOS transistor MN2 for receiving the inverted input signal, a source of the second NMOS transistor MN2 connected to the ground potential;
a third NMOS transistor MN3, a gate of the third NMOS transistor MN3 being connected to the fourth power line, a source of the third NMOS transistor MN3 being connected to the drain of the first NMOS transistor MN 1;
a fourth NMOS transistor MN4, a gate of the fourth NMOS transistor MN4 being connected to the fourth power supply line, a source of the fourth NMOS transistor MN4 being connected to the drain of the second NMOS transistor MN2, a drain of the fourth NMOS transistor MN4 being connected to the drain of the first PMOS transistor 802;
the eighth PMOS transistor MP8, the gate of the eighth PMOS transistor MP8 is connected to the first power line, the drain of the eighth PMOS transistor MP8 is connected to the drain of the third NMOS transistor MN3, and the source of the eighth PMOS transistor MP8 is connected to the first node NH.
Preferably, the level conversion circuit 803 includes a cross-coupling module and a pull-up module, where the cross-coupling module is used for level conversion, and the pull-up module is used for accelerating the level conversion process.
Preferably, the cross-coupling module includes:
a second PMOS transistor MP2, a source terminal of the second PMOS transistor MP2 being connected to the second power supply line, a drain terminal of the second PMOS transistor MP2 being connected to the third node NL, a gate terminal of the second PMOS transistor MP2 being connected to the first node NH;
a source terminal of the third PMOS transistor MP3, a drain terminal of the third PMOS transistor MP3 is connected to the second power line, a drain terminal of the third PMOS transistor MP3 is connected to the first node NH, and a gate terminal of the third PMOS transistor MP3 is connected to the third node NL.
Preferably, the pull-up module comprises:
a fourth PMOS transistor MP4, a gate terminal and a drain terminal of the fourth PMOS transistor MP4 being connected to the first node NH;
a fifth PMOS transistor MP5, a source terminal of the fifth PMOS transistor MP5 being connected to the second power line, a gate terminal of the fifth PMOS transistor MP5 being connected to the third node NL, a drain terminal of the fifth PMOS transistor MP5 being connected to a source terminal of the fourth PMOS transistor MP 4;
a sixth PMOS transistor MP6, a gate terminal and a drain terminal of the sixth PMOS transistor MP6 being connected to the third node NL;
a seventh PMOS transistor MP7, a source terminal of the seventh PMOS transistor MP7 is connected to the second power line, a gate terminal of the seventh PMOS transistor MP7 is connected to the first node NH, and a drain terminal of the seventh PMOS transistor MP7 is connected to a source terminal of the sixth PMOS transistor MP 6.
Preferably, the first terminal of the input circuit 801 is a source terminal of the eighth PMOS transistor MP8, the second terminal of the input circuit 801 is a drain terminal of the fourth NMOS transistor MN4, the first terminal of the level shifter 803 is a drain terminal of the third PMOS transistor MP3, and the second terminal of the level shifter 803 is a drain terminal of the second PMOS transistor MP 2.
Preferably, the first power line is a low potential VSW at which the potential is changed, and the second power line is a high potential V at which the potential is changedBOOTThe third power line is the high-voltage input V of the power converterDDHThe fourth power line is bias voltage VBIAS。
The output end of the shaping circuit 804 is the output of the level shifter, and it needs to pass through the cascade buffer buf when controlling the on and off of the power device 805, and controls the on and off of the power device GaN after passing through the cascade buffer buf.
As shown in FIG. 8, from the circuit structure, capacitors C1 and MN3 in FIG. 6 are removed, high voltage input tubes MN1 and MN2 are replaced by low voltage MOS tubes in FIG. 8 to realize the fast processing of signals, high voltage MOS of MN3 and MN4 are added to provide an isolation voltage division effect larger than 30V, and the gates of MN3 and MN4 are provided with a bias voltage VBIAS(5V) and a high voltage DEPMOS-MP2, V identical to MP1 is added in the left branchSSHThe low-potential NH is connected to the gate of MP2 and is used as the low potential when NH is pulled down, so that NH is prevented from being excessively pulled down in the pulling-down process to exceed the gate-source voltage withstanding value of MP3 or the source-drain voltage withstanding value of MP4, and the same realization is realizedIsolating the voltage division effect, the zener diode Z1 can be eliminated, relatively due to the effect of MP 2. The solution shown in fig. 8 is not as small in transmission delay as the solution in embodiment 1, but can still achieve lower transmission delay and relatively low current consumption.
The high-speed high-voltage level conversion circuit provided by the embodiment has sub-ns transmission delay, can realize high speed and high frequency, and can work under the switching frequency of 30MHz, so that the size of peripheral devices of the whole circuit of the power converter is reduced, the area is reduced, the cost is saved, and meanwhile, the lower power consumption of the ground current is kept.
It will be appreciated by persons skilled in the art that the above description of embodiments of the invention is intended only to illustrate the benefits of embodiments of the invention and is not intended to limit embodiments of the invention to any examples given.
Having described embodiments of the present invention, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments.

Claims (9)

1. A high-speed high-voltage level conversion circuit applied to GaN gate drive is characterized by comprising: the input circuit, the first PMOS transistor, the level conversion circuit and the shaping circuit;
the input circuit first end is connected to the level conversion circuit first end at a first node, the second end is connected to the drain electrode of a first PMOS transistor at a second node, the grid electrode of the first PMOS transistor is connected to a first power line, the source electrode of the first PMOS transistor is connected to the level conversion circuit second end at a third node, the level conversion circuit is connected to a second power line, the level conversion circuit second end is connected to the input end of the shaping circuit at the third node, the shaping circuit is connected to the first power line and the second power line, the output end of the shaping circuit is connected to the first end of a power device at a fourth node, and the power device is connected to the first power line and the third power line;
the input circuit includes:
a first NMOS transistor having a gate for receiving an input signal and a drain connected to the first node;
a second NMOS transistor, a gate of the second NMOS transistor for receiving the inverted input signal, a drain of the second NMOS transistor connected to a drain of the first PMOS transistor, a source of the second NMOS transistor connected to ground potential;
a third NMOS transistor, a gate of the third NMOS transistor being configured to receive the inverted input signal, a drain of the third NMOS transistor being connected to a source of the first NMOS transistor, and a source of the third NMOS transistor being connected to a ground potential;
and one end of the capacitor is connected to the source electrode of the first NMOS transistor, and the other end of the capacitor is connected to the ground potential.
2. The high speed high voltage level shifter circuit applied to GaN gate drive of claim 1, wherein the input circuit further comprises a Zener diode having an anode connected to the first node and a cathode connected to a second power line.
3. The high-speed high-voltage level shifter circuit applied to GaN gate drive of claim 1, wherein the level shifter circuit comprises a cross-coupling module and a pull-up module, the cross-coupling module is used for level shifting, and the pull-up module is used for accelerating the level shifting process.
4. The high-speed high-voltage level shifter circuit applied to GaN gate drive of claim 3, wherein the cross-coupling module comprises:
a second PMOS transistor having a source terminal connected to a second power line, a drain terminal connected to the third node, and a gate terminal connected to the first node;
a third PMOS transistor having a source terminal connected to a second power line, a drain terminal connected to the first node, and a gate terminal connected to the third node.
5. The high-speed high-voltage level shifter circuit applied to GaN gate drive of claim 3, wherein the pull-up module comprises:
a fourth PMOS transistor having a gate terminal and a drain terminal connected to the first node;
a fifth PMOS transistor, wherein a source terminal of the fifth PMOS transistor is connected to a second power line, a gate terminal of the fifth PMOS transistor is connected to the third node, and a drain terminal of the fifth PMOS transistor is connected to a source terminal of the fourth PMOS transistor;
a sixth PMOS transistor having a gate terminal and a drain terminal connected to the third node;
a seventh PMOS transistor having a source terminal connected to a second power line, a gate terminal connected to the first node, and a drain terminal connected to the source terminal of the sixth PMOS transistor.
6. The high speed, high voltage level shifter circuit applied to GaN gate drive of claim 4, wherein the first terminal of the input circuit is a drain terminal of the first NMOS transistor, the second terminal of the input circuit is a drain terminal of the second NMOS transistor, the first terminal of the level shifter circuit is a drain terminal of the third PMOS transistor, and the second terminal of the level shifter circuit is a drain terminal of the second PMOS transistor.
7. The high speed high voltage level shifter circuit applied to GaN gate drive of claim 4, wherein the input circuit comprises:
a first NMOS transistor, a gate of the first NMOS transistor for receiving an input signal, a source of the first NMOS transistor connected to a ground potential;
a second NMOS transistor having a gate for receiving the inverted input signal and a source connected to a ground potential;
a third NMOS transistor, a gate of the third NMOS transistor being connected to a fourth power line, a source of the third NMOS transistor being connected to a drain of the first NMOS transistor;
a fourth NMOS transistor, a gate of which is connected to a fourth power line, a source of which is connected to a drain of the second NMOS transistor, and a drain of which is connected to a drain of the first PMOS transistor;
a gate of the eighth PMOS transistor is connected to a first power line, a drain of the eighth PMOS transistor is connected to a drain of the third NMOS transistor, and a source of the eighth PMOS transistor is connected to the first node.
8. The high speed high voltage level shifter circuit applied to GaN gate drive of claim 7, wherein the first terminal of the input circuit is a source terminal of the eighth PMOS transistor, the second terminal of the input circuit is a drain terminal of the fourth NMOS transistor, the first terminal of the level shifter circuit is a drain terminal of the third PMOS transistor, and the second terminal of the level shifter circuit is a drain terminal of the second PMOS transistor.
9. The high speed high voltage level shifter circuit applied to GaN gate drive of claim 7, wherein the first power line is a low voltage level for voltage shifting, the second power line is a high voltage level for voltage shifting, the third power line is a high voltage input of a power converter, and the fourth power line is a bias voltage.
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