CN112671391B - Level conversion circuit - Google Patents
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- CN112671391B CN112671391B CN202011522544.6A CN202011522544A CN112671391B CN 112671391 B CN112671391 B CN 112671391B CN 202011522544 A CN202011522544 A CN 202011522544A CN 112671391 B CN112671391 B CN 112671391B
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Abstract
The embodiment of the application discloses a level switching circuit, relates to the technical field of level switching, and aims to reduce dynamic power consumption in the level switching process. The level shift circuit includes: the level conversion module comprises a pull-up transistor connected with a power supply and a pull-down transistor connected with the ground, wherein the pull-down transistor is used for inputting a low-voltage level signal, and the pull-up transistor is used for outputting a high-voltage level signal corresponding to the low-voltage level signal; the pull-up transistor and the pull-down transistor are connected through a clamp transistor, so that when the pull-up transistor and the pull-down transistor are simultaneously conducted, the current flowing through the pull-up transistor, the clamp transistor and the pull-down transistor is smaller than a preset current threshold value. The application is applicable to level conversion.
Description
Technical Field
The application relates to the technical field of level conversion, in particular to a level conversion circuit.
Background
In a circuit system, there are usually two or more power domains, the power supplies of each power domain respectively supply power to corresponding circuits, and the circuits in one power domain inevitably need to use signals in other power domains, such as a digital power supply and an analog power supply to supply power to digital and analog circuits, respectively, while the control signal of the analog circuit comes from the digital power domain, which needs a level shifter (level shifter) to implement level shifting across the power domains.
Fig. 1 is a level shifter circuit IN the prior art, which has a large dynamic power consumption IN a process of implementing level conversion IN the prior art, where an input signal IN is a low supply Voltage (VDDL) domain, and needs to be converted into a high supply Voltage (VDDH) domain, the input signal IN drives pull-down transistors N1 and N2 through two-stage Inverters (INV), respectively, and after passing through cross-coupled pairs (cross pair) P1 and P2, the input signal IN is output through one-stage inverters, an output OUT corresponds to a logic level relationship of the input signal IN, and at the same time, the power domain of the OUT is raised to VDDH, and when the input signal IN is converted from low to high, a gate voltage of a cross-coupled transistor P1 is raised from 0 to VDDH, so that when the pull-down transistor N1 and the pull-up transistor P1 are turned on at the same time, the dynamic power consumption is large.
Disclosure of Invention
In view of this, embodiments of the present disclosure provide a level shift circuit, which can reduce dynamic power consumption during a level shift process.
An embodiment of the present application provides a level shift circuit, including: the level conversion module comprises a pull-up transistor connected with a power supply and a pull-down transistor connected with the ground, wherein the pull-down transistor is used for inputting a low-voltage level signal, and the pull-up transistor is used for outputting a high-voltage level signal corresponding to the low-voltage level signal; the pull-up transistor and the pull-down transistor are connected through a clamp transistor, so that when the pull-up transistor and the pull-down transistor are simultaneously conducted, the current flowing through the pull-up transistor, the clamp transistor and the pull-down transistor is smaller than a preset current threshold value.
According to a specific implementation manner of the embodiment of the present application, the method further includes: the low-voltage input module and the high-voltage output module; the low-voltage input module is connected with the level conversion module and transmits a low-voltage level signal to the level conversion module; one end of the level conversion module is connected with the low-voltage input module, and the other end of the level conversion module is connected with the high-voltage output module, so that the low-voltage level signal is converted into a corresponding high-voltage level signal; the high-voltage output module is connected with the level conversion module and outputs the high-voltage level signal; the low-voltage input module, the level conversion module and the high-voltage output module enable a first signal transmission path when the low-voltage level signal jumps from a high level to a low level to be matched with circuit elements in a second signal transmission path when the low-voltage level signal jumps from the low level to the high level; the matching comprises: the circuit elements are identical and/or the kinds of circuit elements are identical.
According to a specific implementation manner of the embodiment of the present application, the types of the circuit elements include: transistor-like elements and/or logic gate-like elements.
According to a specific implementation manner of the embodiment of the application, the pull-up transistor comprises a first pull-up tube and a second pull-up tube; the clamping transistor comprises a third clamping tube and a fourth clamping tube; the source electrode of the first pull-up tube is connected with a high-voltage power supply of the level conversion module, the grid electrode of the first pull-up tube is connected with the grid electrode of the fourth clamping tube, and the drain electrode of the first pull-up tube is connected with the source electrode of the third clamping tube; the source electrode of the second pull-up tube is connected with a high-voltage power supply of the level conversion module, the grid electrode of the second pull-up tube is connected with the grid electrode of the third clamping tube, and the drain electrode of the second pull-up tube is connected with the source electrode of the fourth clamping tube; the grid electrode of the third clamping tube is connected with the drain electrode; and the grid electrode of the fourth clamping tube is connected with the drain electrode.
According to a specific implementation manner of the embodiment of the present application, the pull-down transistor includes: the device comprises a first pull-down pipe, a second pull-down pipe, a third pull-down pipe and a fourth pull-down pipe; the grid electrode of the second pull-down tube and the grid electrode of the fourth pull-down tube are connected with the first output end of the low-voltage input module; the source electrode of the second pull-down tube and the source electrode of the fourth pull-down tube are respectively grounded; the drain electrode of the second pull-down tube is connected with the drain electrode of the fourth clamping tube, and the drain electrode of the fourth pull-down tube is connected with the source electrode of the fourth clamping tube; the grid electrode of the first pull-down tube and the grid electrode of the third pull-down tube are connected with the second output end of the low-voltage input module; the source electrode of the first pull-down tube and the source electrode of the third pull-down tube are respectively grounded; the drain electrode of the first pull-down tube is connected with the drain electrode of the third clamping tube, and the drain electrode of the third pull-down tube is connected with the source electrode of the third clamping tube; and the output level of the first output end of the low-voltage input module is opposite to the output level of the second output end of the low-voltage input module.
According to a specific implementation manner of the embodiment of the application, the low-voltage input module comprises: the inverter comprises a first inverter and a second inverter which are connected in series, wherein the output end of the first inverter is the first output end, and the output end of the second inverter is the second output end.
According to a specific implementation manner of the embodiment of the application, the high-voltage output module comprises an RS latch.
According to a specific implementation manner of the embodiment of the present application, the RS latch includes: two cross-coupled nand gates, or two cross-coupled nor gates.
The level conversion circuit provided by the embodiment of the application comprises a level conversion module, wherein the level conversion module comprises a pull-up transistor connected with a power supply and a pull-down transistor connected with the ground, the pull-down transistor is used for inputting a low-voltage level signal, the pull-up transistor is used for outputting a high-voltage level signal corresponding to the low-voltage level signal, the pull-up transistor and the pull-down transistor are connected through a clamp transistor, so that when the pull-up transistor and the pull-down transistor are simultaneously conducted, the current flowing through the pull-up transistor, the clamp transistor and the pull-down transistor is smaller than a preset current threshold value, and as the pull-up transistor and the pull-down transistor are connected through the clamp transistor, the grid source voltage of the clamp transistor is clamped to a conducting threshold voltage.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a prior art level shifter circuit;
fig. 2 is a schematic structural diagram of a level shift circuit according to an embodiment of the present disclosure;
fig. 3 is a timing comparison diagram of a level shift circuit in the prior art and a level shift circuit of the present application.
Detailed Description
The embodiments of the present application will be described in detail below with reference to the accompanying drawings.
It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
As background art, an existing level shifter circuit is simple in structure, but dynamic power consumption of the circuit in an input signal turning process is too large, and duty ratio distortion of an input clock signal is obvious. Therefore, the method is limited to low speed and low power consumption, such as level conversion of a common pulse signal and level conversion of a low frequency clock.
The low power consumption is an important concern in the application fields of portable electronic equipment, intelligent wearing, wireless sensors and the like at present, and the dynamic power consumption is an important component of the power consumption and reflects the power consumption index of a circuit signal in the dynamic turning process.
Based on this, the application provides a level shift circuit, can reduce the dynamic power consumption in the level shift process, is applicable to low-power consumption, high-speed application field.
In order to make those skilled in the art better understand the technical concepts, embodiments and advantages of the examples of the present application, the following detailed description is given by way of specific examples.
Fig. 2 is a schematic structural diagram of a level shift circuit according to an embodiment of the present disclosure, and as shown in fig. 2, the level shift circuit according to the embodiment includes: the level conversion module 1, the level conversion module 1 includes a pull-up transistor 10 connected to a power supply and a pull-down transistor 12 connected to ground, the pull-down transistor 12 is used for inputting a low-voltage level signal, and the pull-up transistor 10 is used for outputting a high-voltage level signal corresponding to the low-voltage level signal; the pull-up transistor 10 and the pull-down transistor 12 are connected through a clamp transistor 14 such that when the pull-up transistor 10 and the pull-down transistor 12 are simultaneously turned on, the current flowing through the pull-up transistor 10, the clamp transistor 14, and the pull-down transistor 12 is less than a predetermined current threshold.
The low voltage level signal may include a low level signal and a high level signal, and the high voltage level signal may include a low level signal and a high level signal, for example, the low level of the low voltage level signal may be 0V, the high level may be 3V, the low level of the corresponding high voltage level signal may be 0V, and the high level signal may be 15V.
The level shift circuit of the present embodiment can be applied to a System-on-Chip (SOC).
The transistor is a solid semiconductor device and may be a field effect transistor.
During the operation of the circuit, the pull-up transistor 10 can pull up the output voltage to a high-voltage level signal; the pull-down transistor 12 may pull down the voltage of the corresponding terminal of the device connected thereto while being used for inputting a low voltage level signal.
The clamp transistor 14 may clamp the voltage between the gate and the source to a turn-on threshold voltage such that, when the pull-up transistor 10 is turned on, the gate voltage of the clamp transistor 14 is the supply voltage connected to the pull-up transistor 10 minus the turn-on threshold voltage, resulting in a reduction in the peak current at which the pull-up transistor 10 is turned on.
Since the dynamic power consumption is positively correlated to the charge amount from the power supply to the ground, and the charge amount is equal to the integral of the dynamic current and time, when the power supply voltage and the input signal are constant and the dynamic current is reduced, the dynamic power consumption of the simultaneous conduction of the pull-up transistor 10, the pull-down transistor 12 and the clamp transistor 14 is also reduced in the process that the low-voltage level signal changes from high to low or from low to high.
The level conversion circuit of the embodiment comprises a level conversion module, wherein the level conversion module comprises a pull-up transistor connected with a power supply and a pull-down transistor connected with the ground, the pull-down transistor is used for inputting a low-voltage level signal, the pull-up transistor is used for outputting a high-voltage level signal corresponding to the low-voltage level signal, and the pull-up transistor and the pull-down transistor are connected through a clamp transistor, so that when the pull-up transistor and the pull-down transistor are simultaneously conducted, the current flowing through the pull-up transistor, the clamp transistor and the pull-down transistor is less than a preset current threshold value.
The level shift circuit of the embodiment of the application further includes: the low-voltage input module 2 and the high-voltage output module 3; the low-voltage input module 2 is connected with the level conversion module 1 and transmits a low-voltage level signal to the level conversion module; one end of the level conversion module 1 is connected with the low-voltage input module 2, and the other end of the level conversion module is connected with the high-voltage output module 3, so that low-voltage level signals are converted into corresponding high-voltage level signals; the high-voltage output module 3 is connected with the level conversion module 1 and outputs a high-voltage level signal; the low-voltage input module 2, the level conversion module 1 and the high-voltage output module 3 enable a first signal transmission path when a low-voltage level signal jumps from a high level to a low level to be matched with circuit elements in a second signal transmission path when a low-voltage level signal jumps from a low level to a high level.
Matching may include circuit elements being identical; alternatively, the circuit elements are of the same kind; alternatively, the circuit elements and the circuit elements are of the same kind, and in one example, the kinds of the circuit elements include: transistor-like elements and/or logic gate-like elements.
In one example, the high voltage output module 3 includes an RS latch. The RS latch in one example includes: two cross-coupled nand gates, or two cross-coupled nor gates.
In another example, the high voltage output module 3 may include an output buffer stage in addition to the RS latch.
The first signal transmission path may be a path formed by circuit elements through which signals sequentially flow in a process of a transition of an input low-voltage level signal from a high level to a low level; the second signal transmission path may be a path formed by circuit elements through which signals sequentially flow during a transition of an input low-voltage level signal from a low level to a high level. The first signal transmission path and the second signal transmission path may be the same or different. When the first signal transmission path is the same as the second signal transmission path, the circuit element of the first signal transmission path matches the circuit element of the second signal transmission path; because the low-voltage input module and the high-voltage output module of the embodiment are connected with the level conversion module, when the first signal transmission path is different from the second signal transmission path, the circuit elements IN the first signal transmission path and the second signal transmission path can be matched, so that the delays of the circuit elements IN the first signal transmission path and the second signal transmission path are correspondingly matched, and thus, the delay of the first signal transmission path for the low-voltage level signal to jump from the low level to the high level is basically the same as the delay of the second signal transmission path for the high level to jump from the high level to the low level, that is, the transmission time of the low-voltage level signal on the two transmission paths is basically the same.
The pull-up transistor 10 of an embodiment of the present application includes a first pull-up tube P1 and a second pull-up tube P2; clamp transistor 14 includes a third clamp transistor P3 and a fourth clamp transistor P4; the source electrode of the first pull-up tube P1 is connected with a high-voltage power supply of the level conversion module 1, the grid electrode of the first pull-up tube P1 is connected with the grid electrode of the fourth clamping tube P4, and the drain electrode of the first pull-up tube P1 is connected with the source electrode of the third clamping tube P3; the source electrode of the second pull-up tube P2 is connected with the high-voltage power supply of the level conversion module 1, the grid electrode of the second pull-up tube P2 is connected with the grid electrode of the third clamping tube P3, and the drain electrode of the second pull-up tube P2 is connected with the source electrode of the fourth clamping tube P4; the grid electrode of the third clamping tube P3 is connected with the drain electrode; the grid electrode of the fourth clamping pipe P4 is connected with the drain electrode.
In some examples, pull-down transistor 12 includes: a first pull-down pipe N1, a second pull-down pipe N2, a third pull-down pipe N3 and a fourth pull-down pipe N4; the grid electrode of the second pull-down tube N2 and the grid electrode of the fourth pull-down tube N4 are connected with the first output end of the low-voltage input module 2; the source electrode of the second pull-down tube N2 and the source electrode of the fourth pull-down tube N4 are respectively grounded; the drain electrode of the second pull-down tube N2 is connected with the drain electrode of the fourth clamping tube P4, and the drain electrode of the fourth pull-down tube N4 is connected with the source electrode of the fourth clamping tube P4; the grid electrode of the first pull-down tube N1 and the grid electrode of the third pull-down tube N3 are connected with the second output end of the low-voltage input module 2; the source electrode of the first pull-down tube N1 and the source electrode of the third pull-down tube N3 are respectively grounded; the drain electrode of the first pull-down tube N1 is connected with the drain electrode of the third clamping tube P3, and the drain electrode of the third pull-down tube N3 is connected with the source electrode of the third clamping tube P3; the output level of the first output terminal of the low voltage input module 2 is opposite to the output level of the second output terminal of the low voltage input module 2.
In order to enhance the pull-down capability and increase the signal inversion speed, so that the level shift circuit of this embodiment is suitable for high-speed applications, N3 and N4 in the pull-down transistor 12 of this embodiment can match the set and reset functions of the RS latch in the high-voltage output module.
In one example, the low voltage input module 2 includes: the inverter comprises a first inverter INV1 and a second inverter INV2 which are connected in series, wherein the output end of the first inverter INV1 is a first output end, and the output end of the second inverter INV2 is a second output end.
The operation of the level shift circuit of the present application is described below with an embodiment.
Fig. 3 is a timing comparison diagram of a level shift circuit in the prior art and a level shift circuit of the present application. See fig. 1, 2 and 3.
The level shifter circuit of this embodiment is composed of two input inverters, two sets of pull-down tubes N1 to N4, cross-coupled pair pull-up tubes P1 and P2, clamp tubes P3 and P4, a latch, and two output inverters.
When the input low voltage level signal IN is at a low level, INN is at a high level, and the gate terminal voltage INT2 of the clamp P4 is pulled down due to the pull-down action of the pull-down tube N2.
When the input low-voltage level signal IN is at a high level, INP is at a high level, and due to the pull-down action of the pull-down tube N1, the gate terminal voltage INT1 of the clamp tube P3 is pulled down, and at this time, the cross-coupled pull-up tube P2 is turned on, pulling OUT _ R to a high level VDDH. Since INN is low and pull-down transistor N2 is turned off, clamp P4 is also turned off, and the clamping action of clamp P4 fixes the gate-source voltage to | VTHP |, so that gate terminal voltage INT2 of P4 is reduced to VDDH | -VTHP | (the turn-on threshold voltage VTHP of the PMOS transistor is negative).
IN summary, when the input low-voltage level signal IN jumps from low to high, the node voltage INT2 rises from 0 to VDDH- | VTHP |, i.e., the highest conducting voltage of the clamp P4 is lowered from VDDH of the conventional level shifter structure to VDDH- | VTHP |, so that the dynamic power consumption of the branch can be greatly reduced when the pull-down transistor N2 is simultaneously conducted with the clamp P4 and the cross-coupled transistor P2.
Similarly, when the input low voltage level signal IN jumps from high to low, the node voltage lNT rises from 0 to VDDH- | VTHP |, i.e., the highest conducting voltage of the clamp P3 is lowered from VDDH of the conventional level shifter structure to VDDH- | VTHP |, so that the dynamic power consumption of the branch can be greatly reduced when the pull-down transistor N1 is conducted with the clamp P3 and the cross-coupled transistor P1 at the same time.
During the transition of the input (low voltage) level signal, the maximum voltage VDDH- | VTHP | of the node voltages INT1 and INT2 of the present embodiment is reduced by a threshold voltage | VTHP | compared to VDDH of the conventional structure, so that the peak current of the cross-coupled transistor P1 when conducting is greatly reduced. Due to dynamic short circuit power consumption Pshort = VDD × fr × Qx, where VDD is the supply voltage, fr is the inversion rate of the input signal IN, and Qx is the amount of charge of the power supply to ground during each inversion. The amount of the discharged charge Qx is reduced by the peak current, which is equal to the integral of the dynamic current with respect to time, so that the dynamic short-circuit power consumption of the level shift circuit of the present embodiment is greatly reduced for the same supply voltage VDDH and the same input signal.
In addition, the level shifter circuit of the embodiment is additionally provided with pull-down pair transistors N3 and N4, the pull-down capability is enhanced, and meanwhile, the signal turning speed is increased by matching with a latch formed by a NAND gate, so that the level shifter circuit is suitable for high-speed application occasions. IN addition, the level shifter circuit of the embodiment adopts a symmetrical structure, when the input signal IN jumps from low to high, the signal transmission path is IN- > INV1- > INV2- > pull-down tube N3- > nand2- > INV3- > INV4; when an input signal is transited from high to low, the signal transmission path is IN- > lNV- > pull-down tube N4- > nand1- > nand2- > INV3- > INV4, therefore, the delay of the transmission path of the input signal from low to high and from high to low is easy to be the same as long as the delay of INV2 is matched with that of nand1, and the duty ratio of an output clock after the level of a high-speed clock signal is converted is optimized.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments.
In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and reference may be made to the partial description of the method embodiment for relevant points.
For convenience of description, the above devices are described separately in terms of functional division into various units/modules. Of course, the functionality of the units/modules may be implemented in one or more software and/or hardware implementations when the present application is implemented.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (8)
1. A level shift circuit, comprising:
the level conversion module comprises a pull-up transistor connected with a power supply and a pull-down transistor connected with the ground, wherein the pull-down transistor is used for inputting a low-voltage level signal, and the pull-up transistor is used for outputting a high-voltage level signal corresponding to the low-voltage level signal;
the pull-up transistor and the pull-down transistor are connected through a clamp transistor, so that when the pull-up transistor and the pull-down transistor are simultaneously conducted, the current flowing through the pull-up transistor, the clamp transistor and the pull-down transistor is smaller than a preset current threshold value.
2. The level shift circuit of claim 1, further comprising: the low-voltage input module and the high-voltage output module;
the low-voltage input module is connected with the level conversion module and transmits a low-voltage level signal to the level conversion module;
one end of the level conversion module is connected with the low-voltage input module, the other end of the level conversion module is connected with the high-voltage output module, and the level conversion module converts the low-voltage level signals into corresponding high-voltage level signals;
the high-voltage output module is connected with the level conversion module and outputs the high-voltage level signal;
the low-voltage input module, the level conversion module and the high-voltage output module enable a first signal transmission path when the low-voltage level signal jumps from a high level to a low level to be matched with a circuit element in a second signal transmission path when the low-voltage level signal jumps from the low level to the high level; the matching includes: the circuit elements are identical and/or the kinds of circuit elements are identical.
3. The circuit of claim 2, wherein the circuit elements are of the type comprising: transistor-like elements and/or logic gate-like elements.
4. The level shift circuit of claim 2, wherein the pull-up transistor comprises a first pull-up transistor and a second pull-up transistor; the clamping transistor comprises a third clamping tube and a fourth clamping tube;
the source electrode of the first pull-up tube is connected with a high-voltage power supply of the level conversion module, the grid electrode of the first pull-up tube is connected with the grid electrode of the fourth clamping tube, and the drain electrode of the first pull-up tube is connected with the source electrode of the third clamping tube; the source electrode of the second pull-up tube is connected with a high-voltage power supply of the level conversion module, the grid electrode of the second pull-up tube is connected with the grid electrode of the third clamping tube, and the drain electrode of the second pull-up tube is connected with the source electrode of the fourth clamping tube;
the grid electrode of the third clamping tube is connected with the drain electrode; and the grid electrode of the fourth clamping tube is connected with the drain electrode.
5. The circuit of claim 4, wherein the pull-down transistor comprises: the device comprises a first pull-down pipe, a second pull-down pipe, a third pull-down pipe and a fourth pull-down pipe;
the grid electrode of the second pull-down tube and the grid electrode of the fourth pull-down tube are connected with the first output end of the low-voltage input module; the source electrode of the second pull-down tube and the source electrode of the fourth pull-down tube are respectively grounded; the drain electrode of the second pull-down tube is connected with the drain electrode of the fourth clamping tube, and the drain electrode of the fourth pull-down tube is connected with the source electrode of the fourth clamping tube;
the grid electrode of the first pull-down tube and the grid electrode of the third pull-down tube are connected with the second output end of the low-voltage input module; the source electrode of the first pull-down tube and the source electrode of the third pull-down tube are respectively grounded; the drain electrode of the first pull-down tube is connected with the drain electrode of the third clamping tube, and the drain electrode of the third pull-down tube is connected with the source electrode of the third clamping tube;
the output level of the first output end of the low-voltage input module is opposite to the output level of the second output end of the low-voltage input module.
6. The level shift circuit of claim 5, wherein the low voltage input module comprises: the first phase inverter and the second phase inverter are connected in series, wherein an output end of the first phase inverter is the first output end, and an output end of the second phase inverter is the second output end.
7. The level shift circuit of claim 2, wherein the high voltage output module comprises an RS latch.
8. The level shift circuit of claim 7, wherein the RS latch comprises: two cross-coupled nand gates, or two cross-coupled nor gates.
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| CN115620758A (en) * | 2021-07-16 | 2023-01-17 | 长鑫存储技术有限公司 | Voltage conversion circuit and memory |
| CN113611245B (en) * | 2021-08-17 | 2022-08-26 | 深圳市绿源半导体技术有限公司 | Bidirectional transmission device and control method |
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| CN112671391A (en) | 2021-04-16 |
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