CN112073054A

CN112073054A - Level shifter

Info

Publication number: CN112073054A
Application number: CN201910498560.7A
Authority: CN
Inventors: 黄武; 李彬; 周伟雄
Original assignee: Will Semiconductor Ltd
Current assignee: Will Semiconductor Ltd
Priority date: 2019-06-10
Filing date: 2019-06-10
Publication date: 2020-12-11
Anticipated expiration: 2039-06-10
Also published as: CN112073054B

Abstract

The invention discloses a level shifter, which comprises an output end, a first input end, a second input end, a latch circuit, a level overturning pull-down circuit and a voltage clamping circuit, wherein the latch circuit is connected with the output end; the latch circuit comprises a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube; the voltage clamping circuit comprises a first clamping device, a second clamping device, a third NMOS tube, a fourth NMOS tube, a fifth PMOS tube and a sixth PMOS tube; the level overturning pull-down circuit comprises a fifth NMOS tube and a sixth NMOS tube; the first clamping device is used for clamping the voltage of the grid electrodes of the fifth PMOS tube and the sixth PMOS tube; the second clamping device is used for clamping the voltage of the grid electrodes of the third NMOS tube and the fourth NMOS tube. The invention completes level conversion with high speed and low power consumption under the condition of the change of the ground level of the high-voltage driving signal, and has lower cost. The gate oxide layer of a transistor device in the level shifter can be protected from being broken down through the voltage clamping circuit, and the high voltage at the output end is isolated; zero static power consumption and level rapid turnover are realized through the latch circuit and the level turnover pull-down circuit, and the latch circuit has strong driving capability.

Description

Level shifter

Technical Field

The present invention relates to the field of level shifters, and more particularly, to a level shifter for converting a high voltage driving signal, which is applied to a low voltage logic signal changing to a ground level.

Background

The circuit application needs level conversion of a high-voltage driving signal with a low-voltage logic signal changing to a ground level. For example, in a dual NMOS (N-type metal-oxide-semiconductor) drive circuit in a conventional synchronous switching power supply topology, the process of level transition of a high-voltage drive signal involving a change of a low-voltage logic signal to a ground level is driven for the NMOS gate on the high-voltage side. When a bootstrap circuit is used to drive the NMOS gate on the high-voltage side, the thin gate oxide device in the conventional process may be broken down if the bootstrap voltage is higher than 5V (volts). In order to solve the problem of the damage of high bootstrap voltage, a thick gate oxide device is adopted to realize voltage resistance in the traditional method, but the method has high cost and has strict requirements on the voltage resistance of the gate oxide of the device. The level shifter shown in fig. 1 is also adopted, and only a drain-to-terminal voltage-resistant LDMOS (laterally diffused metal oxide semiconductor) device needs to be used, but after the circuit is turned over, the quiescent current IB is consistent, so that the level shifter has the defect of large quiescent power consumption, which is not favorable for realizing low power consumption.

Disclosure of Invention

The invention aims to overcome the defects of high cost and large static power consumption of an implementation mode of carrying out level conversion on a high-voltage driving signal of which a low-voltage logic signal changes to the ground level in the prior art, and provides a level converter which is high in speed, low in power consumption, resistant to high voltage and low in cost and is applied to conversion of the high-voltage driving signal of which the low-voltage logic signal changes to the ground level.

The invention solves the technical problems through the following technical scheme:

the invention provides a level shifter, which comprises an output end, a first input end and a second input end, wherein input signals of the first input end and the second input end are two complementary low-voltage logic signals;

the latch circuit comprises a first PMOS (P-type metal-oxide-semiconductor) tube, a second PMOS tube, a first NMOS tube and a second NMOS tube;

the voltage clamping circuit comprises a first clamping device, a second clamping device, a third NMOS tube, a fourth NMOS tube, a fifth PMOS tube and a sixth PMOS tube;

the level overturning pull-down circuit comprises a fifth NMOS tube and a sixth NMOS tube;

the source stage of the first PMOS tube and the source stage of the second PMOS tube are respectively and electrically connected with an analog power supply;

the drain electrode of the first PMOS tube, the source electrode of the fifth PMOS tube, the grid electrode of the second PMOS tube and the drain electrode of the fifth NMOS tube are electrically connected;

the drain electrode of the second PMOS tube, the source electrode of the sixth PMOS tube, the grid electrode of the first PMOS tube and the drain electrode of the sixth NMOS tube are electrically connected;

the drain electrode of the fifth PMOS tube is electrically connected with the drain electrode of the third NMOS tube;

the drain electrode of the sixth PMOS tube and the drain electrode of the fourth NMOS tube are electrically connected with the output end;

the source electrode of the third NMOS tube, the drain electrode of the first NMOS tube and the grid electrode of the second NMOS tube are electrically connected;

the source electrode of the fourth NMOS tube, the drain electrode of the second NMOS tube and the grid electrode of the first NMOS tube are electrically connected;

the source stage of the first NMOS tube and the source stage of the second NMOS tube are electrically connected with a reference ground;

the grid electrode of the fifth NMOS tube is electrically connected with the first input end;

the grid electrode of the sixth NMOS tube is electrically connected with the second input end;

the source stage of the fifth NMOS transistor and the source stage of the sixth NMOS transistor are electrically connected with a digital ground;

the first clamping device is used for clamping the voltage of the grid electrode of the fifth PMOS tube and the voltage of the grid electrode of the sixth PMOS tube, so that the grid oxide layer of the fifth PMOS tube and the grid oxide layer of the sixth PMOS tube are not broken down;

the second clamping device is used for clamping the voltage of the grid electrode of the third NMOS tube and the voltage of the grid electrode of the fourth NMOS tube, so that the grid oxide layer of the third NMOS tube and the grid oxide layer of the fourth NMOS tube are not broken down.

Preferably, the level shifter further comprises a current backflow prevention circuit, the current backflow prevention circuit comprises a third PMOS transistor and a fourth PMOS transistor, the third PMOS transistor is connected in series between the drain electrode of the first PMOS transistor and the source stage of the fifth PMOS transistor, and the fourth PMOS transistor is connected in series between the drain electrode of the second PMOS transistor and the source stage of the sixth PMOS transistor;

the drain electrode of the third PMOS tube is electrically connected with the drain electrode of the first PMOS tube and the drain electrode of the fifth NMOS tube, and the source stage of the third PMOS tube, the source stage of the fifth PMOS tube and the grid electrode of the second PMOS tube are electrically connected;

the drain electrode of the fourth PMOS tube is electrically connected with the drain electrode of the second PMOS tube and the drain electrode of the sixth NMOS tube, and the source stage of the fourth PMOS tube, the source stage of the sixth PMOS tube and the grid electrode of the first PMOS tube are electrically connected;

the first clamping device is also used for clamping the voltage of the grid electrode of the third PMOS tube and the voltage of the grid electrode of the fourth PMOS tube, so that the grid oxide layer of the third PMOS tube and the grid oxide layer of the fourth PMOS tube are not broken down.

Preferably, the first clamping device is a first zener diode, and the second clamping device is a second zener diode;

the cathode of the first zener diode is electrically connected with the analog power supply, and the anode of the first zener diode is electrically connected with the grid electrode of the third PMOS transistor, the grid electrode of the fourth PMOS transistor, the grid electrode of the fifth PMOS transistor, the grid electrode of the sixth PMOS transistor and the reference ground;

the anode of the second Zener diode is electrically connected with the reference ground, and the cathode of the second Zener diode is electrically connected with the grid electrode of the third NMOS tube, the grid electrode of the fourth NMOS tube and the analog power supply.

Preferably, the voltage clamping circuit further comprises a first current limiting resistor and a second current limiting resistor;

the first current limiting resistor is connected between the analog power supply and the cathode of the second Zener diode in series;

the second current limiting resistor is connected in series between the reference ground and the anode of the first Zener diode.

Preferably, the level shifter further comprises a first pull-up device and a second pull-up device;

the first pull-up device is connected between the analog power supply and the source stage of the fifth PMOS tube in series;

the second pull-up device is connected between the analog power supply and the source stage of the sixth PMOS tube in series.

Preferably, the first pull-up device is a third zener diode, a cathode of the third zener diode is electrically connected to the analog power supply, and an anode of the third zener diode is electrically connected to the source of the fifth PMOS transistor;

or, the first pull-up device is a first pull-up resistor;

the second pull-up device is a fourth Zener diode, the cathode of the fourth Zener diode is electrically connected with the analog power supply, and the anode of the fourth Zener diode is electrically connected with the source of the sixth PMOS tube;

or, the second pull-up device is a second pull-up resistor.

Preferably, the level shifter further comprises a first pull-down device and a second pull-down device;

the first pull-down device is connected between the reference ground and the source stage of the third NMOS tube in series;

the second pull-down device is connected in series between the reference ground and the source stage of the fourth NMOS tube.

Preferably, the first pull-down device is a fifth zener diode, an anode of the fifth zener diode is electrically connected to the reference ground, and a cathode of the fifth zener diode is electrically connected to the source of the third NMOS transistor;

or, the first pull-down device is a first pull-down resistor;

the second pull-down device is a sixth zener diode, an anode of the sixth zener diode is electrically connected with the reference ground, and a cathode of the sixth zener diode is electrically connected with the source of the fourth NMOS transistor;

or, the second pull-down device is a second pull-down resistor.

Preferably, the first clamping device and the second clamping device are both forward conducting diodes.

Preferably, the third NMOS transistor, the fourth NMOS transistor, the fifth PMOS transistor and the sixth PMOS transistor are all LDMOS transistors.

In this scheme, the third NMOS transistor, the fourth NMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor may also be implemented by other high-voltage MOS (metal-oxide-semiconductor) transistors.

The positive progress effects of the invention are as follows:

the level shifter provided by the invention can complete level shifting with high speed and low power consumption under the condition that the ground level of the high-voltage driving signal changes, and has lower cost. The voltage clamping circuit can ensure that a 5V grid oxygen voltage-withstanding device in the traditional process works normally, can protect a grid oxide layer of a transistor device in a level shifter from being broken down, and has the function of isolating high voltage at an output end, so that most of voltage between an analog power supply and a reference ground is dropped on a drain source of the transistor in the voltage clamping circuit; zero static power consumption and level rapid turnover are realized through the latch circuit and the level turnover pull-down circuit, and the latch circuit has strong driving capability.

Furthermore, through the third PMOS tube and the fourth PMOS tube in the current backflow preventing circuit, the current path from the reference ground to the digital ground can be isolated when the fifth NMOS tube or the sixth NMOS tube is pulled down and started, the voltage from the reference ground to the digital ground is dropped on the drain sources of the third PMOS tube and the fourth PMOS tube, and large through current is prevented.

Drawings

Fig. 1 is a circuit diagram of a conventional level shifter.

Fig. 2 is a circuit diagram of a level shifter according to a preferred embodiment of the invention.

Detailed Description

The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.

As shown in fig. 2, the present embodiment provides a level shifter, which includes an output terminal OUT, a first input terminal INP, a second input terminal INN, a latch circuit 4, a level flip pull-down circuit 2, a voltage clamp circuit 1, a current backflow prevention circuit 3, a first pull-up device, a second pull-up device, a first pull-down device, and a second pull-down device.

In this embodiment, the first pull-up device, the second pull-up device, the first pull-down device and the second pull-down device are implemented by zener diodes, which correspond to the third zener diode D3, the fourth zener diode D4, the fifth zener diode D5 and the sixth zener diode D6 in fig. 2, respectively. It should be noted that, in other embodiments based on the inventive concept, the first pull-up device, the second pull-up device, the first pull-down device, and the second pull-down device may also be implemented by using pull-up resistors or pull-down resistors.

In this embodiment, the input signals of the first input terminal INP and the second input terminal INN are two complementary low-voltage logic signals.

In this embodiment, the latch circuit 4 includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, and a second NMOS transistor MN 2.

In this embodiment, the voltage clamp circuit 1 includes a first clamp device, a second clamp device, a first current limiting resistor R1, a second current limiting resistor R2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth PMOS transistor MP5, and a sixth PMOS transistor MP 6. Wherein the first clamping device and the second clamping device may be implemented with zener diodes or forward conducting diodes. In this embodiment, as shown in fig. 2, the first clamping device is implemented by a first zener diode D1, and the second clamping device is implemented by a second zener diode D2.

In this embodiment, the level flip pull-down circuit 2 includes a fifth NMOS transistor MN5 and a sixth NMOS transistor MN 6.

In this embodiment, the current backflow prevention circuit 3 includes a third PMOS transistor MP3 and a fourth PMOS transistor MP 4.

In this embodiment, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are implemented by LDNMOS transistors, the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6 are all LDPMOS transistors, and the first NMOS transistor MN1 and the second NMOS transistor MN2 are both common NMOS transistors.

In this embodiment, the source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are electrically connected to the analog power supply AVDD, respectively. The drain electrode of the first PMOS transistor MP1, the drain electrode of the third PMOS transistor MP3, and the drain electrode of the fifth NMOS transistor MN5 are electrically connected. The source of the third PMOS transistor MP3, the source of the fifth PMOS transistor MP5, the gate of the second PMOS transistor MP2, and the anode of the third zener diode D3 are electrically connected. The drain of the second PMOS transistor MP2, the drain of the fourth PMOS transistor MP4, and the drain of the sixth NMOS transistor MN6 are electrically connected. A source of the fourth PMOS transistor MP4, a source of the sixth PMOS transistor MP6, a gate of the first PMOS transistor MP1, and an anode of the fourth zener diode D4 are electrically connected.

In this embodiment, the drain of the fifth PMOS transistor MP5 is electrically connected to the drain of the third NMOS transistor MN 3; the drain of the sixth PMOS transistor MP6 and the drain of the fourth NMOS transistor MN4 are electrically connected to the output terminal OUT.

In this embodiment, the source of the third NMOS transistor MN3, the drain of the first NMOS transistor MN1, the gate of the second NMOS transistor MN2, and the cathode of the fifth zener diode D5 are electrically connected. The source of the fourth NMOS transistor MN4, the drain of the second NMOS transistor MN2, the gate of the first NMOS transistor MN1, and the cathode of the sixth zener diode are electrically connected. The source of the first NMOS transistor MN1, the source of the second NMOS transistor MN2, the anode of the fifth zener diode D5, and the anode of the sixth zener diode D6 are electrically connected to the ground SW.

In this embodiment, the gate of the fifth NMOS transistor MN5 is electrically connected to the first input terminal INP; the gate of the sixth NMOS transistor MN6 is electrically connected to the second input terminal INN. The source stage of the fifth NMOS transistor MN5 and the source stage of the sixth NMOS transistor MN6 are electrically connected to the digital DGND.

In this embodiment, the first clamp device is used to clamp the voltage of the gate of the PMOS transistor in the level shifter, so that the gate oxide of the PMOS transistor is not broken down. Specifically, the first clamp device is configured to clamp voltages of gates of the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6, so that the corresponding gate oxide layer is not broken down.

In this embodiment, the second clamp device is configured to clamp the voltage of the gate of the third NMOS transistor MN3 and the voltage of the gate of the fourth NMOS transistor MN4, so that the gate oxide of the third NMOS transistor MN3 and the gate oxide of the fourth NMOS transistor MN4 are not broken down.

In this embodiment, a cathode of the first zener diode D1 is electrically connected to the analog power supply AVDD, an anode of the first zener diode D1 is electrically connected to a gate of the third PMOS transistor MP3, a gate of the fourth PMOS transistor MP4, a gate of the fifth PMOS transistor MP5, a gate of the sixth PMOS transistor MP6, and one end of the second current-limiting resistor R2, and the other end of the second current-limiting resistor R2 is electrically connected to the ground SW. An anode of the second zener diode D2 is electrically connected to the ground SW, a cathode of the second zener diode D2 is electrically connected to the gate of the third NMOS transistor MN3, the gate of the fourth NMOS transistor MN4, and one end of the first current limiting resistor R1, and the other end of the first current limiting resistor R1 is electrically connected to the analog power supply AVDD.

In this embodiment, since the LDMOS may have leakage in an actual process, the third zener diode D3, the fourth zener diode D4, the fifth zener diode D5, and the sixth zener diode D6 added in the level shifter may provide a pull-up or pull-down path, so that the clamping functions of the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6 are normal.

In this embodiment, when the circuit normally operates, the first input terminal INP and the second input terminal INN are complementary control logic signals, the high level is less than 5V, the low level is 0V, and the difference between the analog power supply AVDD and the reference ground SW is greater than 5V. The initial state of the circuit is a reference ground SW of which the output end OUT is at a low level, the input signal of the first input end INP is suddenly changed into a high level, the second input end INN is at a low level, the high level of the first input end INP opens the fifth NMOS tube MN5 to provide a low-resistance path to the digital ground DGND, the low level of the second input end INN closes the sixth NMOS tube MN6, and the sixth NMOS tube MN6 outputs a high-resistance state. The opened fifth NMOS transistor MN5 pulls the drain of the first PMOS transistor MP1 low to digital DGND. When the third PMOS transistor MP3 is used as a pass gate, it can transmit high voltage without loss, but its transmit low voltage is limited by the gate voltage, so the source voltages of the fifth PMOS transistor MP5 and the third PMOS transistor MP3 are clamped at the difference between the analog power supplies AVDD and VD1, where VD1 is the voltage drop of the first zener diode D1. At this time, the third PMOS transistor MP3 pulls down the source potential of the fifth PMOS transistor MP5 until the source potential of the fifth PMOS transistor MP5 is pulled down to AVDD-VD1+ VTMP5, and VTMP5 is the sub-threshold turn-on voltage of the fifth PMOS transistor MP 5. Since the source of the fifth PMOS transistor MP5 is connected to the gate of the second PMOS transistor MP2, the second PMOS transistor MP2 starts the positive feedback loop formed by the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 when the voltage of the source of the fifth PMOS transistor MP5 drops to a voltage lower than the threshold voltage of the second PMOS transistor MP 2. Meanwhile, positive feedback loops of the first NMOS transistor MN1 and the second NMOS transistor MN2 are also opened, the two positive feedback loops accelerate the turnover of output voltage, so that the output voltage obtains a stable high level, finally, the clamping circuit clamps the grid potential of the second NMOS transistor MN2 at VD2-VTMN2, VD2 is the voltage drop of a second Zener diode D2, and VTMN2 is the sub-threshold breakover voltage of the second NMOS transistor MN 2. When the first input terminal INP is at a low level and the second input terminal INN is at a high level, the working principle is the same, and the description thereof is omitted. The combination of the latch circuit and the level-reversal pull-down circuit adopted in the embodiment can realize zero static power consumption and level rapid reversal, and has strong driving capability. The voltage clamping circuit and the special topological structure of the circuit enable the circuit to complete level conversion at high-voltage and low-level changing signals.

The level shifter provided by the embodiment can isolate the current path from the reference ground to the digital ground when the fifth NMOS transistor or the sixth NMOS transistor is pulled down and started through the third PMOS transistor and the fourth PMOS transistor in the current backflow preventing circuit, drop the voltage from the reference ground to the digital ground on the drain sources of the third PMOS transistor and the fourth PMOS transistor, and prevent large through current.

The level shifter provided by the embodiment can complete level shifting with high speed and low power consumption under the condition that the ground level of the high-voltage driving signal changes, and is low in cost. The voltage clamping circuit can ensure that a 5V grid oxygen voltage-withstanding device in the traditional process works normally, can protect a grid oxide layer of a transistor device in a level shifter from being broken down, and has the function of isolating high voltage at an output end, so that most of voltage between an analog power supply and a reference ground is dropped on a drain source of the transistor in the voltage clamping circuit; zero static power consumption and level rapid turnover are realized through the latch circuit and the level turnover pull-down circuit, and the latch circuit has strong driving capability.

While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.

Claims

1. A level shifter comprises an output end, a first input end and a second input end, wherein input signals of the first input end and the second input end are two complementary low-voltage logic signals, and the level shifter is characterized by further comprising a latch circuit, a level overturning pull-down circuit and a voltage clamping circuit;

the latch circuit comprises a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube;

2. The level shifter of claim 1, further comprising a current backflow prevention circuit comprising a third PMOS transistor connected in series between the drain of the first PMOS transistor and the source of the fifth PMOS transistor, and a fourth PMOS transistor connected in series between the drain of the second PMOS transistor and the source of the sixth PMOS transistor;

the drain electrode of the fourth PMOS tube is electrically connected with the drain electrode of the second PMOS tube and the drain electrode of the sixth NMOS tube, and the source electrode of the fourth PMOS tube, the source electrode of the sixth PMOS tube and the grid electrode of the first PMOS tube are electrically connected;

3. The level shifter of claim 2, wherein the first clamping device is a first zener diode and the second clamping device is a second zener diode;

4. The level shifter of claim 3, wherein the voltage clamp circuit further comprises a first current limiting resistor and a second current limiting resistor;

5. The level shifter of claim 2, wherein the level shifter further comprises a first pull-up device and a second pull-up device;

6. The level shifter of claim 5,

the first pull-up device is a third Zener diode, the cathode of the third Zener diode is electrically connected with the analog power supply, and the anode of the third Zener diode is electrically connected with the source of the fifth PMOS tube;

or, the first pull-up device is a first pull-up resistor;

or, the second pull-up device is a second pull-up resistor.

7. The level shifter of claim 2, wherein the level shifter further comprises a first pull-down device and a second pull-down device;

8. The level shifter of claim 7,

the first pull-down device is a fifth Zener diode, the anode of the fifth Zener diode is electrically connected with the reference ground, and the cathode of the fifth Zener diode is electrically connected with the source of the third NMOS tube;

or, the first pull-down device is a first pull-down resistor;

or, the second pull-down device is a second pull-down resistor.

9. The level shifter of claim 1 or 2, wherein the first clamping device and the second clamping device are both forward conducting diodes.

10. The level shifter of claim 1, wherein the third NMOS transistor, the fourth NMOS transistor, the fifth PMOS transistor and the sixth PMOS transistor are LDMOS transistors.