CN203193605U - A driving circuit used for driving a high-voltage device - Google Patents
A driving circuit used for driving a high-voltage device Download PDFInfo
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- CN203193605U CN203193605U CN 201220666590 CN201220666590U CN203193605U CN 203193605 U CN203193605 U CN 203193605U CN 201220666590 CN201220666590 CN 201220666590 CN 201220666590 U CN201220666590 U CN 201220666590U CN 203193605 U CN203193605 U CN 203193605U
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Abstract
The utility model provides a driving circuit used for driving a high-voltage device. The driving circuit comprises a voltage-regulator diode, a high-voltage PMOS transistor, a level converter, and a low-voltage driving circuit. The cathode of the voltage-regulator diode is connected with high-voltage supplying voltage, while the anode of the voltage-regulator diode is connected with a ground potential in a low voltage domain through a resistor. The grid electrode of the high-voltage PMOS transistor is connected with the anode of the resistor. The drain electrode of the high-voltage PMOS transistor is connected with the ground potential in the low voltage domain. The source electrode of the high-voltage PMOS transistor can be manipulated in order to provide a ground potential in a high voltage domain. The level converter can be manipulated in order to convert a received first signal in the low voltage domain into a second signal in the high voltage domain and output the second signal. The low-voltage driving circuit can be manipulated in order to receive the second signal and adapts the second signal to a third signal capable of driving the high-voltage device. The driving circuit enables a low-voltage to drive the high-voltage device and achieves the driving of the high-voltage device by using a simple and effective mode.
Description
Technical field
Embodiment of the present utility model relates generally to the technical field of design of electronic circuits, drives the drive circuit of high tension apparatus in particular to level shifting circuit and use low-voltage device.
Background technology
Semiconductor device such as traditional transistor, CMOS are generally operational under the low pressure (that is, differing 5 volts between high-voltage signal level and the low-voltage signal level)., the characteristics of such low-voltage device are high speed, low-power consumption and low heat dissipation.But in design of electronic products of new generation, low voltage transistor or CMOS level no longer occupy the dominant position of logical circuit.The manufacturer of semiconductor device released thereupon can high pressure (that is, the voltage difference between high-voltage signal level and the low-voltage signal level is greater than 5 volts) down can operate as normal semiconductor device.Though this high tension apparatus has greatly satisfied application demand many times, to compare with low-voltage device, its unfavorable aspect is to manufacture and design complexity, cost high, low speed, high power consumption and high heat dissipation etc.
On the other hand, semiconductor device such as high-voltage CMOS must need higher voltage (as greater than 5V) to drive, and this requires driving stage to be constructed by the device that can bear higher voltage, certainly will increase the size of integrated circuit, increased cost, also higher to the requirement of heat radiation simultaneously.
The utility model content
One of the purpose of this utility model is to provide a kind of low-voltage device that uses to control the scheme of high tension apparatus at the signal of low-pressure region.
According to an aspect of the present utility model, provide a kind of for the drive circuit that drives high tension apparatus, comprising: voltage stabilizing didoe, its negative electrode is connected to high voltage supply voltage, and its anode is connected to the earth potential of low voltage domain through resistor; High voltage PMOS transistor, its grid is connected with the anode of resistor, and its drain electrode is connected to the earth potential of low voltage domain, and its source electrode can operate to provide the earth potential of high voltage domain; Level translator, its operating voltage end is connected to high voltage supply voltage, its first earth terminal is connected to the earth potential of low voltage domain, its second earth terminal is connected to the earth potential of high voltage domain, and level translator can be operated with first signal in the low voltage domain that will receive and be converted to the secondary signal in the high voltage domain and export secondary signal; And low-voltage driving circuit, be connected between the earth potential of high voltage supply voltage and high voltage domain, can operate to receive secondary signal, and secondary signal is adapted for the 3rd signal that can drive high tension apparatus.
In an example, low-voltage driving circuit comprises: low pressure PMOS transistor and low voltage nmos transistor, their grid link together for receiving secondary signal, and their drain electrode links together be used to the 3rd signal is provided.The transistorized source electrode of low pressure PMOS is connected to high voltage supply voltage, and the source electrode of low voltage nmos transistor is connected to the earth potential of high voltage domain.
In an example, low-voltage driving circuit comprises the low-voltage operation amplifying circuit, and its input is used for receiving secondary signal, and its output is used for providing the 3rd signal.
In an example, also comprise: high voltage PMOS transistor and high pressure NMOS transistor.The transistorized source electrode of the source electrode of high voltage PMOS transistor and high pressure NMOS is connected to the earth potential of high voltage supply voltage and low voltage domain respectively; The grid of high voltage PMOS transistor is used for receiving described the 3rd signal; The transistorized grid of high pressure NMOS is used for receiving described first signal; The drain electrode of high voltage PMOS transistor and high pressure NMOS transistor drain link together be used to the 4th signal is provided.
In an example, the excursion of first signal is between 0 volt and 5 volts, and the excursion of secondary signal and the 3rd signal is between high voltage supply voltage subtracts 5 volts and high voltage supply voltage, and the excursion of the 4th signal is between 0 volt and high voltage supply voltage.
In an example, high voltage supply voltage is 100 volts or 100 volts of following arbitrary scheduled voltages.
In an example, high voltage supply voltage is in 8 volts, 12 volts, 20 volts, 24 volts, 48 volts.
In an example, level translator comprises a plurality of switch elements.
In an example, level translator comprises first inverter and second inverter of series connection, and wherein first inverter is operated between the earth potential of high voltage supply voltage and low voltage domain, is used for receiving described first signal; And wherein second inverter is operated between the earth potential of high voltage supply voltage and high voltage domain, is used for providing described secondary signal.
According to execution mode of the present utility model, owing to no longer drive and control high tension apparatus with high tension apparatus, replace low-voltage device and drive and control high tension apparatus, thereby reduced the use of circuit design mesohigh pipe, reduced size in blocks and area, make the level translator of high tension apparatus and driving stage at a high speed, low-power consumption and low heat dissipation work.
Characteristics described in specification and advantage are not all, and especially, by reference to the accompanying drawings and specification, many additional feature and advantage will will be tangible for those of ordinary skills.In addition, should be pointed out that term as used in this specification mainly is selecteed for the purpose of readable and directiveness, and may not be to be selected to describe or limit creationary technical scheme.
Description of drawings
Consider following detailed description in conjunction with the drawings, the instruction of the utility model embodiment can be understood at an easy rate.
Fig. 1 shows the drive circuit schematic diagram according to an execution mode of the utility model;
Fig. 2 is the circuit diagram of the level translator in execution mode of the utility model; And
Fig. 3 is the circuit diagram of another level translator in execution mode of the utility model.
In specification and/or in the accompanying drawings the various abbreviations that occur are defined as follows:
The CMOS complementary metal oxide semiconductors (CMOS)
The IN input
The MOSFET mos field effect transistor
(abbreviation metal-oxide-semiconductor)
NMOS N-type MOSFET
PMOS P type MOSFET
OUT output
The output of OUTs level translator
The output of OUTd driving stage
The R1 resistor
VDDH high voltage supply voltage (as high-voltage power voltage),
Or high voltage supply end
VH relatively high pressure feeder ear
VL relatively low pressure feeder ear
VSS logically
VFG floating ground voltage
The threshold voltage of Vthp semiconductor device
The reverse breakdown voltage of VZ voltage-stabiliser tube
The ZD voltage stabilizing didoe
LV PMOS low pressure PMOS
HV PMOS high voltage PMOS
LV NMOS low pressure NMOS
HV NMOS high pressure NMOS
MP1, MP2, MP3 PMOS pipe
MN1, MN2, MN3 NMOS pipe
Embodiment
Accompanying drawing and following description only relate to many embodiment of the present utility model by the mode of explanation.The alternative that should be noted that structure described herein and method from following discussion will be considered at an easy rate can be under the situation that does not break away from the utility model principle and the feasible alternative that is used.
Now will be in detail with reference to some embodiment of the present utility model, its example shown in the drawings.Should be noted that as long as feasible, can use similar or identical Reference numeral in the accompanying drawings, and they can be in order to indicate or identical functions similar.Accompanying drawing is only described some embodiment of the present utility model for purposes of illustration.Those skilled in the art will be easy to recognize from the following description that herein the alternative of the structure of explanation and method can be under the situation of the principle that does not break away from embodiment described herein and be used.As long as feasible, method step described below may not be carried out by illustrated order.
As example, in the following description, the voltage range that the voltage difference of signal amplitude between high-voltage signal level and low-voltage signal level is less than or equal to 5 volts is called low voltage domain, namely 0 volt-5 volts.To in such voltage domain, be called low-voltage device by the device of operate as normal.The voltage difference of signal amplitude between high-voltage signal level and low-voltage signal level is called high voltage domain greater than 5 volts voltage range, will in such voltage domain, be called high tension apparatus by the device of operate as normal.
Fig. 1 shows the drive circuit schematic diagram according to an execution mode of the utility model.This exemplary circuit comprises level translator 110, driving stage 120 and output stage.Output stage comprises high voltage PMOS pipe 160 and high pressure NMOS pipe 170.
Floating ground voltage produces level and comprises voltage stabilizing didoe ZD130, resistor R1 140 and high voltage PMOS pipe MP3 150.The negative electrode of voltage stabilizing didoe ZD is connected to its anode of high voltage supply end VDDH by resistor R1 ground connection VSS.The anode of voltage stabilizing didoe ZD is connected to the grid of high voltage PMOS pipe MP3, the grounded drain VSS of high voltage PMOS pipe MP3, and the source electrode of high voltage PMOS pipe MP3 can operate to provide the earth potential of above-mentioned high voltage domain.
In the course of work of the principle electrical circuit figure of the utility model embodiment illustrated in fig. 1, the voltage of high voltage supply end VDDH (perhaps power end) is greater than the reverse breakdown voltage VZ of voltage stabilizing didoe ZD, the A voltage VA of ordering then, namely, voltage Vgd between the grid of high voltage PMOS pipe MP3 and the drain electrode is VDDH-VZ, so not conducting of MP3, then the voltage of the source electrode of MP3 (be the voltage that the B among Fig. 1 is ordered, can be designated floating ground voltage VFD) is
VFG＝VDDH-VZ-Vthp，
Wherein VFG represents described floating ground voltage, and VDDH represents high voltage supply voltage, and VZ represents the reverse breakdown voltage of described voltage stabilizing didoe, and Vthp represents the threshold voltage of described high voltage PMOS pipe.According to the characteristic of CMOS pipe, Vthp equals the drain electrode of metal-oxide-semiconductor and the voltage Vds between the source electrode.
According to an embodiment of the present utility model, voltage stabilizing didoe ZD is chosen for its reverse breakdown voltage VZ usually and equals about 6 volts, and the threshold voltage of metal-oxide-semiconductor is generally-1 volt, then floating ground voltage V
FG=VDDH-Vz-Vthp=VDDH-5 volt.
According to an embodiment of the present utility model, the voltage of high voltage supply end VDDH is chosen for 20 volts, the floating ground voltage V that then obtains
FGBe about 15V.Replacedly, the supply voltage VDDH of the utility model embodiment can also be chosen as 8V, 12V, 24V, 36V, 48V etc., even also is feasible up to 100V.Replacedly, also can choose its reverse breakdown voltage is other values outside the 6V.
According to embodiment of the present utility model, resistor R1 chooses voltage-current characteristic according to voltage stabilizing didoe, chooses suitable resistor R1 and makes that the stabilized voltage characteristic of voltage stabilizing didoe ZD is better.
According to an embodiment of the present utility model, floating ground voltage produces the earth potential that level can produce the high voltage domain of VDDH-5 volt.
Should be appreciated that above-mentioned first signal 101 both can be that digital signal also can be analog signal; Correspondingly, above-mentioned secondary signal 102 also can be digital signal or analog signal.
According to an embodiment of the present utility model, first signal 101 be low voltage domain earth potential (as, 0V) during signal, the earth potential signal in level translator 110 output HIGH voltage territories (in an example, being 15V) is as secondary signal 102; First signal 101 be low voltage domain high potential (as, 5V) during signal, the high potential signal in level translator 110 output HIGH voltage territories (in an example, being 20V) is as secondary signal 102.
According to another embodiment of the present utility model, first signal 101 be low voltage domain earth potential (as, 0V) with the high potential of low voltage domain (as, during the signal that changes 5V), level translator 110 output at the earth potential signal of high voltage domain (in an example, be 15V) with the high potential signal (in an example, being 20V) of high voltage domain between the signal that changes as secondary signal 102.
Though above-described embodiment is that the low voltage domain with 5V is that example describes, and it will be appreciated by those skilled in the art that low voltage domain and high voltage domain are relative concepts.5 volts low voltage domain only is exemplary in above-described embodiment.Scheme of the present utility model will be adapted to 1.8 volts voltage domain, 6V voltage domain, 10 volts voltage domain, 24V voltage domain, etc.
Fig. 1 also illustrates driving stage 120 and output stage.In this example, driving stage 120 comprises low pressure PMOS pipe MP1 and the low pressure NMOS pipe MN1 that is cascaded.Low pressure PMOS pipe MP1 and low pressure NMOS pipe MN1 are complementary, that is, during one of them conducting, another ends, and vice versa.The grid of low pressure PMOS pipe MP1 and low pressure NMOS pipe MN1 can operate to receive described secondary signal 102 with the output that is connected to level translator 110.The source electrode of low pressure PMOS pipe MP1 is connected to high pressure supply voltage VDDH.The source electrode of low pressure NMOS pipe MN1 is connected to the earth potential of aforesaid high voltage domain, that is, and and floating ground VFG.The drain electrode of low pressure PMOS pipe MP1 and low pressure NMOS pipe MN1 links together be used to the 3rd signal 103 is provided.Like this, driving stage 120 is adapted for secondary signal 102 the 3rd signal 103 that can drive high tension apparatus.
In another example, driver 120 comprises a low voltage operational amplifier (or circuit), it is operated between the earth potential in aforementioned high voltage supply voltage and high pressure territory, be used for secondary signal 102 is enlarged into the 3rd signal 103, in order to drive high tension apparatus (as, the high-voltage MOS pipe 160 that comprises in the output stage) with enough power.
Fig. 1 also shows an optional output stage.This output stage comprises: the high voltage PMOS transistor 160 of series connection and high pressure NMOS transistor 170; The source electrode of the source electrode of high voltage PMOS transistor 160 and high pressure NMOS transistor 170 is connected to the earth potential VSS of high voltage supply voltage VDDH and low voltage domain respectively; The grid of high voltage PMOS transistor 160 is used for receiving the 3rd signal 103, the grid of high pressure NMOS transistor 170 is used for receiving first signal 101, and the drain electrode of the drain electrode of high voltage PMOS transistor 160 and high pressure NMOS transistor 170 links together be used to the 4th signal 104 is provided.
In last example, the PMOS that is cascaded pipe and NMOS pipe are that complementary (that is, during a metal-oxide-semiconductor conducting, another metal-oxide-semiconductor ends; Vice versa), so drive circuit shown in Figure 1 can be realized following function.
First signal 101 be low voltage domain earth potential (as, 0V) during signal, the 4th signal 104 also is that the earth potential of low voltage domain is (as, 0V) signal.First signal 101 be low voltage domain high potential (as, 5V) during signal, 104 of the 4th signals are that the high potential of high voltage domain is (as, 20V) signal.
First signal 101 the earth potential of low voltage domain (as, 0V) and the high potential of low voltage domain (as, when changing between 5V), 104 earth potentials at low voltage domain of the 4th signal (as, 0V) high potential of signal and high voltage domain (as, change between 20V).
By as seen above-mentioned, though the output stage of the utility model embodiment works in high voltage domain, its operating voltage range can be from VSS to VDDH (for example, 0V-20V), can adopt low device (as, low pressure metal-oxide-semiconductor, low voltage operational amplifier) realize driving stage.Compare high tension apparatus, embodiment of the present utility model has reduced the quantity of high tension apparatus, thereby has saved chip size and area, has reduced cost.
Fig. 2 is the circuit diagram of the level translator in execution mode of the utility model.As shown in Figure 2, level translator 110 comprises first inverter 210 and second inverter 202 of series connection, and wherein first inverter 201 is operated between the earth potential VSS of high voltage supply voltage VDDH and low voltage domain, is used for receiving first signal 101; Second inverter 202 is operated in earth potential (that is previously described VFD, of high voltage supply voltage VDDH and high voltage domain; As, VDDH-5V) between, be used for providing secondary signal 102.
Fig. 3 is the circuit diagram of another level translator in execution mode of the utility model.As shown in Figure 3, level translator 110 comprises a plurality of switch elements (such as, M1 to M8).As shown in Figure 3, terminal IN_L is used for receiving first signal 101 of Fig. 1, terminal V
SSLBe used for being connected to the VSS of Fig. 1, terminal V
DDHBe used for being connected to the VDDH of Fig. 1, terminal OUT_H is used for the secondary signal 102 of output map 1.Terminal V
DDLOn voltage can be from terminal V
DDHOn the voltage dividing potential drop obtain.
Such level translator should be appreciated that except Fig. 2 and level translator 110 shown in Figure 3, can adopt any suitable level translator in this area, as long as can be converted to first signal 101 among Fig. 1 the secondary signal 102 among Fig. 1.
In other execution mode, provide a kind of for the method that drives high tension apparatus.This method comprises:
Utilize voltage stabilizing didoe 130, high voltage PMOS transistor 150 and resistor 140 that the earth potential VFG of a high voltage domain is provided, the negative electrode of middle voltage stabilizing didoe 130 is connected to high voltage supply voltage VDDH, its anode is connected to the earth potential VSS of low voltage domain through resistor 140, and wherein the grid of high voltage PMOS transistor 150 is connected with the anode of resistor 140, its drain electrode is connected to the earth potential VSS of low voltage domain, and its source electrode can operate to provide the earth potential VFG of high voltage domain;
Utilize level translator 110 that first signal 101 in the low voltage domain of receiving is converted to secondary signal 102 in the high voltage domain, wherein the operating voltage end of level translator 110 is connected to high voltage supply voltage VDDH, its first earth terminal is connected to the earth potential VSS of low voltage domain, and its second earth terminal is connected to the earth potential VFG of high voltage domain; And
Utilize low-voltage driving circuit 120 secondary signal 102 to be adapted for the 3rd signal 103 that can drive high tension apparatus.
In an example, low-voltage driving circuit 120 comprises: low pressure PMOS transistor and low voltage nmos transistor, their grid links together for receiving secondary signal 102, their drain electrode links together be used to the 3rd signal 103 is provided, the transistorized source electrode of low pressure PMOS is connected to high voltage supply voltage VDDH, and the source electrode of low voltage nmos transistor is connected to the earth potential VFG of high voltage domain.
In an example, low-voltage driving circuit 120 comprises the low-voltage operation amplifying circuit, and its input is used for receiving secondary signal 102, and its output is used for providing the 3rd signal 103.
In an example, this method also comprises: utilize series connection high voltage PMOS transistor 160 and high pressure NMOS transistor 170, provide the 4th signal 104 based on first signal 101 and the 3rd signal 103.The source electrode of the source electrode of high voltage PMOS transistor 160 and high pressure NMOS transistor 170 is connected to the earth potential VSS of high voltage supply voltage VDDH and low voltage domain respectively; The grid of high voltage PMOS transistor 160 is used for receiving the 3rd signal 103; The grid of high pressure NMOS transistor 170 is used for receiving described first signal 101; The drain electrode of the drain electrode of high voltage PMOS transistor 160 and high pressure NMOS transistor 170 links together be used to the 4th signal 104 is provided.
In an example, the excursion of first signal 101 is between 0 volt and 5 volts, the excursion of secondary signal 102 and the 3rd signal 103 is between high voltage supply voltage VDDH subtracts 5 volts and high voltage supply voltage VDDH, and the excursion of the 4th signal 104 is between 0 volt and high voltage supply voltage VDDH.
In an example, wherein high voltage supply voltage VDDH is 100 volts or 100 volts of following arbitrary scheduled voltages.
Therefore, though have illustrated and described some embodiment of the present utility model and application, but should be appreciated that, the utility model is not limited to precision architecture and the assembly of content described herein, and will be that apparent various modification, change and variation can made aspect layout, operation and the details of method and apparatus described herein to those skilled in the art, and can not deviate from spirit and scope of the present utility model.
Claims (9)
1. a drive circuit that is used for driving high tension apparatus is characterized in that, comprising:
Voltage stabilizing didoe, its negative electrode is connected to high voltage supply voltage, and its anode is connected to the earth potential of low voltage domain through resistor;
High voltage PMOS transistor, its grid is connected with the anode of described resistor, and its drain electrode is connected to the earth potential of described low voltage domain, and its source electrode can operate to provide the earth potential of high voltage domain;
Level translator, its operating voltage end is connected to described high voltage supply voltage, its first earth terminal is connected to the earth potential of described low voltage domain, its second earth terminal is connected to the earth potential of described high voltage domain, and described level translator can be operated with first signal in the low voltage domain that will receive and be converted to the secondary signal in the high voltage domain and export described secondary signal; And
Low-voltage driving circuit is connected between the earth potential of described high voltage supply voltage and described high voltage domain, can operate to receive described secondary signal, and described secondary signal is adapted for the 3rd signal that can drive high tension apparatus.
2. drive circuit according to claim 1, it is characterized in that, wherein said low-voltage driving circuit comprises: low pressure PMOS transistor and low voltage nmos transistor, their grid links together for receiving described secondary signal, their drain electrode links together be used to described the 3rd signal is provided, the transistorized source electrode of described low pressure PMOS is connected to described high voltage supply voltage, and the source electrode of described low voltage nmos transistor is connected to the earth potential of described high voltage domain.
3. drive circuit according to claim 1 is characterized in that, wherein said low-voltage driving circuit comprises the low-voltage operation amplifying circuit, and its input is used for receiving described secondary signal, and its output is used for providing described the 3rd signal.
4. according to claim 2 or 3 described drive circuits, it is characterized in that, also comprise: high voltage PMOS transistor and high pressure NMOS transistor, the source electrode of described high voltage PMOS transistor and the transistorized source electrode of described high pressure NMOS are connected to the earth potential of described high voltage supply voltage and described low voltage domain respectively, the grid of described high voltage PMOS transistor is used for receiving described the 3rd signal, the transistorized grid of described high pressure NMOS is used for receiving described first signal, and the drain electrode of described high voltage PMOS transistor and described high pressure NMOS transistor drain link together be used to the 4th signal is provided.
5. drive circuit according to claim 4, it is characterized in that, the excursion of wherein said first signal is between 0 volt and 5 volts, the excursion of described secondary signal and described the 3rd signal is between described high voltage supply voltage subtracts 5 volts and described high voltage supply voltage, and the excursion of described the 4th signal is between 0 volt and described high voltage supply voltage.
6. according to each described drive circuit among the claim 1-3, it is characterized in that wherein said high voltage supply voltage is 100 volts or 100 volts of following arbitrary scheduled voltages.
7. drive circuit according to claim 6 is characterized in that, wherein said high voltage supply voltage is in 8 volts, 12 volts, 20 volts, 24 volts, 48 volts.
8. drive circuit according to claim 1 is characterized in that, described level translator comprises a plurality of switch elements.
9. drive circuit according to claim 1, it is characterized in that, described level translator comprises first inverter and second inverter of series connection, and wherein said first inverter is operated between the earth potential of described high voltage supply voltage and described low voltage domain, is used for receiving described first signal; And wherein said second inverter is operated between the earth potential of described high voltage supply voltage and described high voltage domain, is used for providing described secondary signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201220666590 CN203193605U (en) | 2012-12-05 | 2012-12-05 | A driving circuit used for driving a high-voltage device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201220666590 CN203193605U (en) | 2012-12-05 | 2012-12-05 | A driving circuit used for driving a high-voltage device |
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| CN203193605U true CN203193605U (en) | 2013-09-11 |
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| CN 201220666590 Withdrawn - After Issue CN203193605U (en) | 2012-12-05 | 2012-12-05 | A driving circuit used for driving a high-voltage device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103856205A (en) * | 2012-12-05 | 2014-06-11 | 艾尔瓦特集成电路科技（天津）有限公司 | Level switching circuit, drive circuit for driving high voltage devices and corresponding method |
| CN112383298A (en) * | 2021-01-18 | 2021-02-19 | 灿芯半导体(上海)有限公司 | DDR (double data Rate) sending circuit |
| CN112491408A (en) * | 2019-09-11 | 2021-03-12 | 成都锐成芯微科技股份有限公司 | Level conversion circuit |
-
2012
- 2012-12-05 CN CN 201220666590 patent/CN203193605U/en not_active Withdrawn - After Issue
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103856205A (en) * | 2012-12-05 | 2014-06-11 | 艾尔瓦特集成电路科技（天津）有限公司 | Level switching circuit, drive circuit for driving high voltage devices and corresponding method |
| CN103856205B (en) * | 2012-12-05 | 2016-04-20 | 艾尔瓦特集成电路科技（天津）有限公司 | Level shifting circuit, for driving the drive circuit of high tension apparatus and corresponding method |
| CN112491408A (en) * | 2019-09-11 | 2021-03-12 | 成都锐成芯微科技股份有限公司 | Level conversion circuit |
| CN112491408B (en) * | 2019-09-11 | 2022-07-29 | 成都锐成芯微科技股份有限公司 | Level conversion circuit |
| CN112383298A (en) * | 2021-01-18 | 2021-02-19 | 灿芯半导体(上海)有限公司 | DDR (double data Rate) sending circuit |
| CN112383298B (en) * | 2021-01-18 | 2021-06-11 | 灿芯半导体(上海)股份有限公司 | DDR (double data Rate) sending circuit |
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