CN111294042B

CN111294042B - Level shift circuit

Info

Publication number: CN111294042B
Application number: CN202010093349.XA
Authority: CN
Inventors: 黄明永
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2020-02-14
Filing date: 2020-02-14
Publication date: 2023-07-18
Anticipated expiration: 2040-02-14
Also published as: CN111294042A

Abstract

The invention provides a level shift circuit, which comprises a latch unit, a driving unit, a conversion unit and an input unit, wherein the conversion unit comprises a fifth PMOS transistor, a sixth PMOS transistor, a third NMOS transistor and a fourth NMOS transistor, the input unit comprises a seventh PMOS transistor, an eighth PMOS transistor, a fifth NMOS transistor and a sixth NMOS transistor, when the first signal is a zero-voltage low-level signal, the input voltage of the driving unit (namely, the grid voltage of the third PMOS transistor) is a negative value of the first power supply end voltage, the first power supply end voltage of the third PMOS transistor, of which the voltage between the grid and the source is twice, is greatly higher than the threshold starting voltage of the third PMOS transistor, the driving capability of the third PMOS transistor and the working speed of the level shift circuit are improved, the current of the third PMOS transistor is reduced, and when the first signal is a positive-voltage high-level signal, the input voltage of the driving unit (namely, the grid voltage of the third PMOS transistor) is the first power supply end voltage, and the third PMOS transistor is turned off.

Description

Level shift circuit

Technical Field

The present invention relates to the field of semiconductor technologies, and in particular, to a level shift circuit.

Background

The level shift circuit converts the low-voltage control signal into a high-voltage control signal, and realizes the control of the low-voltage logic on the high-voltage power output stage. In general, the level shift circuit may be classified into a negative voltage level shift circuit and a positive voltage level shift circuit according to the polarity of an output high voltage control signal.

Fig. 1 and 2 are circuit diagrams of a conventional negative voltage level shift circuit and a conventional positive voltage level shift circuit, respectively. Referring to fig. 1, the negative voltage level shift circuit includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a first NMOS transistor N1, and a second NMOS transistor N2. The source electrode of the first PMOS transistor P1 is connected to the substrate and serves as a first power supply terminal V1, the drain electrode is connected to the drain electrode of the first NMOS transistor N1 and serves as a first output terminal out1 of the negative voltage level shift circuit, and the gate electrode is connected to the gate electrode of the first NMOS transistor N1 and serves as a second output terminal out2 of the negative voltage level shift circuit. The source and the substrate of the second PMOS transistor P2 are connected to the first power supply terminal V1, the drain is connected to the drain of the second NMOS transistor N2 and to the second output terminal out2, and the gate is connected to the gate of the second NMOS transistor N2 and to the first output terminal out1. The gate of the third PMOS transistor P3 is the first signal terminal S1 of the negative voltage level shift circuit, the source is the third power terminal V3, the drain is connected to the drain of the first PMOS transistor P1, and the substrate is connected to the first power terminal V1. The gate of the fourth PMOS transistor P4 is the second signal terminal S2 of the negative voltage level shift circuit, the source is connected to the third power terminal V3, the drain is connected to the drain of the second PMOS transistor P2, and the substrate is connected to the first power terminal V1. The source electrode of the first NMOS transistor N1 is connected with the substrate and is used as a second power supply terminal V2; the source of the second NMOS transistor N2 is connected to the substrate and to the second power supply terminal V2.

When the negative pressure level shift circuit is used for carrying out negative pressure level shift, firstly, setting operation is carried out: applying a first signal to the first signal terminal S1, applying a second signal to the second signal terminal S2, applying a first voltage to the first power terminal V1, applying a second voltage to the second power terminal V2, and applying a third voltage to the third power terminal V3, wherein the voltage value of the second voltage is smaller than the voltage value of the first voltage, and the voltage value of the third voltage is equal to the voltage value of the first voltage. Typically, the first voltage is a power supply voltage, the voltage value is 1.2V, 1.5V or 1.8V, the second voltage is a ground voltage, and the voltage value is 0V. The first signal may be a positive-pressure high-level signal "1" or a zero-pressure low-level signal "0", and correspondingly, the second signal is a zero-pressure low-level signal "0" or a positive-pressure high-level signal "1". The positive voltage high level signal '1' is a power supply voltage signal with the amplitude of 1.2V, 1.5V or 1.8V, the zero voltage low level signal '0' is a ground voltage signal with the amplitude of 0V. Assuming that the first signal is a positive-voltage high-level signal "1", the second signal is a zero-voltage low-level signal "0", under the control of the high-low level, the third PMOS transistor P3 is turned off, the fourth PMOS transistor P4 is turned on, the gate of the first NMOS transistor N1 is pulled to a high potential, the first NMOS transistor N1 is turned on, and the first output terminal out1 latches the voltage value of the second voltage; at the same time, the gate of the second PMOS transistor P2 is pulled to a low potential, the second PMOS transistor is turned on, the second output terminal out2 latches the voltage value of the first voltage, and the setting is completed. After the setting is completed, the first signal and the second signal are kept to be input into the first signal end S1 and the second signal end S2, namely, the first signal is kept to be a positive-voltage high-level signal '1' to be input into the first signal end S1, the second signal is kept to be a zero-voltage low-level signal '0' to be input into the second signal end S2, the voltage value of the second voltage is reduced, namely, the voltage value of the second voltage is changed from 0V to negative voltage, and the voltage output by the first output end out1 is changed in the same way as the second voltage. When the second voltage decreases to a predetermined value required to be output by the first output terminal out1, the negative voltage level shift is completed. The predetermined value required by the first output terminal out1 is a voltage value set according to actual requirements. In the process of reducing the second voltage, the voltage difference between the source and drain of the first PMOS transistor P1, the third PMOS transistor P3, and the second NMOS transistor N2 is continuously increased, and the transistor may be damaged when the voltage difference between the source and drain is excessive. Similarly, when the first signal is zero voltage low level signal "0" and the second signal is positive voltage high level signal "1", the second output terminal out2 outputs the required negative voltage. Referring to fig. 2, the positive voltage level shift circuit includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4, and further includes a first signal terminal S1, a second signal terminal S2, a first power terminal V1, a second power terminal V2, and a third power terminal V3. The specific connection relationship between each device and the port of the positive-voltage level shift circuit is shown in fig. 2, and the working principle is similar to that of the negative-voltage level shift circuit shown in fig. 1, and will not be repeated here.

Flash IP is designed on the 55nm process, and a voltage of-0.4V is used in a decoding circuit, so that the second voltage is required to be reduced to-0.4V. As the process becomes more advanced and the power supply voltage becomes lower, the power supply voltage is as low as 1.2V in the 55nm process, and a margin is left in the design, even considering the situation that the power supply voltage is 1.05V to 1.35V. Since the voltage difference between the four poles D, G, S, and B of the PMOS transistor and the NMOS transistor is 1.75V at maximum, the PMOS transistor and the NMOS transistor with rated withstand voltage of 1.2V cannot be selected. In consideration of the demand of cost reduction, the number of devices is reduced, and a level shift circuit in 55nm adopts a PMOS transistor and an NMOS transistor with rated withstand voltage of 5V, but threshold starting voltages of the PMOS transistor and the NMOS transistor with rated withstand voltage of 5V are higher than 0.8V or lower than-0.8V at low temperature. When the power supply voltage of the level shift circuit is 1.05V, the first signal is 0V, the inter-gate-source voltage of the third PMOS transistor P3 is 1.05V, the threshold on voltage is close to the threshold on voltage, the on condition of the third PMOS transistor P3 is just met, at this time, the driving capability of the third PMOS transistor P3 is weak, the level shift operation is slow, and the current of the third PMOS transistor P3 is large.

Disclosure of Invention

The invention aims to provide a level shift circuit to solve the problems of insufficient driving capability and low working speed caused by the insufficient driving capability of the conventional level shift circuit.

In order to solve the above technical problems, the present invention provides a level shift circuit, which includes a conversion unit, an input unit, a driving unit, and a latch unit, wherein:

the conversion unit comprises a fifth PMOS transistor, a sixth PMOS transistor, a third NMOS transistor and a fourth NMOS transistor; the grid electrode of the fifth PMOS transistor is connected with the grid electrode of the third NMOS transistor as a first signal end, the source electrode of the fifth PMOS transistor is connected with a first power supply end, and the drain electrode of the fifth PMOS transistor is connected with the drain electrode of the third NMOS transistor; the grid electrode of the sixth PMOS transistor is connected with the grid electrode of the fourth NMOS transistor as a second signal end, the source electrode of the sixth PMOS transistor is connected with the first power supply end, and the drain electrode of the sixth PMOS transistor is connected with the drain electrode of the fourth NMOS transistor;

the input unit includes a seventh PMOS transistor, an eighth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; the grid electrode of the fifth NMOS transistor is connected with the drain electrode of the fifth PMOS transistor, the source electrode of the fifth NMOS transistor is connected with the source electrode of the third NMOS transistor, and the drain electrode of the fifth NMOS transistor is connected with the second power supply end; the grid electrode of the sixth NMOS transistor is connected with the drain electrode of the sixth PMOS transistor, the source electrode of the sixth NMOS transistor is connected with the source electrode of the fourth NMOS transistor, and the drain electrode of the sixth NMOS transistor is connected with the second power supply end; a gate of the seventh PMOS transistor is connected to a source of the fifth NMOS transistor, and a source and a drain of the seventh PMOS transistor are connected to the driving unit; a gate of the eighth PMOS transistor is connected to a source of the sixth NMOS transistor, and a source and a drain of the eighth PMOS transistor are connected to the driving unit;

the driving unit is used for driving the latch unit to latch according to signals provided by the seventh PMOS transistor and the eighth PMOS transistor;

the latch unit is used for latching according to the signal provided by the drive unit and outputting a predetermined value of the required output of the latch.

Optionally, in the level shift circuit, the latch unit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; the source electrode of the first PMOS transistor is connected with the source electrode of the second PMOS transistor and is used as a first power supply end, the drain electrode of the first PMOS transistor is connected with the drain electrode of the first NMOS transistor and is used as a first output end of the level shift circuit, and the grid electrode of the first PMOS transistor is connected with the grid electrode of the first NMOS transistor and is used as a second output end of the level shift circuit; the drain electrode of the second PMOS transistor is connected with the drain electrode of the second NMOS transistor and is connected to the second output end, and the grid electrode of the second PMOS transistor is connected with the grid electrode of the second NMOS transistor and is connected to the first output end; the source electrodes of the first NMOS transistor and the second NMOS transistor are connected and serve as a second power supply end;

the driving unit comprises a third PMOS transistor and a fourth PMOS transistor; the source electrode of the third PMOS transistor is connected to the first power supply end, the drain electrode of the third PMOS transistor is connected to the first output end, and the grid electrode of the third PMOS transistor is connected to the source electrode and the drain electrode of the seventh PMOS transistor; the source of the fourth PMOS transistor is connected to the first power supply terminal, the drain of the fourth PMOS transistor is connected to the second output terminal, and the gate of the fourth PMOS transistor is connected to the source and drain of the eighth PMOS transistor.

Optionally, in the level shift circuit, the first signal end is used for applying a first signal, and the second signal end is used for applying a second signal, where the first signal is a zero voltage low level signal, and the second signal is a positive voltage high level signal.

Optionally, in the level shift circuit, the first power supply terminal is configured to apply a first voltage, and the second power supply terminal is configured to apply a second voltage, where a voltage value of the second voltage is smaller than a voltage value of the first voltage.

Optionally, in the level shift circuit, the second power supply terminal is further configured to reduce a voltage value of the second voltage to a predetermined value required to be output by the second output terminal.

Optionally, in the level shift circuit, the first signal is 0V, and the second signal is 1.05V to 1.35V.

Optionally, in the level shift circuit, the first voltage is 1.05V to 1.35V, and the second voltage is 0V.

Optionally, in the level shift circuit, the predetermined value required to be output by the second output terminal is-0.4V.

Optionally, in the level shift circuit, substrates of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor are all connected to the first power supply terminal;

the substrate of the seventh PMOS transistor is connected with the source electrode of the seventh PMOS transistor, and the substrate of the eighth PMOS transistor is connected with the source electrode of the eighth PMOS transistor;

the substrates of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor and the sixth NMOS transistor are all connected with the first power end.

The invention also provides a level shift circuit operation method based on the level shift circuit, which comprises the following steps:

performing setting operation, namely applying a first signal to the first signal end and applying a second signal to the second signal end, wherein the first signal is a zero-voltage low-level signal, and the second signal is a positive-voltage high-level signal;

applying a first voltage to the first power supply terminal and applying a second voltage to the second power supply terminal, wherein the voltage value of the second voltage is smaller than that of the first voltage;

the set operation is followed by a level shift operation, the level shift operation comprising: and maintaining the first signal and the second signal to be input into the first signal terminal and the second signal terminal, and reducing the voltage value of the second voltage to a preset value required to be output by the second output terminal.

In the level shift circuit provided by the invention, through connecting the latch unit and the drive unit, the conversion unit comprising the fifth PMOS transistor, the sixth PMOS transistor, the third NMOS transistor and the fourth NMOS transistor and the input unit comprising the seventh PMOS transistor, the eighth PMOS transistor, the fifth NMOS transistor and the sixth NMOS transistor realize that when the first signal is a zero-voltage low-level signal, the input voltage of the drive unit (namely, the gate voltage of the third PMOS transistor) is a negative value of the first power supply end voltage, the voltage between the gate and the source of the third PMOS transistor is the double first power supply end voltage, the threshold value of the third PMOS transistor is greatly higher than the threshold value on voltage, the driving capability of the third PMOS transistor and the working speed of the level shift circuit are improved, the current of the third PMOS transistor is reduced, and when the first signal is a positive-voltage high-level signal, the input voltage of the drive unit (namely, the gate voltage of the third PMOS transistor) is the first power supply end voltage, and the third PMOS transistor is turned off; similarly, when the second signal is a zero-voltage low-level signal, the input voltage of the driving unit (i.e., the gate voltage of the fourth PMOS transistor) is a negative value of the first power supply terminal voltage, and then the voltage between the gates of the fourth PMOS transistor is twice the first power supply terminal voltage, which is substantially higher than the threshold on voltage of the fourth PMOS transistor, so that the driving capability of the fourth PMOS transistor and the operating speed of the level shift circuit are improved, the current of the fourth PMOS transistor is reduced, and when the second signal is a positive-voltage high-level signal, the input voltage of the driving unit (i.e., the gate voltage of the fourth PMOS transistor) is the first power supply terminal voltage, and the fourth PMOS transistor is turned off.

Drawings

FIG. 1 is a schematic diagram of a prior art negative voltage level shift circuit;

FIG. 2 is a schematic diagram of a prior art positive voltage level shifting circuit;

FIG. 3 is a schematic diagram of a level shifting circuit for negative voltage level shifting according to an embodiment of the present invention;

fig. 4 is a schematic diagram of signal waveforms of a level shift circuit according to an embodiment of the invention.

Detailed Description

The level shift circuit according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the invention will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

The core idea of the invention is to provide a level shift circuit to solve the problems of insufficient driving capability and slow working speed caused by the insufficient driving capability of the existing level shift circuit.

To achieve the above idea, the present invention provides a level shift circuit, as shown in fig. 3, including a conversion unit, an input unit, a driving unit, and a latch unit, wherein: a conversion unit including a fifth PMOS transistor P5, a sixth PMOS transistor P6, a third NMOS transistor N3, and a fourth NMOS transistor N4; the gate of the fifth PMOS transistor P5 is connected to the gate of the third NMOS transistor N3 as the first signal S1 terminal, the source of the fifth PMOS transistor P5 is connected to the first power supply terminal V1, and the drain of the fifth PMOS transistor P5 is connected to the drain of the third NMOS transistor N3; the gate of the sixth PMOS transistor P6 is connected to the gate of the fourth NMOS transistor N4 as the second signal S2 terminal, the source of the sixth PMOS transistor P6 is connected to the first power supply terminal V1, and the drain of the sixth PMOS transistor P6 is connected to the drain of the fourth NMOS transistor N4; an input unit including a seventh PMOS transistor P7, an eighth PMOS transistor P8, a fifth NMOS transistor N5, and a sixth NMOS transistor N6; the gate of the fifth NMOS transistor N5 is connected to the drain of the fifth PMOS transistor P5, the source of the fifth NMOS transistor N5 is connected to the source of the third NMOS transistor N3, and the drain of the fifth NMOS transistor N5 is connected to the second power supply terminal V2; the gate of the sixth NMOS transistor N6 is connected to the drain of the sixth PMOS transistor P6, the source of the sixth NMOS transistor N6 is connected to the source of the fourth NMOS transistor N4, and the drain of the sixth NMOS transistor N6 is connected to the second power supply terminal V2; the gate of the seventh PMOS transistor P7 is connected to the source of the fifth NMOS transistor N5, and the source and drain of the seventh PMOS transistor P7 are connected to the gate of the third PMOS transistor P3; the gate of the eighth PMOS transistor P8 is connected to the source of the sixth NMOS transistor N6, and the source and drain of the eighth PMOS transistor P8 are connected to the gate of the fourth PMOS transistor P4. The driving unit is used for driving the latch unit to latch according to signals provided by the seventh PMOS transistor and the eighth PMOS transistor; the latch unit is used for latching according to the signal provided by the drive unit and outputting a predetermined value of the required output of the latch.

Specifically, the latch unit includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, and a second NMOS transistor N2; the source of the first PMOS transistor P1 is connected to the source of the second PMOS transistor P2 and is used as a first power supply terminal V1, the drain of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1 and is used as a first output terminal out1 of the level shift circuit, and the gate of the first PMOS transistor P1 is connected to the gate of the first NMOS transistor N1 and is used as a second output terminal out2 of the level shift circuit; the drain electrode of the second PMOS transistor P2 is connected to the drain electrode of the second NMOS transistor N2 and to the second output terminal out2, and the gate electrode of the second PMOS transistor P2 is connected to the gate electrode of the second NMOS transistor N2 and to the first output terminal out1; the sources of the first NMOS transistor N1 and the second NMOS transistor N2 are connected and serve as a second power supply terminal V2.

Further, the driving unit includes a third PMOS transistor P3 and a fourth PMOS transistor P4; a source of the third PMOS transistor P3 is connected to the first power supply terminal V1, and a drain of the third PMOS transistor P3 is connected to the first output terminal out1; the source of the fourth PMOS transistor P4 is connected to the first power terminal V1, and the drain of the fourth PMOS transistor P4 is connected to the second output terminal out2.

Specifically, in the level shift circuit, the first signal terminal S1 is configured to apply a first signal S1, and the second signal terminal S2 is configured to apply a second signal S2, where the first signal S1 is a zero voltage low level signal, and the second signal S2 is a positive voltage high level signal. The first power supply terminal V1 is configured to apply a first voltage V1, and the second power supply terminal V2 is configured to apply a second voltage V2, where a voltage value of the second voltage V2 is smaller than a voltage value of the first voltage V1. The second power supply terminal V2 is further configured to reduce the voltage value of the second voltage V2 to a predetermined value required to be output by the second output terminal out2. The first signal S1 is 0V, and the second signal S2 is 1.05V-1.35V. The first voltage V1 is 1.05V-1.35V, and the second voltage V2 is 0V. The predetermined value of the required output of the second output terminal out2 is-0.4V.

As shown in fig. 3, in the level shift circuit, substrates of the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, the fourth PMOS transistor P4, the fifth PMOS transistor P5, and the sixth PMOS transistor P6 are all connected to the first power supply terminal V1; the substrate of the seventh PMOS transistor P7 is connected to the source of the seventh PMOS transistor P7, and the substrate of the eighth PMOS transistor P8 is connected to the source of the eighth PMOS transistor P8; substrates of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, the fourth NMOS transistor N4, the fifth NMOS transistor N5, and the sixth NMOS transistor N6 are all connected to the first power supply terminal V1.

In the level shift circuit provided in this embodiment, by connecting the latch unit and the driving unit, the conversion unit including the fifth PMOS transistor P5, the sixth PMOS transistor P6, the third NMOS transistor N3 and the fourth NMOS transistor N4 and the input unit including the seventh PMOS transistor P7, the eighth PMOS transistor P8, the fifth NMOS transistor N5 and the sixth NMOS transistor N6 realize that when the first signal S1 is a zero-voltage low-level signal, the input voltage of the driving unit (i.e., the gate voltage of the third PMOS transistor P3) is a negative value of the voltage at the first power supply terminal V1, the voltage between the gate and source of the third PMOS transistor P3 is twice the voltage at the first power supply terminal V1, which is substantially higher than the threshold on voltage of the third PMOS transistor P3, the driving capability of the third PMOS transistor P3 and the operating speed of the level shift circuit are improved, and when the first signal S1 is a positive-voltage low-level signal, the input voltage of the driving unit (i.e., the gate voltage of the third PMOS transistor P3) is the voltage at the first power supply terminal V1 is turned off; similarly, when the second signal S2 is a zero-voltage low-level signal, the input voltage of the driving unit (i.e., the gate voltage of the fourth PMOS transistor P4) is a negative value of the voltage of the first power supply terminal V1, and then the voltage between the gates and sources of the fourth PMOS transistor P4 is twice the voltage of the first power supply terminal V1, which is substantially higher than the threshold on voltage of the fourth PMOS transistor P4, so that the driving capability of the fourth PMOS transistor P4 and the operating speed of the level shift circuit are improved, the current of the fourth PMOS transistor P4 is reduced, and when the second signal S2 is a positive-voltage high-level signal, the input voltage of the driving unit (i.e., the gate voltage of the fourth PMOS transistor P4) is the voltage of the first power supply terminal V1, and the fourth PMOS transistor P4 is turned off.

The embodiment also provides a level shift circuit operation method based on the level shift circuit, which comprises the following steps: performing a set operation, applying a first signal S1 to the first signal terminal S1, and applying a second signal S2 to the second signal terminal S2, wherein the first signal S1 is a zero voltage low level signal, and the second signal S2 is a positive voltage high level signal; applying a first voltage V1 to the first power supply terminal V1, and applying a second voltage V2 to the second power supply terminal V2, wherein a voltage value of the second voltage V2 is smaller than a voltage value of the first voltage V1; the set operation is followed by a level shift operation, the level shift operation comprising: maintaining the first signal S1 and the second signal S2 input to the first signal terminal S1 and the second signal terminal S2, and reducing the voltage value of the second voltage V2 to a predetermined value required to be output by the second output terminal out2.

Further, in the level shift circuit, the first signal S1 is 0V, the second signal S2 is 1.2V, the first voltage V1 is 1.2V, the second voltage V2 is 0V, and the predetermined value required to be output by the second output terminal is-0.4V.

As shown in fig. 4, each signal waveform of the level shift circuit is shown in fig. 4, the first row waveform is a waveform of the first signal S1, the second row waveform is a gate voltage waveform of the fourth PMOS transistor P4, the third row waveform is a gate voltage waveform of the third PMOS transistor P3, and the fourth row waveform is a waveform of the second output terminal out2.

In summary, the above embodiments describe different configurations of the level shift circuit in detail, however, the present invention includes but is not limited to the configurations listed in the above embodiments, and any configuration that is converted based on the configurations provided in the above embodiments falls within the scope of the present invention. One skilled in the art can recognize that the above embodiments are illustrative.

The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims

1. A level shift circuit, comprising a conversion unit, an input unit, a driving unit, and a latch unit, wherein:

2. The level shift circuit of claim 1, wherein the latch unit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; the source electrode of the first PMOS transistor is connected with the source electrode of the second PMOS transistor and is used as a first power supply end, the drain electrode of the first PMOS transistor is connected with the drain electrode of the first NMOS transistor and is used as a first output end of the level shift circuit, and the grid electrode of the first PMOS transistor is connected with the grid electrode of the first NMOS transistor and is used as a second output end of the level shift circuit; the drain electrode of the second PMOS transistor is connected with the drain electrode of the second NMOS transistor and is connected to the second output end, and the grid electrode of the second PMOS transistor is connected with the grid electrode of the second NMOS transistor and is connected to the first output end; the source electrodes of the first NMOS transistor and the second NMOS transistor are connected and serve as a second power supply end;

3. The level shifting circuit of claim 2, wherein the first signal terminal is configured to apply a first signal and the second signal terminal is configured to apply a second signal, wherein the first signal is a zero voltage low level signal and the second signal is a positive voltage high level signal.

4. The level shifting circuit of claim 3, wherein the first power supply terminal is configured to apply a first voltage and the second power supply terminal is configured to apply a second voltage, wherein the second voltage has a voltage value that is less than a voltage value of the first voltage.

5. The level shifting circuit of claim 4, wherein the second power supply terminal is further configured to reduce a voltage value of the second voltage to a predetermined value for output required by the second output terminal.

6. The level shifting circuit of claim 5, wherein the first signal is 0V and the second signal is 1.05V to 1.35V.

7. The level shifting circuit of claim 5, wherein the first voltage is 1.05V to 1.35V and the second voltage is 0V.

8. The level shifting circuit of claim 5, wherein the predetermined value of the desired output at the second output terminal is-0.4V.

9. The level shift circuit of claim 5, wherein substrates of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor are all connected to the first power supply terminal;

10. A method of level shifting circuit operation based on the level shifting circuit of claim 9, comprising: