CN115913214B

CN115913214B - Positive and negative high voltage level conversion circuit

Info

Publication number: CN115913214B
Application number: CN202310028591.2A
Authority: CN
Inventors: 金建明; 虞豪驰
Original assignee: Shanghai Xinkai Integrated Circuit Co ltd
Current assignee: Shanghai Xinkai Integrated Circuit Co ltd
Priority date: 2023-01-09
Filing date: 2023-01-09
Publication date: 2023-06-27
Anticipated expiration: 2043-01-09
Also published as: CN115913214A

Abstract

The application discloses positive negative high voltage level conversion circuit includes: first and second PMOS transistors, first to sixth NMOS transistors, and an inverter; the gates of the first NMOS transistor and the second NMOS transistor are connected with an enable signal, the source electrode of the second NMOS transistor, the gate electrode of the fifth NMOS transistor and the input end of the inverter are connected with a positive input signal, and the inverter outputs a negative input signal to the source electrode of the first NMOS transistor and the gate electrode of the sixth NMOS transistor; the drain electrode of the fifth NMOS transistor is connected with the source electrode of the third NMOS transistor, and the grid electrode of the third NMOS transistor, the drain electrodes of the fourth NMOS transistor, the second PMOS transistor and the grid electrode of the first PMOS transistor are connected; the drain electrode of the sixth NMOS transistor is connected with the source electrode of the fourth NMOS transistor, and the grid electrode of the fourth NMOS transistor, the drain electrodes of the third NMOS transistor and the first NMOS transistor, the drain electrode of the first PMOS transistor and the grid electrode of the second PMOS transistor are connected. The application adopts a set of circuit to realize positive and negative high voltage level conversion simultaneously.

Description

Positive and negative high voltage level conversion circuit

Technical Field

The application relates to the technical field of integrated circuits, in particular to a positive-negative high-voltage level conversion circuit.

Background

In circuitry, the circuits of different voltage domains need to be connected by a level shifter circuit. The level conversion circuit distinguishes between a positive high voltage level conversion circuit, a negative high voltage level conversion circuit and a positive and negative high voltage level conversion circuit according to the output voltage. Among them, the current practice of the positive and negative high voltage level conversion circuit is to integrate the former two together.

Fig. 1 shows a conventional positive-negative high voltage level conversion circuit, wherein the high-low level corresponding to the input terminal IN is positive low voltage VDD and ground GND, respectively, and the high-low level corresponding to the output terminal OUT is positive high voltage VPOS and negative high voltage VNEG after passing through the level conversion circuit.

The operating principle is that IN outputs a positive high voltage level VPOS or GND through a positive high voltage level switching circuit lsp, which controls the on or off of the P-type transistor MP0, and fig. 2a is an internal circuit structure of the lsp. Meanwhile, IN controls on or off of the N-type transistor MN0 by outputting the negative high voltage VNEG or VDD through a negative high voltage level converting circuit lsn, and fig. 2b is an internal circuit structure of lsn. When IN inputs GND level, lsp outputs GND level, lsn outputs VNEG level, MP0 is turned on, MN0 is turned off, and OUT outputs VPOS level; when IN inputs VDD level, lsp outputs VPOS level, lsn outputs VDD level, MP0 is off, MN0 is on, and OUT outputs VNEG level.

The shortfall of the positive and negative high voltage level conversion circuit is that:

a) A larger number of transistors. lsp and lsn plus two output drive tubes, together require at least 14 transistors.

b) A larger operating current. The lsp and lsn consume current when the input signal IN changes, respectively.

c) The level shift speed is slow. Both lsp and lsn are on for the one-sided input transistor, off for the other-sided input transistor, and slow in output response.

Disclosure of Invention

The purpose of the application is to provide a positive and negative high-voltage level conversion circuit, which can realize the level conversion from a lower input positive level to a higher output positive level and the level conversion from a lower input positive level to a higher output negative level, and the circuit is generally simplified into a set of circuit by two sets of positive and negative independent level conversion circuits, so that the purposes of reducing the circuit area and the circuit power consumption are realized.

The application discloses positive negative high voltage level conversion circuit includes: first and second PMOS transistors, first to sixth NMOS transistors, and an inverter; wherein,,

the gates of the first NMOS transistor and the second NMOS transistor are connected with an enable signal, the source electrode of the second NMOS transistor, the gate electrode of the fifth NMOS transistor and the input end of the inverter are connected with a positive input signal, and the output end of the inverter outputs a negative input signal to the source electrode of the first NMOS transistor and the gate electrode of the sixth NMOS transistor; the drain electrode of the fifth NMOS transistor is connected with the source electrode of the third NMOS transistor, the grid electrode of the third NMOS transistor, the drain electrode of the fourth NMOS transistor, the drain electrode of the second PMOS transistor and the grid electrode of the first PMOS transistor are connected and output positive output voltage; the drain electrode of the sixth NMOS transistor is connected with the source electrode of the fourth NMOS transistor, and the grid electrode of the fourth NMOS transistor, the drain electrode of the third NMOS transistor, the drain electrode of the first PMOS transistor and the grid electrode of the second PMOS transistor are connected and output negative output voltage; the sources of the fifth NMOS transistor and the sixth NMOS transistor are connected with a negative voltage source; the sources of the first PMOS transistor and the second PMOS transistor are connected with a positive voltage source.

In a preferred embodiment, the substrates of the first to sixth NMOS transistors are connected to a negative voltage source, the substrates of the first and second PMOS transistors are connected to a positive voltage source, the voltage domain of the positive input signal is from 0 to a positive low voltage, the voltage of the positive voltage source is greater than or equal to the positive low voltage, and the voltage of the negative voltage source is less than or equal to 0.

In a preferred embodiment, the voltage of the negative voltage source is fixed to 0, the voltage of the positive voltage source is fixed to a positive high voltage, and the enable signal is fixed to a positive low voltage;

when the positive input signal is 0, the second NMOS transistor and the sixth NMOS transistor are turned on, the first NMOS transistor and the fifth NMOS transistor are turned off, so that the positive output voltage is 0, the negative output voltage is positive high voltage, the fourth NMOS transistor is turned on, and the second PMOS transistor is turned off, so that the positive output voltage is kept 0;

when the positive input signal is positive low voltage, the second NMOS transistor and the sixth NMOS transistor are turned off, the first NMOS transistor and the fifth NMOS transistor are turned on, so that the positive output voltage is positive high voltage, the negative output voltage is 0, the third NMOS transistor is turned on, and the first PMOS transistor is turned off, so that the negative output voltage is kept 0.

In a preferred embodiment, the voltage of the negative voltage source is fixed to 0, and the enable signal is fixed to a positive low voltage;

the voltage of the positive voltage source is firstly maintained at a positive low voltage; when the positive input signal is 0, the second NMOS transistor and the sixth NMOS transistor are turned on, the first NMOS transistor and the fifth NMOS transistor are turned off, so that the positive output voltage is 0, the negative output voltage is positive low voltage, the fourth NMOS transistor is turned on, and the second PMOS transistor is turned off, so that the positive output voltage is kept 0;

when the positive input signal is at a positive low voltage, the second NMOS transistor and the sixth NMOS transistor are turned off, the first NMOS transistor and the fifth NMOS transistor are turned on, so that the positive output voltage is at the positive low voltage, the negative output voltage is 0, the third NMOS transistor is turned on, and the first PMOS transistor is turned off, so that the negative output voltage is kept at 0; the voltage of the positive voltage source rises from a positive low voltage to a positive high voltage, so that the positive output voltage rises to the positive high voltage.

In a preferred embodiment, the voltage of the positive voltage source is fixed to be a positive low voltage;

the voltage of the negative voltage source is firstly maintained at 0, and the enabling signal is firstly fixed to be positive low voltage; when the positive input signal is 0, the second NMOS transistor and the sixth NMOS transistor are turned on, the first NMOS transistor and the fifth NMOS transistor are turned off, so that the positive output voltage is 0, the negative output voltage is positive low voltage, the fourth NMOS transistor is turned on, and the second PMOS transistor is turned off, so that the positive output voltage is kept 0;

when the positive input signal is at a positive low voltage, the second NMOS transistor and the sixth NMOS transistor are turned off, the first NMOS transistor and the fifth NMOS transistor are turned on, so that the positive output voltage is at the positive low voltage, the negative output voltage is 0, the third NMOS transistor is turned on, and the first PMOS transistor is turned off, so that the negative output voltage is kept at 0; the voltage of the negative voltage source is reduced from 0 to negative high voltage, and the enabling signal is changed along with the voltage of the negative voltage source, so that the negative output voltage is reduced to negative high voltage.

In a preferred embodiment, the voltage of the positive voltage source is first maintained at a positive low voltage, the voltage of the negative voltage source is first maintained at 0, and the enable signal is first fixed at the positive low voltage; when the positive input signal is 0, the second NMOS transistor and the sixth NMOS transistor are turned on, the first NMOS transistor and the fifth NMOS transistor are turned off, so that the positive output voltage is 0, the negative output voltage is positive low voltage, the fourth NMOS transistor is turned on, and the second PMOS transistor is turned off, so that the positive output voltage is kept 0;

when the positive input signal is at a positive low voltage, the second NMOS transistor and the sixth NMOS transistor are turned off, the first NMOS transistor and the fifth NMOS transistor are turned on, so that the positive output voltage is at the positive low voltage, the negative output voltage is 0, the third NMOS transistor is turned on, and the first PMOS transistor is turned off, so that the negative output voltage is kept at 0; the voltage of the positive voltage source is increased from positive low voltage to positive high voltage, so that the positive output voltage is increased to positive high voltage, the voltage of the negative voltage source is decreased from 0 to negative high voltage, and the enabling signal is changed along with the voltage of the negative voltage source, so that the negative output voltage is decreased to negative high voltage.

The positive and negative high voltage level conversion circuit of this application has compared prior art's advantage:

1. fewer transistor count: the same circuit function is realized by 10 transistors;

2. a smaller operating current;

3. faster switching speed: the positive input signal IN and the negative input signal INb are simultaneously input with opposite levels, so that the level inversion of the positive output voltage OUT and the negative output voltage OUTb is quickened.

In the present application, a number of technical features are described in the specification, and are distributed in each technical solution, which makes the specification too lengthy if all possible combinations of technical features (i.e. technical solutions) of the present application are to be listed. In order to avoid this problem, the technical features disclosed in the above summary of the present application, the technical features disclosed in the following embodiments and examples, and the technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which should be regarded as having been described in the present specification) unless such a combination of technical features is technically impossible. For example, in one example, feature a+b+c is disclosed, in another example, feature a+b+d+e is disclosed, and features C and D are equivalent technical means that perform the same function, technically only by alternative use, and may not be adopted simultaneously, feature E may be technically combined with feature C, and then the solution of a+b+c+d should not be considered as already described because of technical impossibility, and the solution of a+b+c+e should be considered as already described.

Drawings

Fig. 1 is a schematic diagram of a prior art positive-negative high voltage level conversion circuit.

Fig. 2a is a schematic diagram of a prior art positive high voltage level converting circuit.

Fig. 2b is a schematic diagram of a negative high voltage level conversion circuit in the prior art.

Fig. 3 is a schematic diagram of the structure of the positive-negative high voltage level conversion circuit according to one embodiment of the present application.

Fig. 4a is a waveform diagram of a positive-negative high voltage level conversion circuit as a mode of only a positive high voltage level conversion circuit according to one embodiment of the present application.

Fig. 4b is a waveform diagram of positive voltage source voltage rising from positive low voltage to positive high voltage mode in accordance with one embodiment of the present application.

Fig. 5 is a waveform diagram of a positive-negative high voltage level conversion circuit as a negative high voltage level conversion circuit mode only in accordance with one embodiment of the present application.

Fig. 6 is a waveform diagram of a positive-negative high voltage level conversion circuit according to an embodiment of the present application as a mode of the positive-negative high voltage level conversion circuit at the same time.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be understood by those skilled in the art that the claimed invention may be practiced without these specific details and with various changes and modifications from the embodiments that follow.

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

A first embodiment of the present application relates to a positive-negative high voltage level conversion circuit, the structure of which is shown in fig. 3, including: the first PMOS transistor MP1, the second PMOS transistor MP2, the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, and the inverter inv.

The gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 are both connected to an enable signal EN, the source of the second NMOS transistor MN2, the gate of the fifth NMOS transistor MN5, and the input terminal of the inverter inv are connected to a positive input signal IN, and the output terminal of the inverter inv outputs a negative input signal INb to the source of the first NMOS transistor MN1 and the gate of the sixth NMOS transistor MN 6. The drain of the fifth NMOS transistor MN5 is connected to the source of the third NMOS transistor MN3, and the gate of the third NMOS transistor MN3, the drain of the fourth NMOS transistor MN4, the drain of the second NMOS transistor MN2, the drain of the second PMOS transistor MP2, and the gate of the first PMOS transistor MP1 are connected to output a positive output voltage OUT. The drain of the sixth NMOS transistor MN6 is connected to the source of the fourth NMOS transistor MN4, and the gate of the fourth NMOS transistor MN4, the drain of the third NMOS transistor MN3, the drain of the first NMOS transistor MN1, the drain of the first PMOS transistor MP1, and the gate of the second PMOS transistor MP2 are connected to output the negative output voltage OUTb. The source of the fifth NMOS transistor MN5 and the source of the sixth NMOS transistor MN6 are both connected to the negative voltage source VENG. The source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are both connected to a positive voltage source VPOS.

In one embodiment, the substrates of the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, and the sixth NMOS transistor MN6 are all connected to a negative voltage source VENG or other level that does not cause forward conduction of the PN junction, and the substrates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are all connected to a positive voltage source VPOS or other level that does not cause forward conduction of the PN junction.

The voltage domain of the positive input signal IN is 0 to positive low voltage VDD, wherein the voltage of the positive voltage source VPOS is greater than or equal to the positive low voltage VDD, and the voltage of the negative voltage source VNEG is less than or equal to 0. Specifically, the voltage of the positive voltage source VPOS may be fixed to the positive low voltage VDD, or may be maintained at the positive low voltage VDD first and then raised to the positive high voltage, which is a voltage value higher than the positive low voltage VDD. The voltage of the negative voltage source VNEG may be fixed to 0 or first maintained at 0 and then dropped to a negative high voltage, which is a voltage value lower than 0.

Fig. 4a is a waveform diagram of a positive-negative high voltage level conversion circuit as a mode of only a positive high voltage level conversion circuit according to one embodiment of the present application. The voltage of the negative voltage source VNEG is fixed to 0, the voltage of the positive voltage source VPOS is fixed to a positive high voltage, and the enable signal EN is fixed to a positive low voltage VDD. When the positive input signal IN is 0, the second NMOS transistor MN2 and the sixth NMOS transistor MN6 are turned on, the first NMOS transistor MN1 and the fifth NMOS transistor MN5 are turned off so that the positive output voltage OUT is 0, the negative output voltage OUTb is a positive high voltage, the fourth NMOS transistor MN4 is turned on, and the second PMOS transistor MP2 is turned off so that the positive output voltage OUT is maintained at 0. When the positive input signal IN is a positive low voltage VDD, the second NMOS transistor MN2 and the sixth NMOS transistor MN6 are turned off, the first NMOS transistor MN1 and the fifth NMOS transistor MN5 are turned on, so that the positive output voltage OUT is a positive high voltage, the negative output voltage OUTb is 0, the third NMOS transistor MN3 is turned on, and the first PMOS transistor MP1 is turned off, so that the negative output voltage is maintained at 0.

Fig. 4b is a waveform diagram of positive voltage source voltage rising from positive low voltage to positive high voltage mode in accordance with one embodiment of the present application. The voltage of the negative voltage source VNEG is fixed to 0, and the enable signal EN is fixed to the positive low voltage VDD. The voltage of the positive voltage source VPOS is firstly maintained at a positive low voltage VDD; when the positive input signal IN is 0, the second NMOS transistor MN2 and the sixth NMOS transistor MN6 are turned on, the first NMOS transistor MN1 and the fifth NMOS transistor MN5 are turned off so that the positive output voltage OUT is 0, the negative output voltage OUTb is a positive low voltage VDD, the fourth NMOS transistor MN4 is turned on, and the second PMOS transistor MP2 is turned off so that the positive output voltage OUT is maintained at 0. When the positive input signal IN is at a positive low voltage, the second NMOS transistor MN2 and the sixth NMOS transistor MN6 are turned off, the first NMOS transistor MN1 and the fifth NMOS transistor MN5 are turned on, so that the positive output voltage OUT is at a positive low voltage, the negative output voltage is 0, the third NMOS transistor MN3 is turned on, and the first PMOS transistor MP1 is turned off, so that the negative output voltage OUTb is maintained at 0. The voltage of the positive voltage source VPOS rises from the positive low voltage VDD to the positive high voltage, so that the positive output voltage OUT rises to the positive high voltage.

Under the condition that the voltage values of the positive high voltage and the positive low voltage VDD are quite different, the level conversion can be finished when the voltage of the positive voltage source VPOS is maintained at the positive low voltage VDD, then the voltage of the positive voltage source VPOS is increased from VDD to the positive high voltage, the level conversion function is realized by smaller channel widths of NMOS transistors MN1, MN2, MN3, MN4, MN5 and MN6 or smaller channel lengths of PMOS transistors MP1 and MP2, and the circuit design cost is reduced.

Fig. 5 is a waveform diagram of a positive-negative high voltage level conversion circuit as a negative high voltage level conversion circuit mode only in accordance with one embodiment of the present application. The voltage of the positive voltage source VPOS is fixed to a positive low voltage VDD. The voltage of the negative voltage source VNEG is first maintained at 0, and the enable signal EN is first fixed to the positive low voltage VDD. When the positive input signal IN is 0, the second NMOS transistor MN2 and the sixth NMOS transistor MN6 are turned on, the first NMOS transistor MN1 and the fifth NMOS transistor MN5 are turned off so that the positive output voltage OUT is 0, the negative output voltage OUTb is a positive low voltage VDD, the fourth NMOS transistor NM4 is turned on, and the second PMOS transistor MP2 is turned off so that the positive output voltage OUT is maintained at 0. When the positive input signal IN is a positive low voltage VDD, the second NMOS transistor MN2 and the sixth NMOS transistor MN6 are turned off, the first NMOS transistor MN1 and the fifth NMOS transistor MN5 are turned on, so that the positive output voltage OUT is a positive low voltage VDD, the negative output voltage OUTb is 0, the third NMOS transistor MN3 is turned on, and the first PMOS transistor MP1 is turned off, so that the negative output voltage OUTb remains 0. The voltage of the negative voltage source VNEG drops from 0 to a negative high voltage, and the enable signal EN varies with the voltage of the negative voltage source VNEG such that the negative output voltage OUTb drops to a negative high voltage.

Fig. 6 is a waveform diagram of a positive-negative high voltage level conversion circuit according to an embodiment of the present application as a mode of the positive-negative high voltage level conversion circuit at the same time. The voltage of the positive voltage source VPOS is first maintained at the positive low voltage VDD, the voltage of the negative voltage source VNEG is first maintained at 0, and the enable signal EN is first fixed at the positive low voltage VDD; when the positive input signal IN is 0, the second NMOS transistor MN2 and the sixth NMOS transistor MN6 are turned on, the first NMOS transistor MN1 and the fifth NMOS transistor MN5 are turned off so that the positive output voltage OUT is 0, the negative output voltage OUTb is a positive low voltage VDD, the fourth NMOS transistor MN4 is turned on, and the second PMOS transistor MP2 is turned off so that the positive output voltage OUT is maintained at 0. When the positive input signal IN is a positive low voltage VDD, the second NMOS transistor MN2 and the sixth NMOS transistor MN6 are turned off, the first NMOS transistor MN1 and the fifth NMOS transistor MN5 are turned on, so that the positive output voltage OUT is a positive low voltage, the negative output voltage OUTb is 0, the third NMOS transistor MN3 is turned on, and the first PMOS transistor MP1 is turned off, so that the negative output voltage OUTb is maintained at 0. The voltage of the positive voltage source VPOS increases from the positive low voltage VDD to the positive high voltage so that the positive output voltage OUT increases to the positive high voltage, the voltage of the negative voltage source VNEG decreases from 0 to the negative high voltage, and the enable signal EN varies with the voltage of the negative voltage source VNEG so that the negative output voltage OUTb decreases to the negative high voltage.

The positive and negative high voltage level conversion circuit has three working modes: only as a positive high voltage level conversion circuit; only as a negative high voltage level conversion circuit; as a positive and negative high voltage level conversion circuit. In addition, the positive and negative high voltage level conversion circuit of the present application allows NMOS transistors therein to improve circuit performance by connecting multiple transistors of the same type in parallel.

It should be noted that in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, and two cases are included: the act is performed solely on the basis of the element and is performed on the basis of the element and other elements. Multiple, etc. expressions include 2, 2 times, 2, and 2 or more, 2 or more times, 2 or more.

This specification includes combinations of the various embodiments described herein. Separate references to embodiments (e.g., "one embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiment; however, unless indicated as mutually exclusive or as would be apparent to one of skill in the art, the embodiments are not mutually exclusive. It should be noted that the term "or" is used in this specification in a non-exclusive sense unless the context clearly indicates otherwise or requires otherwise.

All documents mentioned in the present specification are considered to be included in the disclosure of the present application as a whole, so that they may be regarded as a basis for modification if necessary. Furthermore, it should be understood that the foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, or the like, which is within the spirit and principles of one or more embodiments of the present disclosure, is intended to be included within the scope of one or more embodiments of the present disclosure.

Claims

1. A positive and negative high voltage level conversion circuit, comprising: first and second PMOS transistors, first to sixth NMOS transistors, and an inverter; wherein,,

2. The positive-negative high voltage level conversion circuit according to claim 1, wherein substrates of the first to sixth NMOS transistors are each connected to a negative voltage source, substrates of the first and second PMOS transistors are each connected to a positive voltage source, a voltage domain of the positive input signal is 0 to a positive low voltage, wherein a voltage of the positive voltage source is equal to or higher than the positive low voltage, and a voltage of the negative voltage source is equal to or lower than 0.

3. The positive-negative high voltage level conversion circuit according to claim 1, wherein the voltage of the negative voltage source is fixed to 0, the voltage of the positive voltage source is fixed to a positive high voltage, and the enable signal is fixed to a positive low voltage;

4. The positive-negative high voltage level conversion circuit according to claim 1, wherein the voltage of the negative voltage source is fixed to 0, and the enable signal is fixed to a positive low voltage;

5. The positive-negative high voltage level conversion circuit according to claim 1, wherein the voltage of the positive voltage source is fixed to a positive low voltage;

6. The positive-negative high voltage level converting circuit according to claim 1, wherein,

the voltage of the positive voltage source is firstly maintained at a positive low voltage, the voltage of the negative voltage source is firstly maintained at 0, and the enabling signal is firstly fixed at the positive low voltage; when the positive input signal is 0, the second NMOS transistor and the sixth NMOS transistor are turned on, the first NMOS transistor and the fifth NMOS transistor are turned off, so that the positive output voltage is 0, the negative output voltage is positive low voltage, the fourth NMOS transistor is turned on, and the second PMOS transistor is turned off, so that the positive output voltage is kept 0;