CN114629489B - Level conversion circuit and electronic equipment with multiple voltage domains - Google Patents
Level conversion circuit and electronic equipment with multiple voltage domains Download PDFInfo
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Abstract
The application discloses a level conversion circuit and multi-voltage-domain electronic equipment, which realize the design targets of high response speed, low static power consumption and small layout area of the level conversion circuit. The circuit comprises: four inverters INV1 to INV4, four N-type switching transistors MN1 to MN4 and four P-type switching transistors MP1 to MP4; the output of INV3 is connected with the input of INV4 and the control electrodes of MN1, MN3 and MP 3; the output of INV4 is connected with the control electrodes of MN2, MN4 and MP4; the outputs of MN3 and MN4 are grounded; the output of MN1 connects the output of MP3 and the input of MN 3; the output of MN2 connects the output of MP4 and the input of MN 4; the input of MP3 and MP4 is connected with low voltage; the inputs of MP2 and MP1 are connected with high voltage; MN1, MN2, MP1 and MP2 constitute pseudo differential inputs and outputs; the output of MP2 is connected with the input of INV2 through INV 1.
Description
Technical Field
The present invention relates to the field of power electronics, and more particularly, to a level shifter circuit and a multi-voltage domain electronic device.
Background
Multi-voltage domain electronic devices typically use level shifting circuitry to effect the conversion of low voltage domain signals to high voltage domain signals. In particular, in large analog-to-digital mixed multi-voltage domain electronic devices, the digital module and the analog module typically correspond to different power supply voltages, and the power supply voltages may be different, for example, the core voltage of the digital module is typically lower than 1V, but more analog modules are typically higher power supply voltages; the digital module and the analog module have data interaction, so the importance of the level conversion circuit is developed, and the level conversion circuit is widely applied to various interface circuits and input/output units to realize the logic conversion of the level.
In the conventional level shift circuit, the lower digital power supply signal VDDL has the problem that NMOS cannot be fully driven, so that the level shift speed is slower, and the output level of the high voltage domain cannot be effectively shifted along with the input level. In order to improve the product competitiveness, the electronic equipment with multiple voltage domains has higher requirements on the response speed, the static power consumption, the layout area and the like of the level conversion circuit, so that the level conversion circuit with high response speed, low static power consumption and small layout area needs to be designed.
Disclosure of Invention
In view of the above, the present invention provides a level shifter circuit and a multi-voltage domain electronic device, so as to achieve the design goals of fast response speed, low static power consumption and small layout area of the level shifter circuit.
A level shifter circuit comprising: the first inverter INV1, the second inverter INV2, the third inverter INV3, the fourth inverter INV4, the first N-type switching tube MN1, the second N-type switching tube MN2, the third N-type switching tube MN3, the fourth N-type switching tube MN4, the first P-type switching tube MP1, the second P-type switching tube MP2, the third P-type switching tube MP3 and the fourth P-type switching tube MP4;
The third inverter INV3 and the fourth inverter INV4 are both powered by the first voltage VDDL, and the first inverter INV1 and the second inverter INV2 are both powered by the second voltage VDDH; the first voltage VDDL is smaller than the second voltage VDDH;
The output end of the third inverter INV3 is connected with the input end of the fourth inverter INV4, the control electrode of the first N-type switching tube MN1, the control electrode of the third N-type switching tube MN3 and the control electrode of the third P-type switching tube MP 3;
the output end of the fourth inverter INV4 is connected with the control electrode of the second N-type switching tube MN2, the control electrode of the fourth N-type switching tube MN4 and the control electrode of the fourth P-type switching tube MP 4;
the current output poles of the third N-type switching tube MN3 and the fourth N-type switching tube MN4 are grounded;
The current output electrode of the first N-type switching tube MN1 is connected with the current output electrode of the third P-type switching tube MP3 and the current input electrode of the third N-type switching tube MN 3;
The current output electrode of the second N-type switching tube MN2 is connected with the current output electrode of the fourth P-type switching tube MP4 and the current input electrode of the fourth N-type switching tube MN 4;
The current input poles of the third P-type switching tube MP3 and the fourth P-type switching tube MP4 are both connected with the first voltage VDDL;
The current input electrode of the first N-type switching tube MN1 is connected with the current output electrode of the second P-type switching tube MP2 and the control electrode of the first P-type switching tube MP 1;
the current input electrode of the second N-type switching tube MN2 is connected with the control electrode of the second P-type switching tube MP2 and the current output electrode of the first P-type switching tube MP 1;
the current input poles of the second P-type switching tube MP2 and the first P-type switching tube MP1 are both connected with the second voltage VDDH;
the output end of the first inverter INV1 is connected with the input end of the second inverter INV 2;
the input end of the first inverter INV1 is connected with the current output electrode of the second P-type switching tube MP 2;
The input of the third inverter INV3 is the control level VIN of the level shift circuit, and the output of the second inverter INV2 is the output VOUT of the level shift circuit.
Optionally, the width-to-length ratio of the first N-type switching tube MN1, the second N-type switching tube MN2, the first P-type switching tube MP1 and the second P-type switching tube MP2 is equal to the width-to-length ratio of the first N-type switching tube MN1 and the second N-type switching tube MN2, and the width-to-length ratio of the first P-type switching tube MP1 and the second P-type switching tube MP2 is equal to the width-to-length ratio of the first P-type switching tube MP1 and the second P-type switching tube MP2, which is also:
The current flowing through the first N-type switching tube MN1 after being turned on is greater than the current flowing through the second P-type switching tube MP2 after being turned on, and/or the gain of amplifying the gate-to-drain voltage of the first N-type switching tube MN1 by the positive feedback structure formed by the first P-type switching tube MP1 and the second P-type switching tube MP2 exceeds a first preset value.
Optionally, the input end of the first inverter INV1 is connected to the current output electrode of the second P-type switching tube MP2, and is replaced by:
the input end of the first inverter INV1 is connected with the current output electrode of the first P-type switching tube MP 1.
Optionally, the threshold voltages of the third N-type switching transistor MN3 and the fourth N-type switching transistor MN4 are smaller than the second preset value.
Optionally, any N-type switching tube in the level conversion circuit is an N-type MOSFET, an N-type IGBT or an NPN triode.
Optionally, any P-type switching tube in the level conversion circuit is a P-type MOSFET, a P-type IGBT or a PNP triode.
Optionally, any inverter in the level shift circuit is a CMOS inverter.
A multi-voltage domain electronic device comprising any of the level shifting circuits disclosed above.
As can be seen from the above technical solution, the present invention can realize the conversion from the low voltage domain signal VDDL to the high voltage domain signal VDDH by controlling the low/high level switching of the level VIN. And one of the left branch circuit and the right branch circuit is kept to be disconnected at any time, so that the static loss of the level conversion circuit is reduced. In addition, the MN3 and the MP3 in the left branch circuit form an inverter, so that the driving capability of the MN1 is improved, and the MN4 and the MP4 in the right branch circuit form an inverter, so that the driving capability of the MN2 is improved, the drains of the MN1 and the MN2 can quickly respond to signal change, the delay of signal transmission is reduced, and the level conversion speed of the level conversion circuit is improved. Moreover, the circuit has simple structure and small layout area.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a level shifter circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a level shifter circuit according to an embodiment of the present invention;
FIG. 3 is a simulated waveform diagram of the level shifter circuit of FIG. 1;
fig. 4 is a schematic diagram of an inverter circuit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of an inverter circuit according to another embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, an embodiment of the present invention discloses a level shift circuit, including: the first inverter INV1, the second inverter INV2, the third inverter INV3, the fourth inverter INV4, the first N-type switching tube MN1, the second N-type switching tube MN2, the third N-type switching tube MN3, the fourth N-type switching tube MN4, the first P-type switching tube MP1, the second P-type switching tube MP2, the third P-type switching tube MP3 and the fourth P-type switching tube MP4;
the third inverter INV3 and the fourth inverter INV4 are powered by the first voltage VDDL, and the first inverter INV1 and the second inverter INV2 are powered by the second voltage VDDH; ground voltage (i.e., zero voltage) < the first voltage VDDL < the second voltage VDDH, e.g., vddl=1.1v and vddh=5v is set
The switching tube is divided into an N-type switching tube and a P-type switching tube; the switching tube is an N-type switching tube or a P-type switching tube, and is provided with three pins, namely a control electrode, a current input electrode and a current output electrode;
The output end of the third inverter INV3 is connected with the input end of the fourth inverter INV4, the control electrode of the first N-type switching tube MN1, the control electrode of the third N-type switching tube MN3 and the control electrode of the third P-type switching tube MP 3;
the output end of the fourth inverter INV4 is connected with the control electrode of the second N-type switching tube MN2, the control electrode of the fourth N-type switching tube MN4 and the control electrode of the fourth P-type switching tube MP 4;
the current output poles of the third N-type switching tube MN3 and the fourth N-type switching tube MN4 are grounded;
The current output electrode of the first N-type switching tube MN1 is connected with the current output electrode of the third P-type switching tube MP3 and the current input electrode of the third N-type switching tube MN 3;
The current output electrode of the second N-type switching tube MN2 is connected with the current output electrode of the fourth P-type switching tube MP4 and the current input electrode of the fourth N-type switching tube MN 4;
The current input poles of the third P-type switching tube MP3 and the fourth P-type switching tube MP4 are connected with the first voltage VDDL;
The current input electrode of the first N-type switching tube MN1 is connected with the current output electrode of the second P-type switching tube MP2 and the control electrode of the first P-type switching tube MP 1;
the current input electrode of the second N-type switching tube MN2 is connected with the control electrode of the second P-type switching tube MP2 and the current output electrode of the first P-type switching tube MP 1;
the current input poles of the second P-type switching tube MP2 and the first P-type switching tube MP1 are both connected with a second voltage VDDH;
the output end of the first inverter INV1 is connected with the input end of the second inverter INV 2;
the input end of the first inverter INV1 is connected with the current output electrode of the second P-type switching tube MP 2;
The input of the third inverter INV3 is the control level VIN of the level shift circuit, and the output of the second inverter INV2 is the output VOUT of the level shift circuit.
Optionally, any N-type switching transistor in the circuit shown in fig. 1 may be an N-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), an N-type IGBT (Insulated Gate Bipolar Transistor ), or an NPN triode, which is not limited. Any P-type switching tube in the circuit shown in fig. 1 can be a P-type MOSFET, a P-type IGBT, or a PNP triode, and is not limited.
When the N-type switching tube is an N-type MOSFET, the current input of the N-type switching tube is a drain electrode, the current output of the N-type switching tube is a source electrode, and the control of the N-type switching tube is a grid electrode. When the N-type switching tube is an N-type IGBT, the current input of the N-type switching tube is a collector electrode, the current output of the N-type switching tube is an emitter electrode, and the control of the switching tube is a grid electrode. When the N-type switching tube is an NPN triode, the current input of the N-type switching tube is a collector electrode, the current output of the N-type switching tube is an emitter electrode, and the control of the N-type switching tube is a base electrode.
When the P-type switching tube is a P-type MOSFET, the current input of the P-type switching tube is a source electrode, the current output of the P-type switching tube is a drain electrode, and the control of the P-type switching tube is a grid electrode. When the P-type switching tube is a P-type IGBT, the current input of the P-type switching tube is an emitter electrode, the current output of the P-type switching tube is a collector electrode, and the control of the P-type switching tube is a grid electrode. When the P-type switching tube is a PNP triode, the current input of the P-type switching tube is an emitter electrode, the current output of the P-type switching tube is a collector electrode, and the control of the P-type switching tube is a base electrode.
The working principle of the circuit shown in fig. 1 will be described in detail only by taking an example that each N-type switching tube in the circuit shown in fig. 1 is an N-type MOSFET (abbreviated as an NMOS tube) and each P-type switching tube is a P-type MOSFET (abbreviated as a PMOS tube).
The switching state of a MOSFET is mainly determined by the gate-source voltage. The NMOS tube is conducted when the gate-source voltage is larger than a certain value (the value is called threshold voltage); the conventional connection method is to make the source electrode of the NMOS tube directly grounded and the grid electrode of the NMOS tube apply a high level, so that the NMOS tube is conducted. The PMOS tube is conducted when the gate-source voltage is smaller than a certain value; the conventional connection method is to make the source electrode of the PMOS tube directly connected with a power supply and the grid electrode of the PMOS tube apply low level, so that the PMOS tube is conducted. The circuit shown in fig. 1 uses conventional coupling for the MOSFETs except for MN1 and MN 2.
The circuit shown in fig. 1 is divided into a left symmetrical branch and a right symmetrical branch, which are respectively a left branch where MN1 is located and a right branch where MN2 is located. When the control level VIN is switched from the high level to the low level, the third inverter INV3 outputs the high level, and the fourth inverter INV4 outputs the low level, at which time:
For the right branch, MN4 is turned off and MP4 is turned on, at this time, the source voltage of MN2 is instantaneously raised from zero voltage to low voltage VDDL, so compared with the conventional connection method of MN2, the gate-source voltage of MN2 is reduced more greatly under the conventional connection method, so that the difference between the gate-source voltage of MN2 and the threshold voltage of MN2 is greater, and MN2 is turned off more thoroughly (i.e. there is no possibility that MN2 cannot be turned off completely);
For the left branch, MN3 and MN1 are turned on and MP3 is turned off, at this time, the drain of MP2 is at low level, and the output VOUT of the level shifter is at low voltage VDDL.
And when the control level VIN is switched from the low level to the high level, the third inverter INV3 outputs the low level, and the fourth inverter INV4 outputs the high level, at which time:
for the left branch, MN3 is turned off and MP3 is turned on, at this time, the source voltage of MN1 is instantaneously raised from zero voltage to low voltage VDDL, so, compared with the conventional connection method adopted by MN1, the reduction of the gate-source voltage of MN1 under the conventional connection method is greater, so the difference between the gate-source voltage of MN1 and the threshold voltage of MN1 is greater, and MN1 is turned off more thoroughly (i.e., there is no possibility that MN1 cannot be completely turned off);
For the right branch, MN4 and MN2 are turned on and MP4 is turned off, at this time MP2 is turned on, the drain of MP2 is turned from zero voltage to high voltage VDDH, and the output VOUT of the level shifter circuit is high voltage VDDH.
It can be seen that the transition of the low voltage domain signal VDDL to the high voltage domain signal VDDH can be achieved by controlling the low/high level switching of the level VIN. And one of the left branch circuit and the right branch circuit is kept to be disconnected at any time, so that the static loss of the level conversion circuit is reduced. Moreover, the circuit shown in fig. 1 has a simple structure, so the layout area is small.
In addition, MN3 and MP3 in the circuit shown in fig. 1 form an inverter, which improves the driving capability of MN1, and MN4 and MP4 form an inverter, which improves the driving capability of MN2, so that the drains of MN1 and MN2 can quickly respond to signal changes, reduce the delay of signal transmission, and improve the level conversion speed of the level conversion circuit.
As can be seen from the above description, the embodiment of the present invention can realize the conversion from the low voltage domain signal VDDL to the high voltage domain signal VDDH by controlling the low/high level switching of the level VIN. And one of the left branch circuit and the right branch circuit is kept to be disconnected at any time, so that the static loss of the level conversion circuit is reduced. In addition, in the embodiment of the invention, the MN3 and the MP3 form the inverter, so that the driving capability of the MN1 is improved, and meanwhile, the MN4 and the MP4 form the inverter, so that the driving capability of the MN2 is improved, the drains of the MN1 and the MN2 can quickly respond to signal change, and the level conversion speed of the level conversion circuit is improved. In addition, the embodiment of the invention has the advantages of simple circuit structure and small layout area.
In addition, MN1, MN2, MP1, MP2 in the circuit shown in fig. 1 constitute pseudo-differential input and output, and the conductive carriers in this structure are mainly electrons, have high mobility, and can shorten the time for the drain voltage to flip from low level to high level or from high level to low level when the MOSFET is turned on. In this structure, when MP2 is turned on, since the gate-source voltage of MP2 is large and the current is large, limitation is required, that is, it is required to ensure that the current I MN flowing after MN1 is turned on is greater than the current I MP flowing after MP2 is turned on, otherwise, the drain voltage of MP2 may not go over from 0 to VDDH or delay of level inversion is increased.
The expressions of I MP and I MN are known as follows:
Where u p denotes electron mobility of MP2, C ox denotes gate capacitance, W P denotes width of a conductive channel of MP2, L P denotes length of the conductive channel of MP2, V thp denotes threshold voltage of MP2, u n denotes electron mobility of MN1, W n denotes width of the conductive channel of MN1, L n denotes length of the conductive channel of MN1, and V thn denotes threshold voltage of MN 1.
As can be seen from the expressions I MP and I MN, to guarantee I MN>IMP, it is necessary to reduce the width to length ratio (W/L) of MP2 to limit I MN, while it is necessary to increase the width to length ratio of MN1 to strengthen I MN. Therefore, in the circuit shown in fig. 1, the embodiment of the invention recommends that the width-to-length ratio of MN1 and MP2 in the structure is reasonably set, so that the delay of signal transmission is further reduced, and the level conversion speed of the level conversion circuit is improved.
Considering circuit symmetry, the aspect ratio of MN1 is identical to the aspect ratio of MN2 in design, and the aspect ratio of MP1 is identical to the aspect ratio of MP 2.
In addition, MP1 and MP2 in the circuit shown in fig. 1 are cross-coupled to form a positive feedback structure, which can quickly amplify the gate-to-drain voltages of MN1 and MN 2. Taking MN1 as an example, the gate-to-drain voltage gain of MN1Gm n1 is the transconductance of MN1, gm p1 is the transconductance of MP1,/>V gsn is the gate-source voltage of MN1 and V gsp is the gate-source voltage of MP 1. Since MP1 selects a smaller width-to-length ratio and MN1 selects a larger width-to-length ratio, the voltage gain a V can be increased, thereby increasing the level conversion speed of the level conversion circuit.
In summary, the embodiment of the present invention recommends to set the width-to-length ratio of the first N-type switching tube MN1, the second N-type switching tube MN2, the first P-type switching tube MP1 and the second P-type switching tube MP2 to satisfy not only that the width-to-length ratio of the first N-type switching tube MN1 is equal to the width-to-length ratio of the second N-type switching tube MN2, but also that the width-to-length ratio of the first P-type switching tube MP1 is equal to the width-to-length ratio of the second P-type switching tube MP 2: the current flowing through the first N-type switching tube MN1 after being turned on is greater than the current flowing through the second P-type switching tube MP2 after being turned on, and/or the gain of amplifying the gate-to-drain voltage of the first N-type switching tube MN1 by the positive feedback structure formed by the first P-type switching tube MP1 and the second P-type switching tube MP2 exceeds a first preset value.
Taking the circuit shown in fig. 1 as a 1.1V-to-5V level conversion circuit and VIN as a square wave signal as an example, the simulation waveforms of the control level VIN, the output VOUT, the first voltage VDDL and the second voltage VDDH of the 1.1V-to-5V level conversion circuit are respectively shown in fig. 2. As can be seen from fig. 2, VOUT follows VIN quickly after VIN goes high, and the rise time is very short; VOUT quickly goes from high to low after VIN switches to low.
Optionally, based on any one of the embodiments disclosed in the foregoing disclosure, the embodiments of the present invention recommend setting the threshold voltages of MN3 and MN4 to be relatively low (lower than a second preset value, where the second preset value is set according to a required level conversion speed on the premise that normal operation of the circuit is not affected), so that the drains of MN3 and MN4 can further quickly respond to signal changes, delay of signal transmission is reduced, and the level conversion speed of the level conversion circuit is improved.
Optionally, based on any of the embodiments disclosed above, the embodiment of the present invention recommends that the sizes of MOS transistors inside the first inverter INV1, the second inverter INV2, the third inverter INV3, and the fourth inverter INV4 all adopt smaller sizes, so as to further reduce the layout area of the whole level conversion circuit. Optionally, the embodiment of the invention recommends that MP3 and MP4 avoid using larger width-to-length ratio, thereby further saving layout area.
Fig. 2 discloses a further level shift circuit which differs from the circuit shown in fig. 1 in that: instead of terminating the input end of the first inverter INV1 in the circuit shown in fig. 1 to the current output electrode of the second P-type switching tube MP2, it is: the input end of the first inverter INV1 is connected with the current output electrode of the first P-type switching tube MP 1. Then, when VIN goes low, VOUT quickly follows VIN going high and the rise time is very short; VOUT quickly goes from high to low after VIN switches to high. The working principle of the circuit is the same as that of the circuit shown in fig. 1, and is not described here again.
Alternatively, based on any of the embodiments disclosed above, a CMOS inverter may be used as any of the inverters, and the circuit structure of the CMOS inverter is shown IN fig. 4 or fig. 5, and the CMOS inverter includes an N-type switching tube and a P-type switching tube, where the current input electrode of the P-type switching tube is connected to a power supply (VDDL is used as an example IN fig. 4 and INV3 and INV4 are corresponding to VDDH is used as an example IN fig. 5 and INV1 and INV2 are corresponding to the power supply), the control electrodes of the P-type switching tube and the N-type switching tube are connected together as an input terminal IN of the inverter, and the current output electrode of the P-type switching tube and the current input electrode of the N-type switching tube are connected together as an output terminal OUT of the inverter, and the current output electrode of the N-type switching tube is grounded.
In addition, the embodiment of the invention also discloses a multi-voltage domain electronic device, which comprises: any of the level shifting circuits disclosed above.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
The terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar different objects and not necessarily for describing a particular sequential or chronological order. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the embodiments of the invention. Thus, the present embodiments are not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. A level shifter circuit, comprising: a first inverter (INV 1), a second inverter (INV 2), a third inverter (INV 3), a fourth inverter (INV 4), a first N-type switching tube (MN 1), a second N-type switching tube (MN 2), a third N-type switching tube (MN 3), a fourth N-type switching tube (MN 4), a first P-type switching tube (MP 1), a second P-type switching tube (MP 2), a third P-type switching tube (MP 3) and a fourth P-type switching tube (MP 4);
Wherein, the third inverter (INV 3) and the fourth inverter (INV 4) are powered by a first Voltage (VDDL), and the first inverter (INV 1) and the second inverter (INV 2) are powered by a second Voltage (VDDH); the first Voltage (VDDL) is less than the second Voltage (VDDH);
The output end of the third inverter (INV 3) is connected with the input end of the fourth inverter (INV 4), the control electrode of the first N-type switching tube (MN 1), the control electrode of the third N-type switching tube (MN 3) and the control electrode of the third P-type switching tube (MP 3);
the output end of the fourth inverter (INV 4) is connected with the control electrode of the second N-type switching tube (MN 2), the control electrode of the fourth N-type switching tube (MN 4) and the control electrode of the fourth P-type switching tube (MP 4);
The current output poles of the third N-type switching tube (MN 3) and the fourth N-type switching tube (MN 4) are grounded;
The current output electrode of the first N-type switching tube (MN 1) is connected with the current output electrode of the third P-type switching tube (MP 3) and the current input electrode of the third N-type switching tube (MN 3);
The current output electrode of the second N-type switching tube (MN 2) is connected with the current output electrode of the fourth P-type switching tube (MP 4) and the current input electrode of the fourth N-type switching tube (MN 4);
The current input poles of the third P-type switching tube (MP 3) and the fourth P-type switching tube (MP 4) are connected with the first Voltage (VDDL);
the current input electrode of the first N-type switching tube (MN 1) is connected with the current output electrode of the second P-type switching tube (MP 2) and the control electrode of the first P-type switching tube (MP 1);
the current input electrode of the second N-type switching tube (MN 2) is connected with the control electrode of the second P-type switching tube (MP 2) and the current output electrode of the first P-type switching tube (MP 1);
the current input poles of the second P-type switching tube (MP 2) and the first P-type switching tube (MP 1) are both connected with the second Voltage (VDDH);
The output end of the first inverter (INV 1) is connected with the input end of the second inverter (INV 2);
The input end of the first inverter (INV 1) is connected with the current output electrode of the second P-type switching tube (MP 2);
the input of the third inverter (INV 3) is the control level (VIN) of the level shift circuit, and the output of the second inverter (INV 2) is the output VOUT of the level shift circuit.
2. The level shift circuit according to claim 1, wherein the aspect ratio of the first N-type switching transistor (MN 1), the second N-type switching transistor (MN 2), the first P-type switching transistor (MP 1) and the second P-type switching transistor (MP 2) satisfies, in addition to the equal aspect ratio of the first N-type switching transistor (MN 1) and the second N-type switching transistor (MN 2), the equal aspect ratio of the first P-type switching transistor (MP 1) and the second P-type switching transistor (MP 2):
The current flowing through the first N-type switching tube (MN 1) after being conducted is larger than the current flowing through the second P-type switching tube (MP 2) after being conducted, and/or the gain of amplifying the grid electrode to the drain electrode voltage of the first N-type switching tube (MN 1) by a positive feedback structure formed by the first P-type switching tube (MP 1) and the second P-type switching tube (MP 2) exceeds a first preset value.
3. The level shift circuit according to claim 1 or 2, wherein the input terminal of the first inverter (INV 1) is connected to the current output terminal of the second P-type switching transistor (MP 2), replaced by:
the input end of the first inverter (INV 1) is connected with the current output electrode of the first P-type switching tube (MP 1).
4. The level shift circuit according to claim 1 or 2, wherein the threshold voltages of the third N-type switching transistor (MN 3) and the fourth N-type switching transistor (MN 4) are each smaller than a second preset value.
5. The level shift circuit according to claim 1 or 2, wherein any N-type switching transistor in the level shift circuit is an N-type MOSFET, an N-type IGBT or an NPN triode.
6. The level shifter circuit of claim 1 or 2, wherein any P-type switching transistor in the level shifter circuit is a P-type MOSFET, a P-type IGBT or a PNP transistor.
7. The level shift circuit according to claim 1 or 2, wherein any one of the inverters in the level shift circuit is a CMOS inverter.
8. A multi-voltage domain electronic device, comprising: the level shifter circuit of any one of claims 1 to 7.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101110575A (en) * | 2007-07-03 | 2008-01-23 | 华为技术有限公司 | Processing method for output stage circuit, power amplification circuit and electrical signal |
| CN105515560A (en) * | 2016-01-27 | 2016-04-20 | 灿芯半导体(上海)有限公司 | Voltage conversion circuit |
| CN108415505A (en) * | 2012-09-04 | 2018-08-17 | 瑞萨电子株式会社 | Differential output circuit and semiconductor devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP4230881B2 (en) * | 2003-10-23 | 2009-02-25 | 富士通マイクロエレクトロニクス株式会社 | Semiconductor integrated circuit and level conversion circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101110575A (en) * | 2007-07-03 | 2008-01-23 | 华为技术有限公司 | Processing method for output stage circuit, power amplification circuit and electrical signal |
| CN108415505A (en) * | 2012-09-04 | 2018-08-17 | 瑞萨电子株式会社 | Differential output circuit and semiconductor devices |
| CN105515560A (en) * | 2016-01-27 | 2016-04-20 | 灿芯半导体(上海)有限公司 | Voltage conversion circuit |
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| 基于双栅场效应管的二值到三值转换电路设计;方晨斌;夏银水;;无线通信技术;20170615(第02期);全文 * |
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