CN114629489A - Level conversion circuit and electronic equipment with multiple voltage domains - Google Patents
Level conversion circuit and electronic equipment with multiple voltage domains Download PDFInfo
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Abstract
The application discloses a level conversion circuit and electronic equipment with multiple voltage domains, which realize the design goals of high response speed of the level conversion circuit, low static power consumption and small layout area. The circuit includes: four inverters INV 1-INV 4, four N-type switch tubes MN 1-MN 4 and four P-type switch tubes MP 1-MP 4; the output of INV3 is connected with the input of INV4 and the control electrodes of MN1, MN3 and MP 3; the output of INV4 is connected with the control electrodes of MN2, MN4 and MP 4; the outputs of MN3 and MN4 are grounded; the output of MN1 is connected with the output of MP3 and the input of MN 3; the output of MN2 is connected with the output of MP4 and the input of MN 4; the input of the MP3 and the MP4 is connected with low voltage; the input of the MP2 and the MP1 is connected with high voltage; MN1, MN2, MP1 and MP2 constitute pseudo-differential input and output; the output of MP2 is connected to the input of INV2 via INV 1.
Description
Technical Field
The present invention relates to the field of power electronics technologies, and in particular, to a level shift circuit and an electronic device with multiple voltage domains.
Background
Electronic devices with multiple voltage domains typically use level shifting circuits to effect the conversion of low voltage domain signals to high voltage domain signals. Specifically, in an electronic device with multiple voltage domains with large-scale digital-analog mixing, a digital module and an analog module usually correspond to different power voltages, and the magnitudes of the power voltages may be different, for example, the core voltage of the digital module is usually lower than 1V, but more analog modules are usually higher power voltages; the digital module and the analog module have data interaction, so the importance of the level conversion circuit is increasing, and the level conversion circuit is widely applied to various interface circuits and input/output units to realize the logic conversion of the level.
In the conventional level conversion circuit, the problem that the NMOS cannot be fully driven exists in a lower digital power supply signal VDDL, so that the level inversion speed is lower, and the output level of a high-voltage domain cannot be effectively inverted along with the input level. In order to improve the product competitiveness, electronic equipment with multiple voltage domains has higher requirements on the response speed, the static power consumption, the layout area and the like of the level conversion circuit, so that the level conversion circuit with high response speed, low static power consumption and small layout area needs to be designed.
Disclosure of Invention
In view of this, the present invention provides a level shift circuit and an electronic device with multiple voltage domains, so as to achieve the design objectives of fast response speed, low static power consumption and small layout area of the level shift circuit.
A level shifting circuit, comprising: a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a first N-type switch tube MN1, a second N-type switch tube MN2, a third N-type switch tube MN3, a fourth N-type switch tube MN4, a first P-type switch tube MP1, a second P-type switch tube MP2, a third P-type switch tube MP3 and a fourth P-type switch tube MP 4;
the third inverter INV3 and the fourth inverter INV4 are both powered by a first voltage VDDL, and the first inverter INV1 and the second inverter INV2 are both powered by a second voltage VDDH; the first voltage VDDL is less than the second voltage VDDH;
the output end of the third inverter INV3 is connected to the input end of the fourth inverter INV4, the control electrode of the first N-type switching tube MN1, the control electrode of the third N-type switching tube MN3 and the control electrode of the third P-type switching tube MP 3;
the output end of the fourth inverter INV4 is connected to the control electrode of the second N-type switch tube MN2, the control electrode of the fourth N-type switch tube MN4 and the control electrode of the fourth P-type switch tube MP 4;
the current output electrodes of the third N-type switch tube MN3 and the fourth N-type switch tube MN4 are both grounded;
the current output pole of the first N-type switch tube MN1 is connected with the current output pole of the third P-type switch tube MP3 and the current input pole of the third N-type switch tube MN 3;
the current output pole of the second N-type switch tube MN2 is connected to the current output pole of the fourth P-type switch tube MP4 and the current input pole of the fourth N-type switch tube MN 4;
the current input electrodes of the third P-type switch tube MP3 and the fourth P-type switch tube MP4 are both connected to the first voltage VDDL;
the current input pole of the first N-type switch tube MN1 is connected with the current output pole of the second P-type switch tube MP2 and the control pole of the first P-type switch tube MP 1;
the current input electrode of the second N-type switch tube MN2 is connected with the control electrode of the second P-type switch tube MP2 and the current output electrode of the first P-type switch tube MP 1;
the current input electrodes of the second P-type switch tube MP2 and the first P-type switch tube MP1 are both connected to the second voltage VDDH;
the output end of the first inverter INV1 is connected with the input end of the second inverter INV 2;
the input end of the first inverter INV1 is connected with the current output electrode of the second P-type switch tube MP 2;
the input of the third inverter INV3 is the control level VIN of the level shift circuit, and the output of the second inverter INV2 is the output VOUT of the level shift circuit.
Optionally, the width-to-length ratios of the first N-type switch tube MN1, the second N-type switch tube MN2, the first P-type switch tube MP1 and the second P-type switch tube MP2 satisfy that, in addition to the requirements that the width-to-length ratios of the first N-type switch tube MN1 and the second N-type switch tube MN2 are equal, and the width-to-length ratios of the first P-type switch tube MP1 and the second P-type switch tube MP2 are equal, the following requirements are also satisfied:
the current flowing after the first N-type switch tube MN1 is turned on is greater than the current flowing after the second P-type switch tube MP2 is turned on, and/or the gain of the positive feedback structure formed by the first P-type switch tube MP1 and the second P-type switch tube MP2 to the gate-to-drain voltage amplification of the first N-type switch tube MN1 exceeds a first preset value.
Optionally, the input end of the first inverter INV1 is connected to the current output electrode of the second P-type switch MP2, and is replaced by:
the input end of the first inverter INV1 is connected to the current output electrode of the first P-type switch MP 1.
Optionally, the threshold voltages of the third N-type switching tube MN3 and the fourth N-type switching tube MN4 are both smaller than the second preset value.
Optionally, any N-type switching tube in the level conversion circuit is an N-type MOSFET, an N-type IGBT, or an NPN triode.
Optionally, any P-type switching tube in the level conversion circuit is a P-type MOSFET, a P-type IGBT, or a PNP triode.
Optionally, any one of the inverters in the level shift circuit is a CMOS inverter.
An electronic device of multiple voltage domains comprising any of the level shifting circuits disclosed above.
It can be seen from the above technical solutions that the present invention can realize the conversion from the low voltage domain signal VDDL to the high voltage domain signal VDDH by controlling the low/high level switching of the level VIN. In addition, one of the left branch and the right branch is kept to be disconnected at any time, so that the static loss of the level conversion circuit is reduced. In addition, in the invention, the MN3 and the MP3 in the left branch form an inverter, so that the driving capability of MN1 is improved, and the MN4 and the MP4 in the right branch form an inverter, so that the driving capability of MN2 is improved, so that the drains of MN1 and MN2 can quickly respond to signal change, the signal transmission delay is reduced, and the level conversion speed of the level conversion circuit is improved. Moreover, the circuit of the invention has simple structure and small layout area.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of a level shift circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another level shifter circuit according to an embodiment of the present invention;
FIG. 3 is a waveform diagram illustrating simulation of the level shift circuit shown in FIG. 1;
FIG. 4 is a schematic diagram of an inverter circuit according to an embodiment of the present invention;
fig. 5 is a schematic circuit diagram of another inverter according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, an embodiment of the present invention discloses a level shift circuit, including: a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a first N-type switch tube MN1, a second N-type switch tube MN2, a third N-type switch tube MN3, a fourth N-type switch tube MN4, a first P-type switch tube MP1, a second P-type switch tube MP2, a third P-type switch tube MP3 and a fourth P-type switch tube MP 4;
the third inverter INV3 and the fourth inverter INV4 are powered by the first voltage VDDL, and the first inverter INV1 and the second inverter INV2 are powered by the second voltage VDDH; the reference ground voltage (i.e., zero voltage) < the first voltage VDDL < the second voltage VDDH, e.g., VDDL 1.1V and VDDH 5V are set
The switch tube is divided into an N-type switch tube and a P-type switch tube; whether the N-type switch tube or the P-type switch tube is provided with three pins, namely a control electrode, a current input electrode and a current output electrode;
the output end of the third inverter INV3 is connected to the input end of the fourth inverter INV4, the control electrode of the first N-type switching tube MN1, the control electrode of the third N-type switching tube MN3 and the control electrode of the third P-type switching tube MP 3;
the output end of the fourth inverter INV4 is connected to the control electrode of the second N-type switch tube MN2, the control electrode of the fourth N-type switch tube MN4 and the control electrode of the fourth P-type switch tube MP 4;
the current output electrodes of the third N-type switch tube MN3 and the fourth N-type switch tube MN4 are both grounded;
the current output pole of the first N-type switch tube MN1 is connected with the current output pole of the third P-type switch tube MP3 and the current input pole of the third N-type switch tube MN 3;
the current output pole of the second N-type switch tube MN2 is connected to the current output pole of the fourth P-type switch tube MP4 and the current input pole of the fourth N-type switch tube MN 4;
the current input electrodes of the third P-type switch tube MP3 and the fourth P-type switch tube MP4 are both connected to the first voltage VDDL;
the current input pole of the first N-type switch tube MN1 is connected with the current output pole of the second P-type switch tube MP2 and the control pole of the first P-type switch tube MP 1;
the current input electrode of the second N-type switch tube MN2 is connected with the control electrode of the second P-type switch tube MP2 and the current output electrode of the first P-type switch tube MP 1;
the current input electrodes of the second P-type switch tube MP2 and the first P-type switch tube MP1 are both connected to a second voltage VDDH;
the output end of the first inverter INV1 is connected with the input end of the second inverter INV 2;
the input end of the first inverter INV1 is connected with the current output electrode of the second P-type switch tube MP 2;
the input of the third inverter INV3 is the control level VIN of the level shift circuit, and the output of the second inverter INV2 is the output VOUT of the level shift circuit.
Optionally, any N-type switching tube in the circuit shown in fig. 1 may be an N-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), may also be an N-type IGBT (Insulated Gate Bipolar Transistor), may also be an NPN Transistor, and is not limited. Any P-type switching tube in the circuit shown in fig. 1 may be a P-type MOSFET, a P-type IGBT, or a PNP triode, without limitation.
When the N-type switch tube is an N-type MOSFET, the current input electrode of the N-type switch tube is a drain electrode, the current output electrode of the N-type switch tube is a source electrode, and the control electrode of the N-type switch tube is a gate electrode. When the N-type switching tube is an N-type IGBT, the current input electrode of the N-type switching tube is a collector electrode, the current output electrode of the N-type switching tube is an emitter electrode, and the control electrode of the switching tube is a grid electrode. When the N-type switching tube is an NPN transistor, the current input terminal of the N-type switching tube is a collector, the current output terminal of the N-type switching tube is an emitter, and the control terminal of the N-type switching tube is a base.
When the P-type switch tube is a P-type MOSFET, the current input electrode of the P-type switch tube is a source electrode, the current output electrode of the P-type switch tube is a drain electrode, and the control electrode of the P-type switch tube is a grid electrode. When the P-type switching tube is a P-type IGBT, the current input electrode of the P-type switching tube is an emitting electrode, the current output electrode of the P-type switching tube is a collecting electrode, and the control electrode of the P-type switching tube is a grid electrode. When the P-type switch tube is a PNP triode, the current input electrode of the P-type switch tube is an emitting electrode, the current output electrode of the P-type switch tube is a collecting electrode, and the control electrode of the P-type switch tube is a base electrode.
The working principle of the circuit shown in fig. 1 will be described in detail below by taking only the example that each N-type switch tube in the circuit shown in fig. 1 is an N-type MOSFET (NMOS tube for short) and each P-type switch tube is a P-type MOSFET (PMOS tube for short):
the switching state of a MOSFET is mainly determined by the gate-source voltage. The NMOS tube is conducted when the grid-source voltage is larger than a certain value (the value is called as threshold voltage); the conventional connection method is to make the source of the NMOS tube directly grounded and the gate apply high level, so as to make the NMOS tube conducted. The PMOS tube is conducted when the grid-source voltage is smaller than a certain value; the conventional connection method is to make the source of the PMOS tube directly connected with a power supply and apply low level to the grid, thereby making the PMOS tube conducted. The circuits shown in fig. 1 have conventional connections for the MOSFETs except for MN1 and MN 2.
The circuit shown in fig. 1 is divided into two symmetrical branches, namely a left branch where MN1 is located and a right branch where MN2 is located. When the control level VIN is switched from the high level to the low level, the third inverter INV3 outputs the high level, and the fourth inverter INV4 outputs the low level, at which time:
for the right branch, MN4 is turned off and MP4 is turned on, and at this time, the source voltage of MN2 is raised from zero voltage to low voltage VDDL instantaneously, so that the gate-source voltage of MN2 is reduced to a larger magnitude under the current connection method compared to when MN2 adopts the conventional connection method, so that the difference between the gate-source voltage of MN2 and the threshold voltage of MN2 is larger, and MN2 is turned off more completely (i.e., there is no possibility that MN2 cannot be turned off completely);
for the left branch, MN3 and MN1 are turned on and MP3 is turned off, the drain of MP2 is low, and the output VOUT of the level shifter circuit is low VDDL.
When the control level VIN is switched from low level to high level, the third inverter INV3 outputs low level, and the fourth inverter INV4 outputs high level, in which case:
for the left branch, MN3 is turned off and MP3 is turned on, and at this time, the source voltage of MN1 is raised from zero voltage to low voltage VDDL instantaneously, so that compared with the case where MN1 adopts a conventional connection, the gate-source voltage of MN1 under the current connection is reduced to a larger magnitude, so that the difference between the gate-source voltage of MN1 and the threshold voltage of MN1 is larger, and MN1 is turned off more completely (i.e., there is no possibility that MN1 cannot be turned off completely);
for the right branch, MN4 and MN2 are turned on and MP4 is turned off, at which time MP2 is turned on, the drain of MP2 flips from zero voltage to high voltage VDDH, and the output VOUT of the level shifter circuit is high voltage VDDH.
It can be seen that the conversion of the low voltage domain signal VDDL to the high voltage domain signal VDDH can be achieved by controlling the low/high level switching of the level VIN. In addition, one of the left branch and the right branch is kept to be disconnected at any time, so that the static loss of the level conversion circuit is reduced. In addition, the circuit shown in fig. 1 has a simple structure, so the layout area is small.
In addition, in the circuit shown in fig. 1, MN3 and MP3 form an inverter, so that the driving capability of MN1 is improved, and MN4 and MP4 form an inverter, so that the driving capability of MN2 is improved, so that the drains of MN1 and MN2 can respond to signal changes quickly, the delay of signal transmission is reduced, and the level conversion speed of the level conversion circuit is improved.
As can be seen from the above description, the embodiment of the present invention can realize the conversion of the low voltage domain signal VDDL to the high voltage domain signal VDDH by controlling the low/high level switching of the level VIN. In addition, one of the left branch and the right branch is kept disconnected at any time, so that the static loss of the level conversion circuit is reduced. In addition, in the embodiment of the invention, the MN3 and the MP3 form an inverter, so that the driving capability of the MN1 is improved, and meanwhile, the MN4 and the MP4 form an inverter, so that the driving capability of the MN2 is improved, so that the drains of the MN1 and the MN2 can quickly respond to signal changes, and the level conversion speed of the level conversion circuit is improved. In addition, the circuit of the embodiment of the invention has simple structure and small layout area.
In addition, in the circuit shown in fig. 1, MN1, MN2, MP1, and MP2 constitute pseudo-differential input and output, conductive carriers in the structure are mainly electrons, mobility is high, and the time for the drain voltage to flip from low level to high level or from high level to low level when the MOSFET is turned on can be shortened. In this structure, when MP2 is turned on, the gate-source voltage of MP2 is large, the current is large, and it is necessary to limit, that is, it is necessary to ensure the current I flowing after MN1 is turned onMN>Current I flowing after MP2 is turned onMPOtherwise, it may cause the drain voltage of MP2 to flip from 0 to VDDH without passing or increase the delay of level flip.
Known as IMPAnd IMNThe expression of (c) is as follows:
in the formula upRepresents the electron mobility, C, of MP2oxDenotes the gate capacitance, WPWidth, L, of the conduction channel of MP2PLength, V, of the conduction channel representing MP2thpDenotes the threshold voltage, u, of MP2nRepresents the electron mobility, W, of MN1nWidth, L, of the conductive channel representing MN1nDenotes the length, V, of the conduction channel of MN1thnRepresenting the threshold voltage of MN 1.
From IMPAnd IMNTo ensure IMN>IMPThe width-to-length ratio (W/L) of MP2 needs to be reduced to limit IMNAt the same time, the width-length ratio of MN1 needs to be increased to strengthen IMN. Therefore, in the circuit shown in fig. 1, the embodiment of the present invention recommends that the width-to-length ratio of MN1 and MP2 in the structure is reasonably set, so as to further reduce the delay of signal transmission and improve the level conversion speed of the level conversion circuit.
Considering circuit symmetry, the width-to-length ratio of MN1 coincides with the width-to-length ratio of MN2, and the width-to-length ratio of MP1 coincides with the width-to-length ratio of MP2 in design.
In addition, the cross-coupling connection of MP1 and MP2 in the circuit shown in FIG. 1 forms a positive feedback structure, which can quickly amplify the gate-to-drain voltages of MN1 and MN 2. Taking MN1 as an example, the gate-to-drain voltage gain of MN1
gmn1Is the transconductance, gm, of MN1p1Is the transconductance of the MP1,
Vgsnis the gate-source voltage, V, of MN1gspIs the gate-source voltage of MP 1. Since MP1 selects a smaller width-to-length ratio and MN1 selects a larger width-to-length ratio, the voltage gain A can be increasedVThereby improving the level conversion speed of the level conversion circuit.
To sum up, the embodiment of the present invention preferably provides that the width-to-length ratios of the first N-type switching tube MN1, the second N-type switching tube MN2, the first P-type switching tube MP1 and the second P-type switching tube MP2 satisfy, in addition to the requirements that the width-to-length ratios of the first N-type switching tube MN1 and the second N-type switching tube MN2 are equal, and the width-to-length ratios of the first P-type switching tube MP1 and the second P-type switching tube MP2 are equal: the current flowing after the first N-type switch tube MN1 is turned on is greater than the current flowing after the second P-type switch tube MP2 is turned on, and/or the gain of the positive feedback structure formed by the first P-type switch tube MP1 and the second P-type switch tube MP2 to the gate-to-drain voltage amplification of the first N-type switch tube MN1 exceeds a first preset value.
Taking the circuit shown in fig. 1 as a 1.1V to 5V level conversion circuit and VIN as a square wave signal as an example, the simulation waveforms of the control level VIN, the output VOUT, the first voltage VDDL and the second voltage VDDH of the 1.1V to 5V level conversion circuit are respectively shown in fig. 2. As can be seen from fig. 2, VOUT quickly follows VIN when VIN becomes high, and the rise time is very short; VOUT quickly goes from high to low when VIN switches to low.
Optionally, based on any of the embodiments disclosed above, the embodiment of the present invention recommends that the threshold voltages of MN3 and MN4 are both set to be relatively low (lower than a second preset value, and the second preset value takes values according to a required level shift speed on the premise of not affecting the normal operation of the circuit), so that the drains of MN3 and MN4 can further respond to signal changes quickly, the delay of signal transmission is reduced, and the level shift speed of the level shift circuit is increased.
Optionally, based on any of the embodiments disclosed above, the embodiments of the present invention recommend that the sizes of the MOS transistors in the first inverter INV1, the second inverter INV2, the third inverter INV3, and the fourth inverter INV4 are all smaller, so as to further reduce the layout area of the entire level shifter circuit. Optionally, the embodiment of the invention recommends the MP3 and the MP4 to avoid using a larger width-to-length ratio, thereby further saving the layout area.
Fig. 2 discloses yet another level shifting circuit, which differs from the circuit shown in fig. 1 in that: the input end of the first inverter INV1 in the circuit shown in fig. 1 is connected to the current output pole of the second P-type switch MP2, instead of: the input end of the first inverter INV1 is connected to the current output electrode of the first P-type switch MP 1. Then, when VIN becomes low, VOUT quickly follows VIN to high, and the rise time is very short; VOUT quickly goes from high to low when VIN switches to high. The working principle of the circuit can be obtained by the same method according to the working principle of the circuit shown in fig. 1, and the details are not repeated herein.
Optionally, based on any of the embodiments disclosed above, any one of the inverters may adopt a CMOS inverter, and its circuit structure is as shown IN fig. 4 or fig. 5, and includes an N-type switch tube and a P-type switch tube, a current input electrode of the P-type switch tube is connected to a power supply (fig. 4 takes the power supply as VDDL for example, corresponding to INV3 and INV 4; fig. 5 takes the power supply as VDDH for example, corresponding to INV1 and INV2), a control electrode of the P-type switch tube and a control electrode of the N-type switch tube are connected together to serve as an input terminal IN of the inverter, a current output electrode of the P-type switch tube and a current input electrode of the N-type switch tube are connected together to serve as an output terminal OUT of the inverter, and a current output electrode of the N-type switch tube is grounded.
In addition, the embodiment of the invention also discloses electronic equipment with multiple voltage domains, which comprises: any of the level shifting circuits disclosed above.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The terms "first," "second," and the like in the description and in the claims, and in the drawings, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, identical element in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the embodiments. Thus, the present embodiments are not intended to be limited to the embodiments shown herein but are to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. A level shift circuit, comprising: the driving circuit comprises a first inverter (INV1), a second inverter (INV2), a third inverter (INV3), a fourth inverter (INV4), a first N-type switching tube (MN1), a second N-type switching tube (MN2), a third N-type switching tube (MN3), a fourth N-type switching tube (MN4), a first P-type switching tube (MP1), a second P-type switching tube (MP2), a third P-type switching tube (MP3) and a fourth P-type switching tube (MP 4);
the third inverter (INV3) and the fourth inverter (INV4) are both powered by a first Voltage (VDDL), and the first inverter (INV1) and the second inverter (INV2) are both powered by a second Voltage (VDDH); the first Voltage (VDDL) is less than the second Voltage (VDDH);
the output end of the third inverter (INV3) is connected with the input end of the fourth inverter (INV4), the control electrode of the first N-type switch tube (MN1), the control electrode of the third N-type switch tube (MN3) and the control electrode of the third P-type switch tube (MP 3);
the output end of the fourth inverter (INV4) is connected with the control electrode of the second N-type switching tube (MN2), the control electrode of the fourth N-type switching tube (MN4) and the control electrode of the fourth P-type switching tube (MP 4);
the current output poles of the third N-type switch tube (MN3) and the fourth N-type switch tube (MN4) are both grounded;
the current output pole of the first N-type switching tube (MN1) is connected with the current output pole of the third P-type switching tube (MP3) and the current input pole of the third N-type switching tube (MN 3);
the current output pole of the second N-type switching tube (MN2) is connected with the current output pole of the fourth P-type switching tube (MP4) and the current input pole of the fourth N-type switching tube (MN 4);
the current input poles of the third P-type switch tube (MP3) and the fourth P-type switch tube (MP4) are connected with the first Voltage (VDDL);
the current input pole of the first N-type switching tube (MN1) is connected with the current output pole of the second P-type switching tube (MP2) and the control pole of the first P-type switching tube (MP 1);
the current input pole of the second N-type switching tube (MN2) is connected with the control pole of the second P-type switching tube (MP2) and the current output pole of the first P-type switching tube (MP 1);
the current input poles of the second P-type switch tube (MP2) and the first P-type switch tube (MP1) are connected with the second Voltage (VDDH);
the output end of the first inverter (INV1) is connected with the input end of the second inverter (INV 2);
the input end of the first inverter (INV1) is connected with the current output electrode of the second P-type switch tube (MP 2);
the input of the third inverter (INV3) is the control level (VIN) of the level shift circuit, and the output of the second inverter (INV2) is the output VOUT of the level shift circuit.
2. The circuit of claim 1, wherein the width-to-length ratios of the first N-type switch transistor (MN1), the second N-type switch transistor (MN2), the first P-type switch transistor (MP1) and the second P-type switch transistor (MP2) satisfy the following requirements, in addition to the requirements that the width-to-length ratios of the first N-type switch transistor (MN1) and the second N-type switch transistor (MN2) are equal, and the width-to-length ratios of the first P-type switch transistor (MP1) and the second P-type switch transistor (MP2) are equal:
the current flowing after the first N-type switch tube (MN1) is conducted is larger than the current flowing after the second P-type switch tube (MP2) is conducted, and/or the gain of a positive feedback structure formed by the first P-type switch tube (MP1) and the second P-type switch tube (MP2) for amplifying the voltage from the grid electrode to the drain electrode of the first N-type switch tube (MN1) exceeds a first preset value.
3. The circuit according to claim 1 or 2, wherein the input terminal of the first inverter (INV1) is connected to the current output terminal of the second P-type switch tube (MP2), and is replaced by:
the input end of the first inverter (INV1) is connected with the current output pole of the first P-type switch tube (MP 1).
4. The circuit of claim 1 or 2, wherein the threshold voltages of the third N-type switch (MN3) and the fourth N-type switch (MN4) are both less than a second predetermined value.
5. The level shift circuit according to claim 1 or 2, wherein any N-type switch tube in the level shift circuit is an N-type MOSFET, an N-type IGBT or an NPN transistor.
6. The level shift circuit according to claim 1 or 2, wherein any P-type switch tube in the level shift circuit is a P-type MOSFET, a P-type IGBT or a PNP triode.
7. The level shift circuit according to claim 1 or 2, wherein any one of the inverters is a CMOS inverter.
8. An electronic device for multiple voltage domains, comprising: the level shift circuit as claimed in any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210318541.3A CN114629489B (en) | 2022-03-29 | Level conversion circuit and electronic equipment with multiple voltage domains |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210318541.3A CN114629489B (en) | 2022-03-29 | Level conversion circuit and electronic equipment with multiple voltage domains |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114629489A true CN114629489A (en) | 2022-06-14 |
| CN114629489B CN114629489B (en) | 2024-05-14 |
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| US20050088202A1 (en) * | 2003-10-23 | 2005-04-28 | Fujitsu Limited | Semiconductor integrated circuit and level conversion circuit |
| CN101110575A (en) * | 2007-07-03 | 2008-01-23 | 华为技术有限公司 | Processing method for output stage circuit, power amplification circuit and electrical signal |
| CN105515560A (en) * | 2016-01-27 | 2016-04-20 | 灿芯半导体(上海)有限公司 | Voltage conversion circuit |
| CN108415505A (en) * | 2012-09-04 | 2018-08-17 | 瑞萨电子株式会社 | Differential output circuit and semiconductor devices |
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| CN101110575A (en) * | 2007-07-03 | 2008-01-23 | 华为技术有限公司 | Processing method for output stage circuit, power amplification circuit and electrical signal |
| CN108415505A (en) * | 2012-09-04 | 2018-08-17 | 瑞萨电子株式会社 | Differential output circuit and semiconductor devices |
| CN105515560A (en) * | 2016-01-27 | 2016-04-20 | 灿芯半导体(上海)有限公司 | Voltage conversion circuit |
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