CN111641407B - Sectional type level conversion circuit, integrated chip and level conversion device - Google Patents
Sectional type level conversion circuit, integrated chip and level conversion device Download PDFInfo
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- CN111641407B CN111641407B CN202010651797.7A CN202010651797A CN111641407B CN 111641407 B CN111641407 B CN 111641407B CN 202010651797 A CN202010651797 A CN 202010651797A CN 111641407 B CN111641407 B CN 111641407B
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Abstract
The application discloses sectional type level shifter circuit includes: the first NMOS tube, the second NMOS tube and the first PMOS tube are sequentially connected between the grounding end and the first power supply voltage; the third NMOS tube and the second PMOS tube are connected between the grounding end and the second voltage power supply; and the source electrode is grounded, and the drain electrode and the grid electrode are respectively connected with the fourth NMOS tube of the drain electrode of the third NMOS tube. Because the circuit structure of the sectional level conversion circuit is arranged, the power supply domain of all MOS tubes is 1.8V, the components of advanced technology can be used for realizing high-voltage signal output of a higher voltage domain, high-voltage resistant components are not needed, the area is small, the cost is lower, and the application value is wider. Correspondingly, the application also discloses a sectional type level conversion integrated chip and a level conversion device with the same beneficial effects.
Description
Technical Field
The present invention relates to the field of electronic circuits and semiconductor designs, and more particularly, to a segmented level shifter, an integrated chip, and a level shifter.
Background
The level conversion circuit is used for converting a low-voltage control signal into a high-voltage control signal, so that the control of the low-voltage domain signal to the high-voltage domain driving circuit is realized, and the level conversion circuit is widely applied to the aspects of display of an LCD (Liquid Crystal Display ), an OLED (Organic Light-Emitting Diode) and the like.
With the improvement of the advanced technology, technicians try to improve the driving circuit of the high-voltage domain, and realize high-voltage resistance by using a low-voltage device, so that the cost of a chip is saved. However, the existing design is not completely separated from the requirement of high-voltage devices, and some circuits still require that the MOS tube must bear 3.3V withstand voltage, and the MOS tube cannot be applied to occasions with higher process requirements.
Therefore, how to provide a solution to the above technical problem is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the present invention is directed to a segmented level shifter, an integrated chip and a level shifter for realizing level shifting in a high voltage domain and high frequency by using a low voltage device. The specific scheme is as follows:
a segmented level shifter circuit comprising:
the source electrode is grounded, and the grid electrode is connected with a first NMOS tube of a first input signal;
the source electrode is connected with the drain electrode of the first NMOS tube, the grid electrode is connected with a preset voltage, and the drain electrode is used as a second NMOS tube of the first voltage output end;
the source electrode is connected with a first voltage power supply, and the drain electrode and the grid electrode are respectively connected with the first PMOS tube of the drain electrode of the second NMOS tube;
the source electrode is grounded, the grid electrode is connected with a second input signal, and the drain electrode is used as a third NMOS tube of the second voltage output end;
the source electrode is connected with a second voltage power supply, the grid electrode is connected with the second input signal, and the drain electrode is connected with the second PMOS tube;
a fourth NMOS tube with a source electrode grounded, a drain electrode and a grid electrode respectively connected with the drain electrode of the third NMOS tube;
the first input signal and the second input signal are in-phase or anti-phase, the first power supply voltage is 3.3V, the second power supply voltage is 1.8V, and the value range of the preset voltage is [1.5,1.8].
Preferably, the source electrode of the first NMOS tube is grounded through a first current source, and the internal current of the first current source flows from the source electrode of the first NMOS tube to the ground terminal;
the source electrode of the second PMOS tube is connected with the second voltage power supply through a second current source, and the internal current of the second current source flows to the source electrode of the second PMOS tube from the second voltage power supply.
Preferably, the size of the first PMOS and the current value of the first current source correspond to the voltage value of the first voltage output terminal.
Preferably, the size of the second PMOS, the size of the fourth NMOS, and the current value of the second current source correspond to the voltage value of the second voltage output terminal.
Preferably, the first input signal and the second input signal are high frequency signals.
Correspondingly, the invention also discloses a sectional type level conversion integrated chip, which comprises:
a segmented level-shifting circuit as claimed in any preceding claim.
Correspondingly, the invention also discloses a level conversion device, which comprises:
a segmented level-shifting circuit as claimed in any preceding claim;
and the driving circuit is connected with the first voltage output end and the second voltage output end of the sectional level conversion circuit.
Preferably, the first input signal and the second input signal of the segmented level-shift circuit are in phase, and the driving circuit includes:
the source electrode is connected with a first voltage power supply, and the grid electrode is connected with a first driving PMOS tube of the first voltage output end;
the source electrode is connected with the drain electrode of the first driving PMOS tube, the grid electrode is connected with a voltage division power supply, and the drain electrode is used as a second driving PMOS tube of a driving output voltage end;
the source electrode is grounded, and the grid electrode is connected with the first driving NMOS tube of the second voltage output end;
the source electrode is connected with the drain electrode of the first driving NMOS tube, the grid electrode is connected with the voltage division power supply, and the drain electrode is connected with the second driving NMOS tube.
Preferably, the voltage value of the divided power supply is 1.8V.
Preferably, the level shifting apparatus further comprises an initial shifting circuit for:
the level of the initial input signal is converted into levels corresponding to the first input signal and the second input signal.
The application discloses sectional type level shifter circuit includes: the source electrode is grounded, and the grid electrode is connected with a first NMOS tube of a first input signal; the source electrode is connected with the drain electrode of the first NMOS tube, the grid electrode is connected with a preset voltage, and the drain electrode is used as a second NMOS tube of the first voltage output end; the source electrode is connected with a first voltage power supply, and the drain electrode and the grid electrode are respectively connected with the first PMOS tube of the drain electrode of the second NMOS tube; the source electrode is grounded, the grid electrode is connected with a second input signal, and the drain electrode is used as a third NMOS tube of the second voltage output end; the source electrode is connected with a second voltage power supply, the grid electrode is connected with the second input signal, and the drain electrode is connected with the second PMOS tube; a fourth NMOS tube with a source electrode grounded, a drain electrode and a grid electrode respectively connected with the drain electrode of the third NMOS tube; the first input signal and the second input signal are in-phase or anti-phase, the first power supply voltage is 3.3V, the second power supply voltage is 1.8V, and the value range of the preset voltage is [1.5,1.8]. Because the circuit structure of the sectional level conversion circuit is arranged, the power supply domain of all MOS tubes is 1.8V, the components of advanced technology can be used for realizing high-voltage signal output of a higher voltage domain, high-voltage resistant components are not needed, the area is small, the cost is lower, and the application value is wider.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a diagram showing a block diagram of a sectional level shifter circuit according to an embodiment of the present invention;
FIG. 2 is a diagram showing a structure of a level shifter according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a level shifter according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the existing design, the driving circuit is not completely separated from the requirement of a high-voltage device, some circuits still require that MOS tubes bear 3.3V withstand voltage, and the MOS tubes cannot be applied to occasions with higher process requirements. The circuit structure of the sectional level conversion circuit is set, wherein the power supply domain of all MOS tubes is 1.8V, and the high-voltage signal output of a higher voltage domain can be realized by using components of an advanced process.
The embodiment of the invention discloses a sectional type level conversion circuit, which is shown in fig. 1 and comprises:
the source electrode is grounded, and the grid electrode is connected to the first NMOS tube MN1 of the first input signal vin 1;
the source electrode is connected with the drain electrode of the first NMOS tube MN1, the grid electrode is connected with a preset voltage VBP, and the drain electrode is used as a second NMOS tube MN2 of the first voltage output end vout 1;
the source electrode is connected with a first voltage power supply, and the drain electrode and the grid electrode are respectively connected with a first PMOS tube MP1 of the drain electrode of the second NMOS tube MN2;
the source electrode is grounded, the grid electrode is connected with a second input signal vin2, and the drain electrode is used as a third NMOS tube MN3 of a second voltage output end vout 2;
the source electrode is connected with a second voltage power supply, the grid electrode is connected with a second input signal vin2, and the drain electrode is connected with a second PMOS tube MP2 connected with the drain electrode of a third NMOS tube MN3;
a fourth NMOS tube MN4 with a grounded source, a drain and a gate connected with the drain of the third NMOS tube MN3 respectively;
the first input signal vin1 and the second input signal vin2 are in phase or in opposite phase, the first power voltage V1 is 3.3V, the circuit is usually denoted by AVDD33, the second power voltage V2 is 1.8V, the circuit is usually denoted by AVDD18, and the value range of the preset voltage VBP is [1.5,1.8].
It can be understood that the voltage settings of the first power supply voltage V1 and the second power supply voltage V2 provide the upper voltage limit for the first voltage output terminal vout1 and the second voltage output terminal vout2, and the value range of the preset voltage VBP is set, and is generally selected to be not more than the voltage withstand range of the MOS transistor, and the value range of the preset voltage VBP can be set to be between 1.5 and 1.8V for the MOS transistor with the voltage withstand of 1.8V in the 3.3V voltage range.
Specifically, since the first input signal vin1 is in phase or in phase opposition to the second input signal vin2, both are always synchronized, so that the output signals of the first voltage output terminal vout1 and the second voltage output terminal vout2 are also kept synchronized.
It can be understood that the frequency application range of the first input signal vin1 and the second input signal vin2 is wider, and the sectional level conversion circuit has better response effect when the first input signal vin1 and the second input signal vin2 are high-frequency signals.
In the prior art, due to the limitation of a circuit structure, the size of the MOS tube is large to realize high-speed overturning, and the size of the MOS tube limits the application of the MOS tube in high-frequency occasions. Therefore, in order to increase the response speed of the segmented level conversion circuit, a bias current is generally added, so that the segmented level conversion circuit has a very good application effect in the application field with higher frequency, the bias current is realized in the form of a first current source I1 and a second current source I2, specifically, the source electrode of the first NMOS tube MN1 is grounded through the first current source I1, and the internal current of the first current source I1 flows from the source electrode of the first NMOS tube MN1 to the grounding terminal; the source electrode of the second PMOS tube MP2 is connected with a second voltage power supply through a second current source I2, and the internal current of the second current source I2 flows to the source electrode of the second PMOS tube MP2 from the second voltage power supply.
Generally, the voltage domains of the first input signal vin1 and the second input signal vin2 are both 0-1.8V, and the following is a specific operation condition of the segmented level shifter circuit:
when the first input signal vin1 is 1.8V, the first NMOS transistor MN1 is turned on, the first PMOS transistor MP1 is in a saturated state, the voltage of the first voltage output terminal vout1 is rapidly charged by the first current source I1, and the specific voltage value is determined by the size of the first PMOS transistor MP1 and the current value of the first current source I1 together, that is, the voltage of the first voltage output terminal vout1 can be adjusted by using the size of the first PMOS transistor MP1 and the current value of the first current source I1, and at this time, the voltage of the first voltage output terminal vout1 is generally slightly greater than VBP, and is generally about 1.8V; when the first input signal vin1 is 0V, the first NMOS transistor NM1 is turned off, the first PMOS transistor MP1 is weakly pulled up to the first voltage source V1, that is, 3.3V, and the voltage of the first voltage output terminal vout1 is 3.3V.
When the second input signal vin2 is 1.8V, the third NMOS transistor MN3 is turned on, and the voltage of the second voltage output terminal vout2 is 0V; when the second input signal vin2 is 0V, the second PMOS transistor MP2 is turned on, the second voltage output terminal vout2 is charged rapidly, and the specific voltage value is determined by the size of the second PMOS transistor MP2, the size of the fourth NMOS transistor MN4, and the current value of the second current source I2, that is, the voltage of the second voltage output terminal vout2 can be adjusted by using the size of the second PMOS transistor MP2, the size of the fourth NMOS transistor MN4, and the current value of the second current source I2, and at this time, the voltage of the second voltage output terminal vout2 is generally lower than 1.8V, and is generally between 1 and 1.2V.
Analysis can be obtained, all MOS tubes in the embodiment can adopt elements with withstand voltage of 1.8V in advanced technology, and meanwhile, the level conversion of high-voltage segmentation is realized: the voltage domain of the first voltage output end vout1 is between 1.8 and 3.3V, the voltage domain of the second voltage output end vout2 is between 0 and 1.8V, wherein the first voltage output end vout1 and the second voltage output end vout2 are synchronous in output, so that the output levels of the two synchronous variable and different voltage domains can be output to a high-voltage-resistant driving circuit, and the driving circuit is further controlled.
The first current source I1 and the second current source I2 are used for fast charging, so as to support the fast inversion of the segmented level shifter circuit when the first input signal vin1 and the second input signal vin2 are high frequency.
Further, as can be obtained from the above analysis, the size of the first PMOS MP1 and the current value of the first current source I1 correspond to the voltage value of the first voltage output terminal vout 1; correspondingly, the size of the second PMOS MP2, the size of the fourth NMOS MN4, and the current value of the second current source I2 correspond to the voltage value of the second voltage output terminal vout 2. When the voltage values of the first voltage output terminal vout1 and the second voltage output terminal vout2 are adjusted, the sizes of the elements associated therewith can be adjusted.
Because the circuit structure of the sectional level conversion circuit is arranged, the power supply domain of all MOS tubes is 1.8V, the components of advanced technology can be used for realizing high-voltage signal output of a higher voltage domain, high-voltage resistant components are not needed, the area is small, the cost is lower, and the application value is wider.
Correspondingly, the embodiment of the invention also discloses a sectional type level conversion integrated chip, which comprises:
a segmented level shifter circuit as in any above.
For details about the segmented level shift circuit in this embodiment, reference may be made to the description in the above embodiment, and meanwhile, the segmented level shift integrated chip in this embodiment has the same technical effects as the segmented level shift circuit in the above embodiment, which is not described herein.
Correspondingly, the embodiment of the invention also discloses a level conversion device, which is shown in fig. 2 and comprises:
a segmented level shifter circuit 1 as in any one of the above;
and a driving circuit 2 connected to the first voltage output terminal vout1 and the second voltage output terminal vout2 of the segmented level shift circuit 1.
It will be appreciated that the driving circuit 2 herein is any driving circuit requiring two synchronized voltage segment input levels, and the specific circuit configuration is not limited. Referring to fig. 3, for example, the first input signal vin1 and the second input signal vin2 of the segmented level shift circuit are in phase, and the driving circuit 2 may include:
the source electrode is connected with a first voltage power supply V1, and the grid electrode is connected with a first driving PMOS tube MPd1 of a first voltage output end vout 1;
the source electrode is connected with the drain electrode of the first driving PMOS tube MPd1, the grid electrode is connected with the voltage division power supply V3, and the drain electrode is used as a second driving PMOS tube MPd2 for driving the output voltage end VO;
the source electrode is grounded, and the grid electrode is connected with the first driving NMOS tube MNd of the second voltage output end vout 2;
the source is connected to the drain of the first driving NMOS transistor MNd1, the gate is connected to the voltage dividing power source V3, and the drain is connected to the second driving NMOS transistor MNd of the drain of the second driving PMOS transistor MPd 2.
Specifically, the voltage value of the divided power supply is generally in the range of about 1.8V, and may be set to 1.8V directly.
As known from the above embodiment, when the first input signal vin1 and the second input signal vin2 of the segmented level shift circuit are in phase, the voltage of the first voltage output terminal vout1 is about 1.8V, the voltage of the second voltage output terminal vout2 is 0V, for the driving circuit 2 in fig. 3, the first driving PMOS transistor MP-d1 is turned on, the first driving NMOS transistor MN-d1 is turned off, and finally the driving circuit 2 outputs 3.3V; when the first input signal vin1 is 0V, the first driving PMOS transistor MP-d1 is turned off, the first NMOS transistor MN-d1 is turned on, and finally the driving circuit 2 outputs 0V.
Further, the level shifting apparatus further includes an initial shifting circuit 3 for:
the level of the initial input signal vin0 is converted into levels corresponding to the first input signal vin1 and the second input signal vin 2.
The initial conversion circuit 3 is suitable for the case that the initial level is different from the input level of the segmented level conversion circuit, for example, the voltage domain of the initial input signal vin0 is 0-0.8V, and the initial level can be converted into the first input signal vin1 and the second input signal vin2 with the voltage domain of 0-1.8V, and then the subsequent actions are performed, and the specific circuit structure of the initial conversion circuit 3 can be selected according to the actual situation, which is not limited herein.
In the embodiment, the conventional low-voltage components are adopted, so that the level conversion and the driving under a high-voltage domain are realized, the circuit and the device are small in size, the design cost is low, and the application value is wider.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above description of the present invention provides a sectional level conversion circuit, an integrated chip and a level conversion device, and specific examples are applied to illustrate the principles and embodiments of the present invention, and the above description of the embodiments is only used to help understand the method and core idea of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (10)
1. A segmented level shifter circuit, comprising:
the source electrode is grounded, and the grid electrode is connected with a first NMOS tube of a first input signal;
the source electrode is connected with the drain electrode of the first NMOS tube, the grid electrode is connected with a preset voltage, and the drain electrode is used as a second NMOS tube of the first voltage output end;
the source electrode is connected with a first voltage power supply, and the drain electrode and the grid electrode are respectively connected with the first PMOS tube of the drain electrode of the second NMOS tube;
the source electrode is grounded, the grid electrode is connected with a second input signal, and the drain electrode is used as a third NMOS tube of the second voltage output end;
the source electrode is connected with a second voltage power supply, the grid electrode is connected with the second input signal, and the drain electrode is connected with the second PMOS tube;
a fourth NMOS tube with a source electrode grounded, a drain electrode and a grid electrode respectively connected with the drain electrode of the third NMOS tube;
the first input signal is in phase or in opposite phase with the second input signal, the first voltage power supply is 3.3V, the second voltage power supply is 1.8V, and the value range of the preset voltage is [1.5,1.8].
2. The segmented level-shifting circuit of claim 1, wherein,
the source electrode of the first NMOS tube is grounded through a first current source, and the internal current of the first current source flows from the source electrode of the first NMOS tube to the grounding end;
the source electrode of the second PMOS tube is connected with the second voltage power supply through a second current source, and the internal current of the second current source flows to the source electrode of the second PMOS tube from the second voltage power supply.
3. The segmented level-shifting circuit of claim 2, wherein,
the size of the first PMOS tube and the current value of the first current source correspond to the voltage value of the first voltage output end.
4. The segmented level-shifting circuit of claim 2, wherein,
the size of the second PMOS, the size of the fourth NMOS, and the current value of the second current source correspond to the voltage value of the second voltage output terminal.
5. The segmented level-shift circuit of any one of claims 1-4, wherein the first input signal and the second input signal are high frequency signals.
6. A segmented level-shifting integrated chip, comprising:
a segmented level-shifting circuit as claimed in any one of claims 1 to 5.
7. A level shifter, comprising:
a segmented level-shifting circuit as claimed in any one of claims 1 to 5;
and the driving circuit is connected with the first voltage output end and the second voltage output end of the sectional level conversion circuit.
8. The level shifting apparatus of claim 7, wherein the first input signal and the second input signal of the segmented level shifting circuit are in phase, the driving circuit comprising:
the source electrode is connected with a first voltage power supply, and the grid electrode is connected with a first driving PMOS tube of the first voltage output end;
the source electrode is connected with the drain electrode of the first driving PMOS tube, the grid electrode is connected with a voltage division power supply, and the drain electrode is used as a second driving PMOS tube of a driving output voltage end;
the source electrode is grounded, and the grid electrode is connected with the first driving NMOS tube of the second voltage output end;
the source electrode is connected with the drain electrode of the first driving NMOS tube, the grid electrode is connected with the voltage division power supply, and the drain electrode is connected with the second driving NMOS tube.
9. The level shifter of claim 8, wherein the divided power supply has a voltage value of 1.8V.
10. The level shifting apparatus according to any one of claims 7 to 9, further comprising an initial shifting circuit for:
the level of the initial input signal is converted into levels corresponding to the first input signal and the second input signal.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5821799A (en) * | 1996-10-25 | 1998-10-13 | Cypress Semiconductor Corporation | Low voltage level shifting circuit and low voltage sense amplifier |
| US6114874A (en) * | 1998-05-11 | 2000-09-05 | National Semiconductor Corporation | Complementary MOS level translating apparatus and method |
| JP2000244305A (en) * | 1999-02-19 | 2000-09-08 | Matsushita Electric Ind Co Ltd | Level conversion circuit |
| CN109075783A (en) * | 2016-04-21 | 2018-12-21 | 株式会社索思未来 | Semiconductor integrated circuit |
| CN110729995A (en) * | 2019-11-28 | 2020-01-24 | 华中科技大学 | Level conversion circuit and level conversion method |
-
2020
- 2020-07-08 CN CN202010651797.7A patent/CN111641407B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5821799A (en) * | 1996-10-25 | 1998-10-13 | Cypress Semiconductor Corporation | Low voltage level shifting circuit and low voltage sense amplifier |
| US6114874A (en) * | 1998-05-11 | 2000-09-05 | National Semiconductor Corporation | Complementary MOS level translating apparatus and method |
| JP2000244305A (en) * | 1999-02-19 | 2000-09-08 | Matsushita Electric Ind Co Ltd | Level conversion circuit |
| CN109075783A (en) * | 2016-04-21 | 2018-12-21 | 株式会社索思未来 | Semiconductor integrated circuit |
| CN110729995A (en) * | 2019-11-28 | 2020-01-24 | 华中科技大学 | Level conversion circuit and level conversion method |
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