CN111641407A - Sectional type level conversion circuit, integrated chip and level conversion device - Google Patents
Sectional type level conversion circuit, integrated chip and level conversion device Download PDFInfo
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Abstract
The application discloses sectional type level conversion circuit includes: the first NMOS tube, the second NMOS tube and the first PMOS tube are sequentially connected between the grounding end and the first power supply voltage; the third NMOS tube and the second PMOS tube are connected between the grounding end and the second voltage power supply; and the source electrode is grounded, and the drain electrode and the grid electrode are respectively connected with the fourth NMOS tube of the drain electrode of the third NMOS tube. Because the circuit structure of the sectional level conversion circuit is arranged, wherein the power domains of all MOS tubes are at 1.8V, high-voltage signal output of a higher voltage domain can be realized by using components and parts of an advanced process, high-voltage resistant devices are not needed, the area is small, the cost is low, and the application value is wider. Correspondingly, the application also discloses a sectional type level conversion integrated chip and a level conversion device with the same beneficial effects.
Description
Technical Field
The present invention relates to the field of electronic circuit and semiconductor design, and in particular, to a segmented level shifter, an integrated chip, and a level shifter.
Background
The level shift circuit is used for converting a low-voltage control signal into a high-voltage control signal, so as to control the high-voltage domain driving circuit by the low-voltage domain signal, and is widely applied to the aspects of LCD (Liquid Crystal Display), OLED (Organic Light-Emitting Diode) Display, and the like.
With the advance degree of the process increasing, technicians try to improve a driving circuit of a high-voltage domain, and realize high-voltage resistance by using a low-voltage device, so that the cost of a chip is saved. However, the existing design does not completely depart from the requirement of high-voltage devices, some circuits still require that MOS transistors must bear the withstand voltage of 3.3V, and the MOS transistors cannot be applied to occasions with higher process requirements.
Therefore, how to provide a solution to the above technical problems is a problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the present invention provides a segmented level shifter, an integrated chip and a level shifter, which use low voltage devices to realize level shifting in high voltage domain and high frequency. The specific scheme is as follows:
a segmented level shifting circuit, comprising:
a first NMOS tube with a grounded source electrode and a grid electrode connected to a first input signal;
the source electrode of the second NMOS tube is connected with the drain electrode of the first NMOS tube, the grid electrode of the second NMOS tube is connected with a preset voltage, and the drain electrode of the second NMOS tube is used as a first voltage output end;
the source electrode is connected with a first voltage power supply, and the drain electrode and the grid electrode are respectively connected with the first PMOS tube of the drain electrode of the second NMOS tube;
a third NMOS tube with a grounded source electrode, a second input signal connected to the grid electrode and a second voltage output end serving as a drain electrode;
the source electrode of the second PMOS tube is connected with a second voltage power supply, the grid electrode of the second PMOS tube is connected with the second input signal, and the drain electrode of the second PMOS tube is connected with the drain electrode of the third NMOS tube;
a fourth NMOS tube with a grounded source electrode and a drain electrode and a grid electrode respectively connected with the drain electrode of the third NMOS tube;
the first input signal and the second input signal are in phase or in phase opposition, the first power supply voltage is 3.3V, the second power supply voltage is 1.8V, and the value range of the preset voltage is [1.5, 1.8 ].
Preferably, the source of the first NMOS transistor is grounded through a first current source, and an internal current of the first current source flows from the source of the first NMOS transistor to a ground terminal;
and the source electrode of the second PMOS tube is connected with the second voltage power supply through a second current source, and the internal current of the second current source flows to the source electrode of the second PMOS tube from the second voltage power supply.
Preferably, the size of the first PMOS transistor and the current value of the first current source correspond to the voltage value of the first voltage output terminal.
Preferably, the size of the second PMOS transistor, the size of the fourth NMOS transistor, and the current value of the second current source correspond to the voltage value of the second voltage output terminal.
Preferably, the first input signal and the second input signal are high frequency signals.
Correspondingly, the invention also discloses a sectional type level conversion integrated chip, which comprises:
a segmented level shifting circuit as claimed in any preceding claim.
Correspondingly, the invention also discloses a level conversion device, which comprises:
the segmented level shifting circuit of any of the above;
and the driving circuit is connected with the first voltage output end and the second voltage output end of the sectional type level conversion circuit.
Preferably, the first input signal and the second input signal of the segmented level shift circuit are in phase, and the driving circuit includes:
the source electrode of the first driving PMOS tube is connected with a first voltage power supply, and the grid electrode of the first driving PMOS tube is connected with the first voltage output end;
the source electrode is connected with the drain electrode of the first driving PMOS tube, the grid electrode is connected with a voltage division power supply, and the drain electrode is used as a second driving PMOS tube of a driving output voltage end;
the source electrode is grounded, and the grid electrode is connected with the first drive NMOS tube of the second voltage output end;
and the source electrode of the second drive NMOS tube is connected with the drain electrode of the first drive NMOS tube, the grid electrode of the second drive NMOS tube is connected with the voltage division power supply, and the drain electrode of the second drive PMOS tube is connected with the drain electrode of the first drive NMOS tube.
Preferably, the voltage value of the voltage division power supply is 1.8V.
Preferably, the level shifter further comprises an initial conversion circuit for:
converting a level of an initial input signal to a level corresponding to the first input signal and the second input signal.
The application discloses sectional type level conversion circuit includes: a first NMOS tube with a grounded source electrode and a grid electrode connected to a first input signal; the source electrode of the second NMOS tube is connected with the drain electrode of the first NMOS tube, the grid electrode of the second NMOS tube is connected with a preset voltage, and the drain electrode of the second NMOS tube is used as a first voltage output end; the source electrode is connected with a first voltage power supply, and the drain electrode and the grid electrode are respectively connected with the first PMOS tube of the drain electrode of the second NMOS tube; a third NMOS tube with a grounded source electrode, a second input signal connected to the grid electrode and a second voltage output end serving as a drain electrode; the source electrode of the second PMOS tube is connected with a second voltage power supply, the grid electrode of the second PMOS tube is connected with the second input signal, and the drain electrode of the second PMOS tube is connected with the drain electrode of the third NMOS tube; a fourth NMOS tube with a grounded source electrode and a drain electrode and a grid electrode respectively connected with the drain electrode of the third NMOS tube; the first input signal and the second input signal are in phase or in phase opposition, the first power supply voltage is 3.3V, the second power supply voltage is 1.8V, and the value range of the preset voltage is [1.5, 1.8 ]. Because the circuit structure of the sectional level conversion circuit is arranged, wherein the power domains of all MOS tubes are at 1.8V, high-voltage signal output of a higher voltage domain can be realized by using components and parts of an advanced process, high-voltage resistant devices are not needed, the area is small, the cost is low, and the application value is wider.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a block diagram of a sectional type level shift circuit according to an embodiment of the present invention;
FIG. 2 is a structural diagram of a level shifter according to an embodiment of the present invention;
fig. 3 is a structural distribution diagram of an embodiment of a level shifter according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the existing design, a driving circuit is not completely separated from the requirement of a high-voltage device, and some circuits still require MOS (metal oxide semiconductor) tubes to bear the withstand voltage of 3.3V, so that the MOS tubes cannot be applied to occasions with higher process requirements. And the circuit structure of the segmented level conversion circuit is arranged, wherein the power domains of all MOS tubes are at 1.8V, and high-voltage signal output of a higher voltage domain can be realized by using components and parts of an advanced process.
The embodiment of the invention discloses a sectional type level conversion circuit, which is shown in figure 1 and comprises the following components:
a first NMOS transistor MN1 with a grounded source and a gate connected to a first input signal vin 1;
a second NMOS transistor MN2 having a source connected to the drain of the first NMOS transistor MN1, a gate connected to a predetermined voltage VBP, and a drain serving as a first voltage output terminal vout 1;
a first PMOS transistor MP1 with a source connected to a first voltage source, a drain and a gate respectively connected to the drain of the second NMOS transistor MN 2;
a third NMOS transistor MN3 having a grounded source, a gate connected to the second input signal vin2, and a drain serving as the second voltage output terminal vout 2;
a second PMOS transistor MP2 having a source connected to a second voltage source, a gate connected to a second input signal vin2, and a drain connected to the drain of the third NMOS transistor MN 3;
a fourth NMOS transistor MN4 with a grounded source electrode, a drain electrode and a grid electrode connected with the drain electrode of the third NMOS transistor MN3 respectively;
the first input signal vin1 and the second input signal vin2 are in phase or in phase opposition, the first power supply voltage V1 is 3.3V, which is often represented by AVDD33 in the circuit, the second power supply voltage V2 is 1.8V, which is often represented by AVDD18 in the circuit, and the value range of the preset voltage VBP is [1.5, 1.8 ].
It can be understood that the voltage settings of the first power voltage V1 and the second power voltage V2 respectively provide upper voltage limits for the first voltage output terminal vout1 and the second voltage output terminal vout2, the value range of the preset voltage VBP is set to be generally not greater than the withstand voltage range of the MOS transistor, and the value range of the preset voltage VBP can be set to be between 1.5V and 1.8V in the voltage range of 3.3V for the MOS transistor with withstand voltage of 1.8V.
Specifically, since the first input signal vin1 is in phase or in anti-phase with the second input signal vin2, and they are always synchronized, the output signals of the first voltage output terminal vout1 and the second voltage output terminal vout2 are also synchronized.
It can be understood that the frequency application range of the first input signal vin1 and the second input signal vin2 is wide, and when the first input signal vin1 and the second input signal vin2 are high-frequency signals, the segmented level shift circuit has a better response effect.
In the prior art, due to the limitation of a circuit structure, the size of an MOS (metal oxide semiconductor) transistor must be large to realize high-speed inversion, and the size of the MOS transistor limits the application of the MOS transistor in high-frequency occasions. Therefore, in order to improve the response speed of the segmented level shift circuit, a bias current is usually added, which has a very good application effect in an application occasion with a higher frequency, the bias current is implemented in the form of a first current source I1 and a second current source I2, specifically, the source of the first NMOS transistor MN1 is grounded through the first current source I1, and the internal current of the first current source I1 flows from the source of the first NMOS transistor MN1 to the ground; the source of the second PMOS transistor MP2 is connected to the second voltage source via a second current source I2, and the internal current of the second current source I2 flows from the second voltage source to the source of the second PMOS transistor MP 2.
Generally, the voltage domains of the first input signal vin1 and the second input signal vin2 are both 0-1.8V, and the following is the specific operation of the segmented level shift circuit:
when the first input signal vin1 is 1.8V, the first NMOS transistor MN1 is turned on, the first PMOS transistor MP1 is in a saturation state, the voltage of the first voltage output terminal vout1 is rapidly charged by the first current source I1, and the specific voltage value is determined by the size of the first PMOS transistor MP1 and the current value of the first current source I1, that is, the voltage of the first voltage output terminal vout1 can be adjusted by the size of the first PMOS transistor MP1 and the current value of the first current source I1, and the voltage of the first voltage output terminal vout1 is generally slightly larger than VBP and is generally about 1.8V; when the first input signal vin1 is 0V, the first NMOS transistor NM1 is turned off, the first PMOS transistor MP1 is pulled up to the first voltage source V1, i.e., 3.3V, and the voltage at the first voltage output terminal vout1 is 3.3V.
When the second input signal vin2 is 1.8V, the third NMOS transistor MN3 is turned on, and the voltage of the second voltage output terminal vout2 is 0V; when the second input signal vin2 is 0V, the second PMOS transistor MP2 is turned on, and the second voltage output terminal vout2 is charged quickly, the specific voltage value is determined by the size of the second PMOS transistor MP2, the size of the fourth NMOS transistor MN4, and the current value of the second current source I2, that is, the voltage of the second voltage output terminal vout2 can be adjusted by the size of the second PMOS transistor MP2, the size of the fourth NMOS transistor MN4, and the current value of the second current source I2, and the voltage of the second voltage output terminal vout2 is generally lower than 1.8V, and generally ranges from 1V to 1.2V.
Analysis can show that all the MOS transistors in the embodiment can adopt elements with withstand voltage of 1.8V in the advanced technology, and simultaneously realize level conversion of high-voltage segmentation: the voltage domain of the first voltage output terminal vout1 is between 1.8V and 3.3V, the voltage domain of the second voltage output terminal vout2 is between 0V and 1.8V, wherein the outputs of the first voltage output terminal vout1 and the second voltage output terminal vout2 are synchronous, so that the output levels of two synchronously-changed and different voltage domains can be output to the high-voltage resistant driving circuit, and the driving circuit is further controlled.
The first current source I1 and the second current source I2 are used for fast charging, so as to support fast inversion of the segmented level shift circuit when the first input signal vin1 and the second input signal vin2 are high frequency in the present embodiment.
Further, from the above analysis, it can be found that the size of the first PMOS transistor MP1 and the current value of the first current source I1 correspond to the voltage value of the first voltage output terminal vout 1; accordingly, the size of the second PMOS transistor MP2, the size of the fourth NMOS transistor MN4, and the current value of the second current source I2 correspond to the voltage value of the second voltage output terminal vout 2. When the voltage values of the first voltage output terminal vout1 and the second voltage output terminal vout2 are adjusted, the sizes of the components associated therewith can be adjusted.
Because the circuit structure of the sectional level conversion circuit is arranged, wherein the power domains of all MOS tubes are at 1.8V, high-voltage signal output of a higher voltage domain can be realized by using components and parts of an advanced process, high-voltage resistant devices are not needed, the area is small, the cost is low, and the application value is wider.
Correspondingly, the embodiment of the invention also discloses a sectional type level conversion integrated chip, which comprises:
such as any of the segmented level shifting circuits described above.
For details of the segmented level shift circuit in this embodiment, reference may be made to the description in the above embodiments, and meanwhile, the segmented level shift integrated chip in this embodiment has the same technical effect as the segmented level shift circuit in the above embodiments, and details are not described here again.
Correspondingly, the embodiment of the present invention further discloses a level shifter, as shown in fig. 2, including:
the segmented level shifting circuit 1 as any one of the above;
and the driving circuit 2 is connected with the first voltage output end vout1 and the second voltage output end vout2 of the segmented level shift circuit 1.
It is understood that the driving circuit 2 is any driving circuit requiring two synchronized voltage segment input levels, and the specific circuit structure is not limited. For example, referring to fig. 3, the first input signal vin1 and the second input signal vin2 of the segmented level shift circuit are in phase, and the driving circuit 2 may include:
the first driving PMOS transistor MPd1 is connected with the source electrode of the first voltage source V1 and the grid electrode of the first driving PMOS transistor MPd is connected with the first voltage output end vout 1;
the source electrode of the second driving PMOS tube MPd2 is connected with the drain electrode of the first driving PMOS tube MPd1, the grid electrode of the second driving PMOS tube MPd1 is connected with the voltage dividing power supply V3, and the drain electrode of the second driving PMOS tube MPd2 is used as a driving output voltage end VO;
a first driving NMOS tube MNd1 having a grounded source and a gate connected to the second voltage output terminal vout 2;
a second driving NMOS tube MNd2 having a source connected to the drain of the first driving NMOS tube MNd1, a gate connected to the voltage-dividing power source V3, and a drain connected to the drain of the second driving PMOS tube MPd 2.
Specifically, the voltage value of the voltage-dividing power supply is generally in the range of about 1.8V, and can be directly set to 1.8V.
As known from the above embodiments, when the first input signal vin1 and the second input signal vin2 of the segmented level shift circuit are in phase and the first input signal vin1 is 1.8V, the voltage of the first voltage output terminal vout1 is about 1.8V, the voltage of the second voltage output terminal vout2 is 0V, for the driving circuit 2 in fig. 3, the first driving PMOS transistor MP-d1 is turned on, the first driving NMOS transistor MN-d1 is turned off, and finally the driving circuit 2 outputs 3.3V; when the first input signal vin1 is 0V, the first driving PMOS transistor MP-d1 is turned off, the first NMOS transistor MN-d1 is turned on, and finally the driving circuit 2 outputs 0V.
Further, the level shifter includes an initial converting circuit 3 for:
the level of the initial input signal vin0 is converted to a level corresponding to the first input signal vin1 and the second input signal vin 2.
The initial converting circuit 3 is suitable for the case that the initial level is different from the input level of the segmented level converting circuit, for example, the initial input signal vin0 has a voltage range of 0-0.8V, and can be converted into the first input signal vin1 and the second input signal vin2 of 0-1.8V, and then the subsequent operations are performed, and the specific circuit structure of the initial converting circuit 3 can be selected according to the actual situation, which is not limited herein.
The conventional low-voltage component is adopted in the embodiment, level conversion and driving under a high-voltage domain are realized, the size of the circuit and the device is small, the design cost is low, and the circuit and the device have wider application value.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The present invention provides a segmented level shifter, an integrated chip and a level shifter, which are described in detail above, and the principle and the implementation of the present invention are explained in this document by applying specific examples, and the description of the above embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A segmented level shift circuit, comprising:
a first NMOS tube with a grounded source electrode and a grid electrode connected to a first input signal;
the source electrode of the second NMOS tube is connected with the drain electrode of the first NMOS tube, the grid electrode of the second NMOS tube is connected with a preset voltage, and the drain electrode of the second NMOS tube is used as a first voltage output end;
the source electrode is connected with a first voltage power supply, and the drain electrode and the grid electrode are respectively connected with the first PMOS tube of the drain electrode of the second NMOS tube;
a third NMOS tube with a grounded source electrode, a second input signal connected to the grid electrode and a second voltage output end serving as a drain electrode;
the source electrode of the second PMOS tube is connected with a second voltage power supply, the grid electrode of the second PMOS tube is connected with the second input signal, and the drain electrode of the second PMOS tube is connected with the drain electrode of the third NMOS tube;
a fourth NMOS tube with a grounded source electrode and a drain electrode and a grid electrode respectively connected with the drain electrode of the third NMOS tube;
the first input signal and the second input signal are in phase or in phase opposition, the first power supply voltage is 3.3V, the second power supply voltage is 1.8V, and the value range of the preset voltage is [1.5, 1.8 ].
2. The segmented level shifting circuit of claim 1,
the source electrode of the first NMOS tube is grounded through a first current source, and the internal current of the first current source flows to the ground end from the source electrode of the first NMOS tube;
and the source electrode of the second PMOS tube is connected with the second voltage power supply through a second current source, and the internal current of the second current source flows to the source electrode of the second PMOS tube from the second voltage power supply.
3. The segmented level shifting circuit of claim 2,
the size of the first PMOS tube and the current value of the first current source correspond to the voltage value of the first voltage output end.
4. The segmented level shifting circuit of claim 2,
the size of the second PMOS tube, the size of the fourth NMOS tube and the current value of the second current source correspond to the voltage value of the second voltage output end.
5. The segmented level shifting circuit of any of claims 1 to 4, wherein the first input signal and the second input signal are high frequency signals.
6. A segmented level shifting integrated chip, comprising:
the segmented level shifting circuit of any of claims 1 to 5.
7. A level shifting apparatus, comprising:
the segmented level shifting circuit of any of claims 1 to 5;
and the driving circuit is connected with the first voltage output end and the second voltage output end of the sectional type level conversion circuit.
8. The level shifting apparatus of claim 7, wherein the first and second input signals of the segmented level shifting circuit are in phase, and wherein the driving circuit comprises:
the source electrode of the first driving PMOS tube is connected with a first voltage power supply, and the grid electrode of the first driving PMOS tube is connected with the first voltage output end;
the source electrode is connected with the drain electrode of the first driving PMOS tube, the grid electrode is connected with a voltage division power supply, and the drain electrode is used as a second driving PMOS tube of a driving output voltage end;
the source electrode is grounded, and the grid electrode is connected with the first drive NMOS tube of the second voltage output end;
and the source electrode of the second drive NMOS tube is connected with the drain electrode of the first drive NMOS tube, the grid electrode of the second drive NMOS tube is connected with the voltage division power supply, and the drain electrode of the second drive PMOS tube is connected with the drain electrode of the first drive NMOS tube.
9. The apparatus of claim 8, wherein the voltage of the divided power supply has a value of 1.8V.
10. The level shifter according to any one of claims 7 to 9, further comprising an initial shift circuit for:
converting a level of an initial input signal to a level corresponding to the first input signal and the second input signal.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5821799A (en) * | 1996-10-25 | 1998-10-13 | Cypress Semiconductor Corporation | Low voltage level shifting circuit and low voltage sense amplifier |
| US6114874A (en) * | 1998-05-11 | 2000-09-05 | National Semiconductor Corporation | Complementary MOS level translating apparatus and method |
| JP2000244305A (en) * | 1999-02-19 | 2000-09-08 | Matsushita Electric Ind Co Ltd | Level conversion circuit |
| CN109075783A (en) * | 2016-04-21 | 2018-12-21 | 株式会社索思未来 | Semiconductor integrated circuit |
| CN110729995A (en) * | 2019-11-28 | 2020-01-24 | 华中科技大学 | Level conversion circuit and level conversion method |
-
2020
- 2020-07-08 CN CN202010651797.7A patent/CN111641407B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5821799A (en) * | 1996-10-25 | 1998-10-13 | Cypress Semiconductor Corporation | Low voltage level shifting circuit and low voltage sense amplifier |
| US6114874A (en) * | 1998-05-11 | 2000-09-05 | National Semiconductor Corporation | Complementary MOS level translating apparatus and method |
| JP2000244305A (en) * | 1999-02-19 | 2000-09-08 | Matsushita Electric Ind Co Ltd | Level conversion circuit |
| CN109075783A (en) * | 2016-04-21 | 2018-12-21 | 株式会社索思未来 | Semiconductor integrated circuit |
| CN110729995A (en) * | 2019-11-28 | 2020-01-24 | 华中科技大学 | Level conversion circuit and level conversion method |
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