CN106200741A - Electric current sinks load circuit and low pressure difference linear voltage regulator - Google Patents
Electric current sinks load circuit and low pressure difference linear voltage regulator Download PDFInfo
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- CN106200741A CN106200741A CN201610596446.4A CN201610596446A CN106200741A CN 106200741 A CN106200741 A CN 106200741A CN 201610596446 A CN201610596446 A CN 201610596446A CN 106200741 A CN106200741 A CN 106200741A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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Abstract
The invention provides a kind of electric current and sink load circuit and low pressure difference linear voltage regulator, described low pressure difference linear voltage regulator includes: a bandgap reference circuit, an amplifier, 1 the 12nd MOS transistor, one second resistance, one the 3rd resistance, one first electric capacity and an electric current sink load circuit, described electric current sinks load circuit and is parallel to the two ends of a load, one end of described load is connected to the drain electrode of described 12nd MOS transistor, other end ground connection.When described low pressure difference linearity wave filter is when carrying out pattern switching, described electric current is utilized to sink load circuit to reduce the frequency of the total load current of described low pressure difference linearity wave filter, make described low pressure difference linear voltage regulator have enough time to respond, also will not waste too much electric current simultaneously, save power consumption.
Description
Technical field
The present invention relates to technical field of semiconductors, especially a kind of electric current sinks load circuit and low pressure difference linear voltage regulator.
Background technology
Recently, increasing occasion needs to use LDO (low pressure difference linear voltage regulator) to chip power supply.Refer to accompanying drawing
1, Fig. 1 structural representation showing a kind of currently used LDO.Described traditional LDO includes: a bandgap reference circuit 101,
One amplifier 102, the 12nd MOS transistor M12, one second resistance R2, one the 3rd resistance R3 and one first electric capacity C1, its
In, the outfan of described bandgap reference circuit 101 is connected to the inverting input of described amplifier 102, described amplifier 102
Outfan is connected to the grid of described 12nd MOS transistor M12, and the source electrode of described 12nd MOS transistor M12 is connected to
Two voltage VDD, drain electrode is connected to one end of described second resistance R2, the other end of described second resistance R2 and described 3rd resistance
One end of R3 is series at one the 3rd node, the other end ground connection of described 3rd resistance R3, described 3rd node be connected to described in put
The normal phase input end of big device 102, one end of described first electric capacity C1 is connected to the drain electrode of described 12nd MOS transistor M12, separately
One end is connected to ground, the output voltage that output voltage is described traditional LDO of described 12nd MOS transistor M12 drain electrode
VOUT1。
When the load current of described LDO changes quickly, during for example, 1ns or several ns, traditional LDO is difficult to so
The change of response LDO output voltage in the short time.This loop bandwidth being primarily due to LDO is limited.Current solution
Have: one is to filter ripple with off-chip electric capacity；Another kind is with electric capacity in sufficiently large sheet.The most any being required for introduces electricity
Hold, if stablize the output voltage of LDO without electric capacity, then the ripple of the output voltage of LDO will be the biggest.
Summary of the invention
It is an object of the invention to provide a kind of electric current and sink load circuit and low pressure difference linear voltage regulator, not introduce electricity
On the basis of appearance, reduce the ripple of LDO output voltage.
In order to achieve the above object, the invention provides a kind of electric current and sink load circuit, including: a RC filter circuit, one
First resistance and one first MOS transistor；Wherein, the grid of described first MOS transistor is connected to described RC filter circuit
Outfan, source electrode pass through described first resistance eutral grounding, drain electrode be connected to one first voltage.
Preferably, sinking in load circuit at above-mentioned electric current, described RC filter circuit includes: one second MOS transistor,
3rd MOS transistor, one the 4th resistance, one the 5th MOS transistor, one the 5th resistance, one the 7th MOS transistor, one second electricity
Appearance, one the 3rd electric capacity, 1 the tenth MOS transistor and 1 the 11st MOS transistor；
Wherein, the grid of described second MOS transistor is connected to the grid of described 3rd MOS transistor, and source electrode is connected to
Second voltage, described one end of 4th resistance and the drain electrode of the 5th MOS transistor are connected to the leakage of described second MOS transistor
Pole, the described other end of the 4th resistance and the source electrode of the 5th MOS transistor are connected to a primary nodal point；
Described one end of 5th resistance and the source electrode of the 7th MOS transistor are connected to described primary nodal point, described 5th electricity
The other end of resistance and the drain electrode of the 7th MOS transistor are connected to the drain electrode of described 3rd MOS transistor, described 3rd MOS crystal
The source ground of pipe；
One end of described second electric capacity is connected to described second voltage, and one end of the other end and described 3rd electric capacity is connected to
One secondary nodal point, the other end ground connection of described 3rd electric capacity；
The source electrode of described tenth MOS transistor is connected to the drain electrode of described 11st MOS transistor, and drain electrode is connected to described
Secondary nodal point, the source electrode of described 11st MOS transistor is connected to described second voltage；
Described primary nodal point and secondary nodal point are connected to the grid of described first MOS transistor.
Preferably, sinking in load circuit at above-mentioned electric current, described 4th resistance and/or the 5th resistance are a MOS crystal
Pipe；Wherein,
When described 4th resistance is four MOS transistor, the drain electrode of described 4th MOS transistor and the 5th MOS are brilliant
The drain electrode of body pipe is connected to the drain electrode of described second MOS transistor, the source electrode of described 4th MOS transistor and the 5th MOS crystal
The source electrode of pipe is connected to described primary nodal point, the grounded-grid of described 4th MOS transistor；
When described 5th resistance is six MOS transistor, the source electrode of described 6th MOS transistor and the 7th MOS are brilliant
The source electrode of body pipe is connected to described primary nodal point, and the drain electrode of the 6th MOS transistor and the drain electrode of the 7th MOS transistor are connected to institute
Stating the drain electrode of the 3rd MOS transistor, the grid of described 6th MOS transistor is connected to described second voltage.
Preferably, sinking in load circuit at above-mentioned electric current, described second electric capacity and the/the three electric capacity are a MOS transistor；
Wherein,
When described second electric capacity is eight MOS transistor, the source electrode of described 8th MOS transistor and drain electrode conducting are also
Being connected to described second voltage, grid is connected to described secondary nodal point；
When described 3rd electric capacity is nine MOS transistor, the source electrode of described 9th MOS transistor and drain electrode conducting are also
Being connected to ground, grid is connected to described secondary nodal point.
Preferably, sinking in load circuit at above-mentioned electric current, one first control signal is simultaneously entered to described 2nd MOS brilliant
The grid of body pipe, the grid of the 3rd MOS transistor and the grid of the tenth MOS transistor.
Preferably, sinking in load circuit at above-mentioned electric current, one second control signal is simultaneously entered to described 5th MOS brilliant
The grid of body pipe and the grid of the 7th MOS transistor.
Preferably, sinking in load circuit at above-mentioned electric current, an id signal input is to described 11st MOS transistor
Grid.
Preferably, sink in load circuit at above-mentioned electric current, described second MOS transistor, the 5th MOS transistor, the tenth
MOS transistor and the 11st MOS transistor are N-type MOS transistor；Described first MOS transistor, the 3rd MOS transistor
And the 7th MOS transistor be N-type MOS transistor.
Present invention also offers a kind of low pressure difference linear voltage regulator, sink load circuit including a: electric current as above, institute
Stating electric current to sink load circuit and be parallel to the two ends of a load, one end of described load connects the output electricity of low pressure difference linear voltage regulator
Pressure, other end ground connection.
Preferably, in above-mentioned low pressure difference linear voltage regulator, also include: a bandgap reference circuit, an amplifier, one
12 MOS transistors, one second resistance, one the 3rd resistance and one first electric capacity, wherein, the output of described bandgap reference circuit
End is connected to the inverting input of described amplifier, and the outfan of described amplifier is connected to described 12nd MOS transistor
Grid, the source electrode of described 12nd MOS transistor is connected to the second voltage, and drain electrode is connected to one end of described second resistance, institute
One end of the other end and described 3rd resistance of stating the second resistance is series at one the 3rd node, another termination of described 3rd resistance
Ground, described 3rd node is connected to the normal phase input end of described amplifier, and one end of described first electric capacity is connected to the described tenth
The drain electrode of two MOS transistor M12, the other end is connected to ground；One end of described load connects the leakage of described 12nd MOS transistor
Pole, the output voltage that output voltage is described low pressure difference linear voltage regulator of described 12nd MOS transistor drain electrode.
The electric current provided in the present invention sinks in load circuit and low pressure difference linear voltage regulator, when described low pressure difference linearity filters
Device, when carrying out pattern switching, utilizes described electric current to sink load circuit to reduce the load electricity that described low pressure difference linearity wave filter is total
The frequency of stream so that described low pressure difference linear voltage regulator has enough time to respond, and also will not waste too much electric current simultaneously, saves merit
Consumption.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of traditional LDO；
Fig. 2 is the structural representation of LDO in the embodiment of the present invention；
Fig. 3 is that in the embodiment of the present invention, electric current sinks the structural representation of load circuit；
Fig. 4 is that in further embodiment of this invention, electric current sinks the structural representation of load circuit；
Fig. 5 be load current ILOAD be schematic diagram over time；
Fig. 6 a, Fig. 6 b and Fig. 6 c are ICS schematic diagram over time；
Fig. 7 is load current ILOAD, ICS and total load current (ILOAD+ICS) schematic diagram over time；
Fig. 8 is the oscillogram under the first control signal and the second control signal long idle pattern；
In figure: 101-bandgap reference current；102-operational amplifier；
201-bandgap reference current；202-operational amplifier；203-electric current sinks load circuit；204-loads；2031-RC filters
Wave circuit.
Detailed description of the invention
Below in conjunction with schematic diagram, the detailed description of the invention of the present invention is described in more detail.According to description below and
Claims, advantages and features of the invention will be apparent from.It should be noted that, accompanying drawing all uses the form simplified very much and all
Use non-ratio accurately, only in order to facilitate, to aid in illustrating lucidly the purpose of the embodiment of the present invention.
Embodiments providing a kind of low pressure difference linear voltage regulator (LDO), refer to accompanying drawing 2, Fig. 2 shows this
The structural representation of the low pressure difference linear voltage regulator provided in bright embodiment.Described low pressure difference linear voltage regulator includes that an electric current sinks
Load circuit, described electric current sinks load circuit and is parallel to be the two ends of load, and one end of described load connects described low voltage difference line
The output voltage of property manostat, other end ground connection.The most described electric current sinks one end of load circuit and is also connected to described low voltage difference line
The output voltage of property manostat, other end ground connection.
In embodiments of the present invention, described low pressure difference linear voltage regulator includes: bandgap reference circuit 201, amplifier
202,1 the 12nd MOS transistor M12, one second resistance R2, one the 3rd resistance R3, one first electric capacity C1 and an electric current are heavy negative
Carry circuit 203.Wherein, the outfan of described bandgap reference circuit 201 is connected to the inverting input of described amplifier 202, for
Described low pressure difference linear voltage regulator provides its bias voltage VREF needed.The outfan of described amplifier 202 is connected to described
The grid of the 12nd MOS transistor M12, the source electrode of described 12nd MOS transistor M12 is connected to the second voltage VDD, and drain electrode is even
Being connected to one end of described second resistance R2, the other end of described second resistance R2 and one end of described 3rd resistance R3 are series at one
3rd node, the other end ground connection of described 3rd resistance R3, described 3rd node is connected to the positive input of described amplifier 202
End, one end of described first electric capacity C1 is connected to the drain electrode of described 12nd MOS transistor M12, other end ground connection.Described electric current
Heavy load circuit 203 is parallel to the two ends of a load 204, and one end of described load 204 is connected to described 12nd MOS transistor
The drain electrode of M12, other end ground connection.It is steady that the output voltage of described 12nd MOS transistor drain electrode M12 is described low pressure difference linearity
Output voltage VO UT of depressor.
Wherein, described operational amplifier the 202, the 12nd MOS transistor M12, the second resistance R2 and the 3rd resistance R3 structure
Becoming an amplification feedback control loop, output voltage VO UT of described low pressure difference linear voltage regulator is stablized by this amplification feedback control loop
VREF*(1+R2/R3).ILOAD in accompanying drawing 2 represents the electric current flowing through described load 204, i.e. load current.ICS is for flowing through
State electric current and sink the electric current of load circuit 203.
In other embodiments of the invention, described low pressure difference linear voltage regulator is not restricted to above-mentioned structure, also
Can be other structures, if ensure described electric current sink load circuit and described low pressure difference linear voltage regulator load parallel connection i.e.
Can, to reach to utilize described electric current to sink load circuit to reduce the frequency of the total load current of described low pressure difference linearity wave filter
Purpose.
As it is shown on figure 3, Fig. 3 shows that the electric current in one embodiment of the invention sinks the structural representation of load circuit.Described
Electric current sinks load circuit 203 and includes: RC filter circuit 2031, a 1 first resistance R1 and one first MOS transistor M1；Its
In, the grid of described first MOS transistor M1 is connected to the outfan of described RC filter circuit 2031, and source electrode passes through described first
Resistance R1 ground connection, drain electrode is connected to described first voltage.Described first voltage is described 12nd MOS transistor drain electrode M12
Output voltage, output voltage VO UT of the most described low pressure difference linear voltage regulator.
Wherein, described RC filter circuit 2031 includes: one second MOS transistor M2, one the 3rd MOS transistor M3, one
4 the 4th resistance R4, one the 5th MOS transistor M5, one the 5th resistance R5, one the 7th MOS transistor M7, one second electric capacity C2, one
3rd electric capacity C3,1 the tenth MOS transistor M10 and 1 the 11st MOS transistor M11.
Concrete, refer to accompanying drawing 3, Fig. 3 shows that the electric current in one embodiment of the invention sinks the structure of load circuit and shows
It is intended to.The grid of described second MOS transistor M2 is connected to the grid of described 3rd MOS transistor M3, and source electrode is connected to second
Voltage VDD, described one end of 4th resistance R4 and the drain electrode of the 5th MOS transistor M5 are connected to described second MOS transistor M2
Drain electrode, the described other end of the 4th resistance R4 and the source electrode of the 5th MOS transistor M5 are connected to a primary nodal point A；Described
One end of five resistance R5 and the source electrode of the 7th MOS transistor M7 are connected to described primary nodal point A, the other end of the 5th resistance R5 and
The drain electrode of the 7th MOS transistor M7 is connected to the drain electrode of described 3rd MOS transistor M3, the source of described 3rd MOS transistor M3
Pole ground connection；One end of described second electric capacity C2 is connected to described second voltage VDD, the other end and one end of described 3rd electric capacity C3
Being connected to a secondary nodal point B, the other end of described 3rd electric capacity C3 is connected to ground；The source electrode of described tenth MOS transistor M10 is even
Being connected to described 11st MOS transistor, the drain electrode of M11, drain electrode is connected to described secondary nodal point B, described 11st MOS transistor
The source electrode of M11 is connected to described second voltage VDD；Described primary nodal point A and secondary nodal point B is connected to a described MOS crystal
The grid of pipe M1.
Described first MOS transistor M1, the 3rd MOS transistor M3, the 7th MOS transistor M7 and be N-type MOS crystal
Pipe is N-type MOS transistor.Described second MOS transistor M2, the 5th MOS transistor M5, the tenth MOS transistor M10 and the tenth
One MOS transistor M11 is N-type MOS transistor.Further, described 4th MOS transistor M4 and the 6th MOS transistor M6
For MOS resistance, described 8th MOS transistor M8 and the 9th MOS transistor M9 is mos capacitance.
Described 4th electric capacity R4 and the 5th resistance R5 can be MOS transistor resistance can also be polysilicon resistance.Equally
Described second electric capacity C2 and the 3rd electric capacity C3 can be MOS transistor cAN_SNacitor can also be polysilicon capacitance, the most another at this
One repeats.
Further, described 4th resistance R4 and the 5th resistance R5 can be the resistance of same form, the most described 4th
Resistance R4 and the 5th resistance R5 can be MOS transistor resistance simultaneously, it is also possible to be polysilicon resistance, it is also possible to be simultaneously simultaneously
The resistance of other forms.In like manner, described 4th resistance R4 and the 5th resistance R5 can also be two different form of resistance, such as
Described 4th resistance R4 is the resistance of a kind of form, and described 5th resistance R5 is another form of resistance.Further, example
As, described 4th resistance R4 is MOS transistor resistance, and described 5th resistance R5 is polysilicon resistance.Or, described 4th electricity
Resistance R4 is polysilicon resistance, and described 5th resistance R5 is MOS transistor resistance.
When described 4th resistance R4 is a MOS transistor resistance, such as, described 4th resistance R4 is that one the 4th MOS is brilliant
During body pipe M4, described 4th MOS transistor M4 is a N-type MOS transistor.And the drain electrode and of described 4th MOS transistor M4
The drain electrode of five MOS transistor M5 is connected to the drain electrode of described second MOS transistor M2, the source electrode of described 4th MOS transistor M4
It is connected to described primary nodal point, the grounded-grid of described 4th MOS transistor M4 with the source electrode of the 5th MOS transistor M5.
When described 5th resistance R5 is a MOS transistor resistance, such as, described 5th resistance R5 is that one the 6th MOS is brilliant
During body pipe M6, described 6th MOS transistor M6 is a N-type MOS transistor.The source electrode and the 7th of described 6th MOS transistor M6
The source electrode of MOS transistor M7 is connected to described primary nodal point A, and the drain electrode of the 6th MOS transistor M6 is with the 7th MOS transistor M7's
Drain electrode is connected to the drain electrode of described 3rd MOS transistor M3, and the grid of described 6th MOS transistor M6 is connected to described second electricity
Pressure VDD.
Described second electric capacity C2 and the 3rd electric capacity C3 can be MOS transistor cAN_SNacitor, it is also possible to is polysilicon capacitance, also may be used
To be the electric capacity of other forms.Described second electric capacity C2 and the 3rd electric capacity C3 can be identic electric capacity, it is also possible to be shape
The electric capacity that formula is different.Such as, described second electric capacity C2 and the 3rd electric capacity C3 can be MOS transistor cAN_SNacitor simultaneously, it is also possible to
It it is polysilicon capacitance simultaneously.Can also be that described second electric capacity C2 is the electric capacity of a kind of form, and described 3rd electric capacity C3 is another
A kind of electric capacity of form.Such as, described second electric capacity C2 is a MOS transistor cAN_SNacitor, and described 3rd electric capacity C3 is another kind of
The electric capacity of form, such as polysilicon capacitance.Can also be described second electric capacity C2 be a polysilicon capacitance, and described 3rd electric capacity
C3 is a MOS transistor cAN_SNacitor.
When described second electric capacity C2 is a MOS transistor cAN_SNacitor, for example, during a 8th MOS transistor M8, the 8th MOS
Transistor M8 is a N-type MOS transistor.Further, the source electrode of described 8th MOS transistor M8 and drain electrode turn on and are connected to
Described second voltage VDD, grid is connected to described secondary nodal point B.
When described 3rd electric capacity C3 is a MOS transistor cAN_SNacitor, for example, during a 9th MOS transistor M9, described
Nine MOS transistor M9 are a N-type MOS transistor.Further, the source electrode of described 9th MOS transistor M9 and drain electrode conducting are also
Being connected to ground, grid is connected to described secondary nodal point B.
Fig. 4 is to show that inventing electric current in another embodiment sinks the structural representation of load circuit.Now, described 4th electricity
Resistance R4, the 5th resistance R5, the second electric capacity C2 and the 3rd electric capacity C3 are MOS transistor.Concrete connected mode such as Fig. 4 institute
Show.
Wherein, the drain electrode of described 4th MOS transistor M4 and the drain electrode of the 5th MOS transistor M5 are connected to described second
The drain electrode of MOS transistor M2, the described source electrode of the 4th MOS transistor M4 and the source electrode of the 5th MOS transistor M5 are connected to described
Primary nodal point, the grounded-grid of described 4th MOS transistor M4.The source electrode of described 6th MOS transistor M6 and the 7th MOS crystal
The source electrode of pipe M7 is connected to described primary nodal point A, and the drain electrode of the 6th MOS transistor M6 and the drain electrode of the 7th MOS transistor M7 are even
Being connected to the drain electrode of described 3rd MOS transistor M3, the grid of described 6th MOS transistor M6 is connected to described second voltage VDD.
The source electrode of described 8th MOS transistor M8 and drain electrode turn on and are connected to described second voltage VDD, and grid is connected to described second
Node B.The source electrode of described 9th MOS transistor M9 and drain electrode turn on and are connected to ground, and grid is connected to described secondary nodal point B.
One first control signal in1 is simultaneously entered the grid to described second MOS transistor M2, the 3rd MOS transistor M3
Grid and the grid of the tenth MOS transistor M10.One second control signal in2 is simultaneously entered to described 5th MOS transistor
The grid of M5 and the grid of the 7th MOS transistor M7..One id signal flag_longblank input extremely described 11st MOS
The grid of transistor M11.
Described first control signal in1 and the second control signal in2 are combined by some simple logic, waveform such as Fig. 8
Shown in, Fig. 8 shows that in the embodiment of the present invention, the first control signal in1 and the second control signal in2 are under long idle pattern
Oscillogram.Wherein, hs_en is that the fast mode of described load 204 enables signal, and hs_pre is the high speed mould of described load 204
The advance signal of formula, general, he_pre Tre more Zao than hs_en, wherein, Tre should be greater than the anti-of low pressure difference linear voltage regulator LDO
Between Ying Shi.Specifically, Tre ＞ 1/ (2* π * BW), BW is the responsive bandwidth of low pressure difference linear voltage regulator LDO, 1/ (2* π * BW)
It is the response time of described low pressure difference linear voltage regulator.
Wherein, In2=hs_en | hs_pre, in1=hs_en ⊙ in2_dealy, in2_dealy are that in2 postpones a timing
Waveform after between, is for postponing the waveform after 5ns, in other embodiments of the invention, institute in accompanying drawing 8 in the present embodiment
The time postponed can carry out sets itself as required, can be such as postpone 2ns, 4ns, 6ns, 7ns and 8ns etc. other
Time, this is no longer going to repeat them.The most described second control signal in2 is that described fast mode enables signal hs_en with high
The advance signal hs_pre of fast mode is carried out or the result of calculation of computing, and described first control signal in1 is described high speed mould
Formula enables signal hs_en Yu in2_dealy and carries out the same or result of calculation of computing.Then recycle described fast mode and enable letter
Described fast mode is enabled to negate after signal hs_en samples again and just obtains described id signal by the rising edge of number hs_pre
flag_longblank。
Described load current ILOAD is time dependent, and it is the most as shown in Figure 5.When described low voltage difference
When linear voltage regulator is under fast mode (HS), described load current ILOAD is big；When described low pressure difference linear voltage regulator is in
Time under idle pulley (LP), described load current ILOAD is little.When low pressure difference linear voltage regulator needs to switch between two patterns
Time, this switching is typically to complete within one or two nanosecond, current often use low pressure difference linear voltage regulator LDO come at all
Not as good as responding, and described electric current sinks load circuit 203 for providing an electric current heavy load so that (ILOAD+ICS's)
The change of amplitude and frequency is kept in certain scope, in particularly the change of frequency maintains certain scope so that
Low pressure difference linear voltage regulator in this programme can have time enough to carry out accordingly.
Concrete, idle pulley can be divided into three kinds according to the difference of idle pulley duration: long idle mould
Formula (long blanking mode), medium idle pulley (medium blamking mode) and short idle pulley (short
blank mode).Described long idle pattern refers to that low-power consumption mode is sustained for longer than 2*Tre, described medium idle pulley
Refer to that low-power consumption mode duration is less than 2*Tre, simultaneously greater than Tre.Described short idle pulley refers to that low-power consumption mode is held
The continuous time is less than Tre.Wherein, the Tre response time more than low pressure difference linear voltage regulator LDO, Tre ＞ 1/ (2* π * BW), BW
For the responsive bandwidth of low pressure difference linear voltage regulator LDO, 1/ (2* π * BW) is the response time of described 1/ (2* π * BW) LDO.
For three kinds of different idle pulleys, the time dependent form of ICS is also different.Concrete, refer to attached
Fig. 6 a, Fig. 6 b and Fig. 6 c, Fig. 6 a is the version of ICS under long idle pattern；Fig. 6 b is the change of ICS under medium idle pulley
Change form；Fig. 6 c is the version of ICS under short idle pulley.The version of the ICS under these three pattern can be by adjusting
Whole described id signal realizes.When described id signal flag_longblank is 1, at described low pressure difference linear voltage regulator
In long idle pattern, described 11st MOS transistor M11 closes, and the version of described ICS is as shown in Figure 6 a.When described mark
When knowledge signal flag_longblank is 0, described low pressure difference linear voltage regulator is in medium idle pulley or short idle pulley, institute
Stating the 11st MOS transistor M11 to open, the version of described ICS is as shown in Fig. 6 b or Fig. 6 c.So, total load current
(ILOAD+ICS) amplitude and frequency can maintain within the scope of certain so that described low pressure difference linear voltage regulator comes
And response, also will not waste too much electric current simultaneously, save power consumption.Total load current (ILOAD+ICS) is over time
As shown in Figure 7.As can be seen from Figure, the load current (ILOAD+ that described low pressure difference linear voltage regulator is total when pattern switches
ICS) FREQUENCY CONTROL is within the scope of certain so that described low pressure difference linear voltage regulator has certain response time.
Concrete operation principle, refers to accompanying drawing 7.When described low pressure difference linear voltage regulator is in long idle pattern, institute
Stating id signal flag_longblank is 1, in conjunction with Fig. 7 it can be seen that when hs_en is by high step-down, described first controls letter
Number in1 is also by high step-down, and described second MOS transistor M2 conducting, the most described second control signal in2 is low, therefore, described
5th MOS transistor M5 conducting, the grid voltage of described first MOS transistor M1 is quickly pulled up, thus causes described first
MOS transistor M1 turns on, and extracts electric current ICS from the drain electrode of described first MOS transistor M1.After continuing the most several nanosecond,
Described first control signal in1 uprises, and described second MOS transistor M2 closes, described 3rd MOS transistor M3 conducting, described
3rd MOS transistor M3 is slowly discharged to described secondary nodal point B by described 9th MOS transistor M9, causes described second section
The voltage of some B is gradually lowered, so that drain circuit ICS of described first MOS transistor M1 is gradually reduced.
Further, when hs-pre is by low uprising, described first control signal in1 step-down, described second control signal
In2 uprises, and described second MOS transistor M2 conducting, described 3rd MOS transistor M3 closes, and described 5th MOS transistor M5 closes
Close.Described second MOS transistor M2 is slowly charged to described secondary nodal point B by described 4th MOS transistor M4, causes described
The voltage of secondary nodal point B gradually rises, so that the electric current ICS of described first MOS transistor M1 drain electrode is gradually increased.
Further, when hs_en is by low uprising, described first control signal in2 uprises, the second control signal in2
Step-down, described 3rd MOS transistor M3 conducting, described 7th MOS transistor M7 conducting, described second MOS transistor M2 closes,
Described 3rd MOS transistor M3 to described secondary nodal point B repid discharge, causes described by described 7th MOS transistor M7
The voltage of two node B reduces rapidly, so that the electric current ICS of described first MOS transistor M1 drain electrode is 0.
When described low pressure difference linear voltage regulator is in medium idle pulley, described id signal flag_longblank is
1, in conjunction with Fig. 7.Operation principle when its operation principle is in long idle pattern with described low pressure difference linear voltage regulator is identical, and it is not
With being only that the time that its hs_en is 0 is shorter, the electric current ICS of described first MOS transistor M1 drain electrode has little time to drop to 0 will
It is gradually increasing.
When described low pressure difference linear voltage regulator is in short idle pulley, described id signal flag_longblank is 0,
Described second control signal in2 is high, i.e. in2=1, when hs_en is by high step-down, described first control signal is also become by height
Low, described second MOS transistor M2 conducting, described tenth MOS transistor M10 conducting, described 11st MOS transistor M11 leads
Logical, described tenth MOS transistor M10 and the 11st MOS transistor M11 to described secondary nodal point quick charge, a described MOS
Transistor M1 turns on.When hs_en is by low uprising, described first control signal in1 uprises, and described 3rd MOS transistor M3 leads
Logical, the 7th MOS transistor M7 conducting, described second MOS transistor M2 closes, and described tenth MOS transistor M10 closes, described
3rd MOS transistor M3 to secondary nodal point B repid discharge, causes described secondary nodal point B's by described 7th MOS transistor M7
Voltage reduces rapidly, so that the drain current ICS of described first MOS transistor M1 becomes 0.
To sum up, the electric current provided in the embodiment of the present invention sinks in load circuit and low pressure difference linear voltage regulator, when described low
Pressure reduction linear filter, when carrying out pattern switching, utilizes described electric current to sink load circuit to reduce the filtering of described low pressure difference linearity
The frequency of the load current that device is total so that described low pressure difference linear voltage regulator has enough time to respond, also will not waste too much simultaneously
Electric current, saves power consumption.
Above are only the preferred embodiments of the present invention, the present invention is not played any restriction effect.Belonging to any
Those skilled in the art, in the range of without departing from technical scheme, to the technical scheme that the invention discloses and
Technology contents makes the variations such as any type of equivalent or amendment, all belongs to the content without departing from technical scheme, still
Within belonging to protection scope of the present invention.
Claims (10)
1. an electric current sinks load circuit, it is characterised in that including: a RC filter circuit, one first resistance and one the oneth MOS
Transistor；Wherein, the grid of described first MOS transistor is connected to the outfan of described RC filter circuit, and source electrode is by described
First resistance eutral grounding, drain electrode is connected to one first voltage.
2. electric current as claimed in claim 1 sinks load circuit, it is characterised in that described RC filter circuit includes: one the 2nd MOS
Transistor, one the 3rd MOS transistor, one the 4th resistance, one the 5th MOS transistor, one the 5th resistance, one the 7th MOS transistor,
One second electric capacity, one the 3rd electric capacity, 1 the tenth MOS transistor and 1 the 11st MOS transistor；
Wherein, the grid of described second MOS transistor is connected to the grid of described 3rd MOS transistor, and source electrode is connected to second
Voltage, described one end of 4th resistance and the drain electrode of the 5th MOS transistor are connected to the drain electrode of described second MOS transistor, institute
The source electrode of the other end and the 5th MOS transistor of stating the 4th resistance is connected to a primary nodal point；
Described one end of 5th resistance and the source electrode of the 7th MOS transistor are connected to described primary nodal point, described 5th resistance
The drain electrode of the other end and the 7th MOS transistor is connected to the drain electrode of described 3rd MOS transistor, described 3rd MOS transistor
Source ground；
One end of described second electric capacity is connected to described second voltage, and one end of the other end and described 3rd electric capacity is connected to one
Two nodes, the other end ground connection of described 3rd electric capacity；
The source electrode of described tenth MOS transistor is connected to the drain electrode of described 11st MOS transistor, and drain electrode is connected to described second
Node, the source electrode of described 11st MOS transistor is connected to described second voltage；
Described primary nodal point and secondary nodal point are connected to the grid of described first MOS transistor.
3. electric current as claimed in claim 2 sinks load circuit, it is characterised in that described 4th resistance and/or the 5th resistance are
One MOS transistor；Wherein,
When described 4th resistance is four MOS transistor, the drain electrode of described 4th MOS transistor and the 5th MOS transistor
Drain electrode be connected to the drain electrode of described second MOS transistor, the source electrode of described 4th MOS transistor and the 5th MOS transistor
Source electrode is connected to described primary nodal point, the grounded-grid of described 4th MOS transistor；
When described 5th resistance is six MOS transistor, the source electrode of described 6th MOS transistor and the 7th MOS transistor
Source electrode be connected to described primary nodal point, the drain electrode of the 6th MOS transistor and the drain electrode of the 7th MOS transistor are connected to described the
The drain electrode of three MOS transistors, the grid of described 6th MOS transistor is connected to described second voltage.
4. electric current as claimed in claim 2 sinks load circuit, it is characterised in that described second electric capacity and the/the three electric capacity are one
MOS transistor；Wherein,
When described second electric capacity is eight MOS transistor, the source electrode of described 8th MOS transistor and drain electrode conducting also connect
In described second voltage, grid is connected to described secondary nodal point；
When described 3rd electric capacity is nine MOS transistor, the source electrode of described 9th MOS transistor and drain electrode conducting also connect
Yu Di, grid is connected to described secondary nodal point.
5. electric current as claimed in claim 2 sinks load circuit, it is characterised in that one first control signal is simultaneously entered to described
The grid of the second MOS transistor, the grid of the 3rd MOS transistor and the grid of the tenth MOS transistor.
6. electric current as claimed in claim 2 sinks load circuit, it is characterised in that one second control signal is simultaneously entered to described
The grid of the 5th MOS transistor and the grid of the 7th MOS transistor.
7. electric current as claimed in claim 2 sinks load circuit, it is characterised in that an id signal input is to the described 11st
The grid of MOS transistor.
8. electric current as claimed in claim 2 sinks load circuit, it is characterised in that described second MOS transistor, the 5th MOS are brilliant
Body pipe, the tenth MOS transistor and the 11st MOS transistor are N-type MOS transistor；Described first MOS transistor, the 3rd
MOS transistor and the 7th MOS transistor are N-type MOS transistor.
9. a low pressure difference linear voltage regulator, including: just like the heavy load electricity of the electric current described in any one in claim 1 to 8
Road, described electric current sinks load circuit and is parallel to the two ends of a load, and one end of described load connects low pressure difference linear voltage regulator
Output voltage, other end ground connection.
10. low pressure difference linear voltage regulator as claimed in claim 9, it is characterised in that also include a: bandgap reference circuit,
Amplifier, 1 the 12nd MOS transistor, one second resistance, one the 3rd resistance and one first electric capacity, wherein, described band gap is joined
The outfan examining circuit is connected to the inverting input of described amplifier, and the outfan of described amplifier is connected to the described 12nd
The grid of MOS transistor, the source electrode of described 12nd MOS transistor is connected to the second voltage, and drain electrode is connected to described second electricity
One end of resistance, the other end of described second resistance is series at one the 3rd node, described 3rd electricity with one end of described 3rd resistance
The other end ground connection of resistance, described 3rd node is connected to the normal phase input end of described amplifier, and one end of described first electric capacity is even
Being connected to the drain electrode of described 12nd MOS transistor M12, the other end is connected to ground；One end of described load connects the described 12nd
The drain electrode of MOS transistor, the output that output voltage is described low pressure difference linear voltage regulator of described 12nd MOS transistor drain electrode
Voltage.
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| CN107678480A (en) * | 2017-11-13 | 2018-02-09 | 常州欣盛微结构电子有限公司 | A kind of linear voltage manager for low-power consumption digital circuit |
| CN110187733A (en) * | 2019-06-20 | 2019-08-30 | 江苏润石科技有限公司 | The low pressure difference linear voltage regulator of Earl benefit phenomenon can be eliminated |
| US10866607B1 (en) | 2019-12-17 | 2020-12-15 | Analog Devices International Unlimited Company | Voltage regulator circuit with correction loop |
| CN115202427A (en) * | 2021-04-09 | 2022-10-18 | 上海艾为电子技术股份有限公司 | Voltage stabilizing circuit and power management chip |
| CN115469706A (en) * | 2022-09-06 | 2022-12-13 | 北京空间机电研究所 | Low dropout regulator |
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|---|---|
| CN106200741B (en) | 2017-12-22 |
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