CN109075783A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuit Download PDFInfo
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- CN109075783A CN109075783A CN201780024431.3A CN201780024431A CN109075783A CN 109075783 A CN109075783 A CN 109075783A CN 201780024431 A CN201780024431 A CN 201780024431A CN 109075783 A CN109075783 A CN 109075783A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/002—Switching arrangements with several input- or output terminals
- H03K17/005—Switching arrangements with several input- or output terminals with several inputs only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
- H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0018—Special modifications or use of the back gate voltage of a FET
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Electronic Switches (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Power supply switch circuit is realized in order to reach using only low resistance to piezoelectric crystal, and it does not need special perforation electric current and prevents control circuit, when the first supply voltage (VDD1 (=0V/3.3V)) is in off state and second source voltage (VDD2 (=0V/1.8V)) is in the conductive state, control switching circuit (2, 3) output is from ground voltage potential to the signal of second source voltage potential, as the first supply voltage (VDD1), when second source voltage (VDD2) is all on state, control switching circuit (2, 3) output is from second source voltage potential to the signal of the first supply voltage current potential, thus PMOS transistor (P1) and NMOS transistor (N1) are controlled as on state or off state.
Description
Technical field
This disclosure relates to a kind of semiconductor integrated circuit including power supply switch circuit, which has to institute
The function that the supply voltage of supply switches over.
Background technique
In general, in order to make interface high speed and in the case where improve the frequency of signal, to inhibit power consumption to increase
Reduce the voltage level of signal.For example, in the interface standard of SD storage card (safe digital card: secure digital card)
Under, it was the interface of 3.3V signal in the past, in contrast, being the interface of 1.8V signal under new high speed modular.Moreover, in such as SD
Under storage card interface standard widely available like that, it is desirable that equipment meets new and old two standards.Therefore, it is necessary to interface circuit according to
Standard corresponding to the SD storage card connected carrys out the voltage level of switching signal.Therefore, it is necessary to will feed to the electricity of interface circuit
Source voltage is switched to the power supply switch circuit of 3.3V or 1.8V.
Even if certain prior art realizes one kind, a supply voltage in multiple supply voltage is in dissengaged positions
In the case of also do not allow the following power supply switch circuit (referring to patent document 1) for generating the useless electric current such as parasitic diode electric current.
Patent document 1: International Publication No. 2014/038115
Summary of the invention
The technical problems to be solved by the invention-
In the above prior art, because be applied to constitute power supply switch circuit MOS (metal-oxide semiconductor (MOS):
Metal-oxide-semiconductor) maximum value of the voltage between the terminal of transistor is 3.3V, therefore uses 3.3V pressure resistance
MOS transistor, above-mentioned 3.3V pressure resistance MOS transistor are which two terminals no matter taken in four terminals of each transistor, are all permitted
Perhaps thus the transistor that potential difference is up to 3.3V between above-mentioned two terminal is led so as to cause manufacturing process cost increase etc.
Overall cost is caused to increase.Moreover, in order to cope with multiple power supplys that are pressure-resistant and using external 1.8V/3.3V, but in such case
Under need to prevent control circuit with perforation electric current, which prevents control circuit from preventing passing through in side's power supply
Galvanization.
To solve the technical solution-of technical problem
The disclosure realizes the power supply switch circuit for not allowing and generating useless electric current using only low pressure-resistant MOS transistor, and
Not needing special perforation electric current prevents control circuit.
First semiconductor integrated circuit of the disclosure is characterised by comprising: ground terminal is applied earthing potential；
First power supply terminal is applied the first supply voltage, and in the off state, first supply voltage indicates and earthing potential
The voltage of equal ground voltage level, in the on-state, first supply voltage indicate higher than earthing potential first
The voltage of mains voltage level；Second source terminal is applied second source voltage, in the off state, second electricity
Source voltage indicates the voltage of ground voltage level, and in the on-state, ground voltage level is compared in the second source voltage expression
The voltage of high and lower than the first mains voltage level second source voltage level；Third power supply terminal, output are applied to the
The second source voltage that the first supply voltage or output on one power supply terminal are applied on second source terminal；PMOS (P ditch
Road MOS) transistor, connect the first power supply terminal and third power supply terminal；NMOS (N-channel MOS) transistor, connection second
Power supply terminal and third power supply terminal；First control switching circuit is connected with the grid of PMOS transistor；And second switching
Control circuit is connected with the grid of NMOS transistor, when the first supply voltage is at off state and second source voltage
When on state, the first control switching circuit is exported from ground voltage level to the signal second source voltage level,
When the first supply voltage and second source voltage are all on state, the output of the first control switching circuit is electric from second source
Thus voltage level controls PMOS transistor on state or off state to the signal between the first mains voltage level,
When the first supply voltage is in off state and second source voltage in the conductive state, the second control switching circuit output from
Ground voltage level is to the signal between second source voltage level, when the first supply voltage and second source voltage are all in leading
When logical state, the second control switching circuit is exported from second source voltage level to the signal the first mains voltage level,
It thus is conducting (ON) state or cut-off (OFF) state by NMOS transistor control.
Second semiconductor integrated circuit of the disclosure is characterised by comprising: ground terminal is applied earthing potential；
First power supply terminal is applied the first supply voltage, and in the off state, first supply voltage indicates and earthing potential
The voltage of equal ground voltage level, in the on-state, first supply voltage indicate higher than earthing potential first
The voltage of mains voltage level；Second source terminal is applied second source voltage, in the off state, second electricity
Source voltage indicates the voltage of ground voltage level, and in the on-state, ground voltage level is compared in the second source voltage expression
The voltage of high and lower than the first mains voltage level second source voltage level；Third power supply terminal, output are applied to the
The second source voltage that the first supply voltage or output on one power supply terminal are applied on second source terminal；First PMOS
Transistor connects the first power supply terminal and third power supply terminal；Second PMOS transistor connects second source terminal and the
Three power supply terminals；First control switching circuit is connected with the grid of the first PMOS transistor；And second switching control electricity
Road is connected with the grid of the second PMOS transistor, when the first supply voltage is in off state and second source voltage is in
When on state, the first control switching circuit export from ground voltage level to the signal second source voltage level, when
When first supply voltage and second source voltage are all on state, the first control switching circuit is exported from second source voltage
Thus level controls the first PMOS transistor on state or cut-off shape to the signal between the first mains voltage level
State；When the first supply voltage is in off state and the second source voltage is in the conductive state, the second switching control electricity
Road is exported from ground voltage level to the signal second source voltage level, when the first supply voltage and second source voltage
When all on state, the second control switching circuit is exported from ground voltage level to the letter the first mains voltage level
Number, thus the second PMOS transistor is controlled as on state or off state.
The effect of invention-
According to the disclosure, in the semiconductor integrated circuit for including power supply switch circuit, low pressure-resistant MOS transistor is used only
It can be realized as not allowing the power supply switch circuit for generating useless electric current, and do not need special perforation electric current to prevent control electricity
Road.
Detailed description of the invention
Fig. 1 is the circuit diagram for showing semiconductor integrated circuit involved in first embodiment.
Fig. 2 is the voltage of the voltage of higher side in the first supply voltage and second source voltage shown in selection Fig. 1
The circuit diagram of selector.
Fig. 3 is the voltage of the voltage of a lower side in the first supply voltage and second source voltage shown in selection Fig. 1
The circuit diagram of selector.
Fig. 4 is the circuit diagram of the prime level shifter in each control switching circuit shown in Fig. 1.
Fig. 5 is the circuit diagram of the rear class level shifter in each control switching circuit shown in Fig. 1.
Fig. 6 is the timing diagram for showing the working condition of the semiconductor integrated circuit in Fig. 1.
Fig. 7 is the circuit diagram for showing the variation of Fig. 5.
Fig. 8 is the circuit diagram for showing the variation of Fig. 4.
Fig. 9 is the circuit diagram for showing semiconductor integrated circuit involved in second embodiment.
Figure 10 is the timing diagram for showing the working condition of the semiconductor integrated circuit in Fig. 9.
Specific embodiment
In the following, being described with reference to two embodiments of the disclosure.
In various embodiments, it is illustrated using the semiconductor integrated circuit for including power supply switch circuit, which cuts
Circuit is changed to cut-off (OFF) state (=0V)/first supply voltage VDD1 of conducting (ON) state (=3.3V), off state
(=0V) the second source voltage VDD2 of/on state (=1.8V) the two supply voltages switch over.Assuming that semiconductor collection
It can be at off state (=0V)/on state (=0.9V) at the internal power source voltage VDD of circuit.
<first embodiment>
Fig. 1 is the circuit diagram for showing semiconductor integrated circuit involved in first embodiment.Semiconductor in Fig. 1 is integrated
Circuit includes power supply switch circuit 1, the first control switching circuit 2 and the second control switching circuit 3.In Fig. 1, VOH is first
The voltage (selection high voltage) of higher side in supply voltage VDD1 and second source voltage VDD2, VOL is the first supply voltage
The voltage (selection low-voltage) of a lower side in VDD1 and second source voltage VDD2.
Power supply switch circuit 1 has the first power supply terminal 11, second source feeding terminal 12, switching circuit and electricity
Source output terminal 13.Wherein, the first supply voltage VDD1 is applied to the first power supply terminal 11 from outside；Second source electricity
VDD2 is pressed to be applied to the second source feeding terminal 12 from outside；The switching circuit is by PMOS transistor P1 and NMOS transistor N1
It constitutes；The first supply voltage VDD1 or second source voltage VDD2 is exported VOUT by the power output terminal 13
It is output to the outside.For PMOS transistor P1, source electrode is connected with the first power supply terminal 11, drain electrode and power output terminal
13 are connected, and grid is connected with the output signal of the first control switching circuit 2 i.e. the first switch-over control signal SW1, back grid (back
Gate) it is connected with selection high voltage VOH.For NMOS transistor N1, source electrode is connected with second source feeding terminal 12, drain electrode
It is connected with power output terminal 13, output signal i.e. the second switch-over control signal SW2 phase of grid and the second control switching circuit 3
Even, back grid is connected with selection low-voltage VOL.Here, PMOS transistor P1 and NMOS transistor N1 is 1.8V pressure resistance MOS brilliant
Body pipe, even if that is, meet and take any two terminal in four terminals of each transistor, the electricity between above-mentioned two terminal
Potential difference is all in the transistor of the such bias condition of 1.8V or less (1.8V pressure resistance condition).
There is first control switching circuit 2 first level shifter L1, the first level shifter L1 to receive 0V/1.8V's
The input signal IN from outside of (enable) signal OE and 0V/0.9V, the first switching of supply are enabled from external output
Control signal SW1.First level shifter L1 is by electric using second source voltage VDD2 and earthing potential VSS as the prime of power supply
Translational shifting device LV11 and to select high voltage VOH and low-voltage VOL to be selected to be constituted as the rear class level shifter LV21 of power supply.
That is, the first level shifter L1 using prime level shifter LV11 will have from VSS (=0V) level to VDD (=
0.9V) the input signal IN of the amplitude of level, which is converted to, has from VSS (=0V) level to the amplitude of VDD2 (=1.8V) level
Signal, further using rear class level shifter LV21 by the output signal of prime level shifter LV11 be converted to have from
Select low-voltage VOL to the first switch-over control signal SW1 of the amplitude of selection high voltage VOH.
There is second control switching circuit 3 second electrical level shift unit L2, the second electrical level shift unit L2 to receive 0V/1.8V's
The input signal IN from outside from external output enable signal OE and 0V/0.9V, supplies the second switch-over control signal
SW2.Second electrical level shift unit L2 is by using second source voltage VDD2 and earthing potential VSS as the prime level shifter of power supply
LV12 and to select high voltage VOH and low-voltage VOL to be selected to be constituted as the rear class level shifter LV22 of power supply.That is,
Second electrical level shift unit L2 will have using prime level shifter LV12 from VSS (=0V) level to VDD (=0.9V) level
The input signal IN of amplitude be converted to and have from VSS (=0V) level to the signal of the amplitude of VDD2 (=1.8V) level, into
One step, which is converted to the output signal of prime level shifter LV12 using rear class level shifter LV22, has electricity low from selection
Press VOL to the second switch-over control signal SW2 of the amplitude of selection high voltage VOH.
Fig. 2 is the circuit diagram for showing the first voltage selector 4 of supply selection high voltage VOH.First voltage selector 4 has
There are the first PMOS transistor P21 and the second PMOS transistor P22.For the first PMOS transistor P21, source electrode and second source
Voltage VDD2 is connected, and drain electrode is connected with selection high voltage VOH, and grid is connected with the first supply voltage VDD1, back grid and selection
High voltage VOH is connected.For the second PMOS transistor P22, source electrode is connected with the first supply voltage VDD1, and drain electrode is high with selection
Voltage VOH is connected, and grid is connected with second source voltage VDD2, and back grid is connected with selection high voltage VOH.Here, first
PMOS transistor P21 and the second PMOS transistor P22 is 1.8V pressure resistance MOS transistor.
First voltage selector 4 according to Fig.2, if VDD1=0V, VDD2=1.8V, the first PMOS transistor
P21 becomes on state, the second PMOS transistor P22 becomes off state, therefore becomes VOH=VDD2=1.8V.Moreover, if
VDD1=3.3V, VDD2=1.8V, then the first PMOS transistor P21 becomes off state, the second PMOS transistor P22 becomes to lead
Logical state, therefore become VOH=VDD1=3.3V.That is, first voltage selector 4 selects the first supply voltage VDD1 and the
High voltage in two supply voltage VDD2 alternatively high voltage VOH.
Fig. 3 is the circuit diagram for showing the second voltage selector 5 of supply selection low-voltage VOL.Second voltage selector 5 has
There are the first NMOS transistor N31 and the second NMOS transistor N32.For the first NMOS transistor N31, source electrode and second source
Voltage VDD2 is connected, and drain electrode is connected with selection low-voltage VOL, and grid is connected with the first supply voltage VDD1, back grid and selection
Low-voltage VOL is connected.For the second NMOS transistor N32, source electrode is connected with the first supply voltage VDD1, and drain electrode is low with selection
Voltage VOL is connected, and grid is connected with second source voltage VDD2, and back grid is connected with selection low-voltage VOL.Here, first
NMOS transistor N31 and the second NMOS transistor N32 is 1.8V pressure resistance MOS transistor.
Second voltage selector 5 according to Fig.3, if VDD1=0V, VDD2=1.8V, the first NMOS transistor
N31 becomes off state, the second NMOS transistor N32 becomes on state, therefore becomes VOL=VDD1=0V.Moreover, if
VDD1=3.3V, VDD2=1.8V, then the first NMOS transistor N31 becomes on state, the second NMOS transistor N32 becomes to cut
Only state, therefore become VOL=VDD2=1.8V.That is, second voltage selector 5 selects the first supply voltage VDD1 and the
Low-voltage in two supply voltage VDD2 alternatively low-voltage VOL.
As described above, according to first voltage selector 4 and second voltage selector 5, if VDD1=0V, VDD2=
1.8V then becomes VOH=1.8V, VOL=0V.Moreover, if VDD1=3.3V, VDD2=1.8V, become VOH=3.3V,
VOL=1.8V.
Fig. 4 is the circuit diagram of prime level shifter LV11, LV12 in each control switching circuit 2,3 shown in Fig. 1.
The level shifter of the representation of Fig. 4 being discussed further below receives above-mentioned input signal IN, above-mentioned output enable signal OE
And second source voltage VDD2, output is generated to the output signal OUT1 of rear class level shifter LV21, LV22, which moves
Position device has the first PMOS transistor P41, the second PMOS transistor P42, third PMOS transistor P43, the 4th PMOS transistor
P44, the first NMOS transistor N41, the second NMOS transistor N42, third NMOS transistor N43 and the first phase inverter INV41,
Second phase inverter INV42, the first above-mentioned PMOS transistor P41, the second PMOS transistor P42, third PMOS transistor P43,
4th PMOS transistor P44, the first NMOS transistor N41, the second NMOS transistor N42, third NMOS transistor N43, first
Phase inverter INV41, the second phase inverter INV42 are only made of 1.8V pressure resistance MOS transistor.First phase inverter INV41 allows input to believe
The logic level reverse phase of number IN, the second phase inverter INV42 allow the logic level reverse phase of output enable signal OE.With regard to the first PMOS crystalline substance
For body pipe P41, source electrode is connected with second source voltage VDD2, and drain electrode is connected with the source electrode of the second PMOS transistor P42, grid
It is connected with the grid of the output signal of the second phase inverter INV42 and third PMOS transistor P43.With regard to the second PMOS transistor P42
For, drain electrode is connected with the drain electrode of the grid of the 4th PMOS transistor P44 and the first NMOS transistor N41, and grid and output are believed
Number OUT1, the drain electrode of the 4th PMOS transistor P44, the drain electrode of the second NMOS transistor N42 and third NMOS transistor N43
Drain electrode is connected.For third PMOS transistor P43, source electrode is connected with second source voltage VDD2, and drain electrode is brilliant with the 4th PMOS
The source electrode of body pipe P44 is connected.For the first NMOS transistor N41, source electrode is connected with earthing potential, grid and input signal IN
It is connected.For the second NMOS transistor N42, source electrode is connected with earthing potential, the output letter of grid and the first phase inverter INV41
Number be connected.For third NMOS transistor N43, source electrode is connected with earthing potential, the output of grid and the second phase inverter INV42
Signal is connected.
According to the structure of Fig. 4, if output enable signal OE is L level, the output signal of the second phase inverter INV42 is just
Become H level, the first PMOS transistor P41, third PMOS transistor P43 become off state, third NMOS transistor N43
Become on state, therefore the logic level regardless of input signal IN, output signal OUT1 are fixed on L (=0V) level
On.
Next, explanation exports in Fig. 4, enable signal OE is H level and input signal IN is H (=0.9V) level
In the case of level shifter how to work.Because output enable signal OE is H level, the second phase inverter INV42's
Output signal becomes L level, and the first PMOS transistor P41, third PMOS transistor P43 become on state, the 3rd NMOS
Transistor N43 becomes off state.On the other hand, because input signal IN be H level, the first NMOS transistor N41 and
4th PMOS transistor P44 becomes on state, and the second NMOS transistor N42 and the second PMOS transistor P42 become to cut
Only state.As a result, output signal OUT1 becomes H (=1.8V) level.
Finally, illustrating the case where output enable signal OE is H level in Fig. 4 and input signal IN is L (=0V) level
How lower level shifter works.Because output enable signal OE is H level, the output of the second phase inverter INV42
Signal becomes L level, and the first PMOS transistor P41, third PMOS transistor P43 become on state, the 3rd NMOS crystal
Pipe N43 becomes off state.On the other hand, because input signal IN is L level, the first NMOS transistor N41 and the 4th
PMOS transistor P44 becomes off state, and the second NMOS transistor N42 and the second PMOS transistor P42 become that shape is connected
State.As a result, output signal OUT1 becomes L (=0V) level.
As described above, side receives the control carried out using output enable signal OE according to the structure of Fig. 4, side receives amplitude
For the input signal IN of 0.9V, it will be able to obtain that logic level is identical as input signal IN and amplitude is the output signal of 1.8V
OUT1。
Fig. 5 is the circuit diagram of rear class level shifter LV21, LV22 in each control switching circuit 2,3 shown in Fig. 1.
The level shifter of the representation of Fig. 5 being discussed further below receives the output signal of prime level shifter LV11, LV12
OUT1 makees input signal IN1, and receives second source voltage VDD2, selection high voltage VOH and selection low-voltage VOL, generates
Output signal OUT has as above-mentioned first switch-over control signal SW1 and the second switch-over control signal SW2, the level shifter
First PMOS transistor P51, the second PMOS transistor P52, third PMOS transistor P53, the 4th PMOS transistor P54, the 5th
PMOS transistor P55, the 6th PMOS transistor P56, the 7th PMOS transistor P57, the 8th PMOS transistor P58, the first NMOS
Transistor N51, the second NMOS transistor N52, third NMOS transistor N53, the 4th NMOS transistor N54, the 5th NMOS crystal
Pipe N55, the 6th NMOS transistor N56, the 7th NMOS transistor N57, the 8th NMOS transistor N58 and phase inverter INV51, it
Be only made of 1.8V pressure resistance MOS transistor.Phase inverter INV51 allows the logic level reverse phase of input signal IN1.With regard to the first PMOS
For transistor P51, source electrode and selection high voltage VOH, the back grid of itself, the second PMOS transistor P52 back grid and
The back grid of 5th PMOS transistor P55 is connected, the source electrode and the 5th PMOS transistor of drain electrode and the second PMOS transistor P52
The drain electrode of P55 is connected, the source of grid and output signal OUT, the source electrode of the 6th PMOS transistor P56, the 8th PMOS transistor P58
Pole is connected with the drain electrode of back grid and the 7th NMOS transistor N57.For the second PMOS transistor P52, drain electrode and the 7th
The drain electrode of the grid of PMOS transistor P57 and the first NMOS transistor N51 are connected, and grid is connected with selection low-voltage VOL.With regard to
For three PMOS transistor P53, the backgate of source electrode and selection high voltage VOH, the back grid of itself, the 4th PMOS transistor P54
Pole is connected with the back grid of the 6th PMOS transistor P56, the source electrode and the 6th PMOS crystal of drain electrode and the 4th PMOS transistor P54
The drain electrode of pipe P56 is connected, the source electrode and back grid of the source electrode of grid and the 5th PMOS transistor P55, the 7th PMOS transistor P57
And the 5th NMOS transistor N55 drain electrode be connected.For the 4th PMOS transistor P54, drain electrode and the 8th PMOS transistor
The grid of P58 is connected with the drain electrode of third NMOS transistor N53, and grid is connected with selection low-voltage VOL.5th PMOS transistor
P55 and the 6th respective grid of PMOS transistor P56 are connected with selection low-voltage VOL.7th PMOS transistor P57 and the 8th
The respective drain electrode of PMOS transistor P58 is also connected with selection low-voltage VOL.For the first NMOS transistor N51, source electrode and
The drain electrode of bi-NMOS transistor N52 is connected, and grid is connected with second source voltage VDD2.For the second NMOS transistor N52,
Source electrode is connected with earthing potential, and grid is connected with the grid of input signal IN1 and the 6th NMOS transistor N56.With regard to the 3rd NMOS
For transistor N53, source electrode is connected with the drain electrode of the 4th NMOS transistor N54, and grid is connected with second source voltage VDD2.Just
For 4th NMOS transistor N54, source electrode is connected with earthing potential, the output signal and the 8th of grid and phase inverter INV51
The grid of NMOS transistor N58 is connected.For the 5th NMOS transistor N55, the drain electrode of source electrode and the 6th NMOS transistor N56
It is connected, grid is connected with second source voltage VDD2.The source electrode of 6th NMOS transistor N56 is connected with selection low-voltage VOL.Just
For 7th NMOS transistor N57, source electrode is connected with the drain electrode of the 8th NMOS transistor N58, grid and second source voltage
VDD2 is connected.The source electrode of 8th NMOS transistor N58 is connected with selection low-voltage VOL.
In Fig. 5 in the case where VOH=1.8V, VOL=0V, if input signal IN1 is H (=1.8V) level, the
Three PMOS transistor P53, the 4th PMOS transistor P54, the 6th PMOS transistor P56, the 7th PMOS transistor P57, first
NMOS transistor N51, the second NMOS transistor N52, the 5th NMOS transistor N55 and the 6th NMOS transistor N56 become respectively
At on state, the first PMOS transistor P51, the second PMOS transistor P52, the 5th PMOS transistor P55, the 8th PMOS crystal
Pipe P58, third NMOS transistor N53, the 4th NMOS transistor N54, the 7th NMOS transistor N57 and the 8th NMOS transistor
N58 respectively becomes off state.As a result, output signal OUT becomes H (=1.8V) level.
In Fig. 5 in the case where VOH=1.8V, VOL=0V, if input signal IN1 be L (=0V) level, first
PMOS transistor P51, the second PMOS transistor P52, the 5th PMOS transistor P55, the 8th PMOS transistor P58, the 3rd NMOS
Transistor N53, the 4th NMOS transistor N54, the 7th NMOS transistor N57 and the 8th NMOS transistor N58 respectively become and lead
Logical state, third PMOS transistor P53, the 4th PMOS transistor P54, the 6th PMOS transistor P56, the 7th PMOS transistor
P57, the first NMOS transistor N51, the second NMOS transistor N52, the 5th NMOS transistor N55 and the 6th NMOS transistor
N56 respectively becomes off state.As a result, output signal OUT becomes L (=0V) level.
In Fig. 5 in the case where VOH=3.3V, VOL=1.8V, if input signal IN1 is H (=1.8V) level,
Third PMOS transistor P53, the 4th PMOS transistor P54, the 6th PMOS transistor P56, the 7th PMOS transistor P57, first
NMOS transistor N51, the second NMOS transistor N52, the 5th NMOS transistor N55 and the 6th NMOS transistor N56 become respectively
At on state, the first PMOS transistor P51, the second PMOS transistor P52, the 5th PMOS transistor P55, the 8th PMOS crystal
Pipe P58, third NMOS transistor N53, the 4th NMOS transistor N54, the 7th NMOS transistor N57 and the 8th NMOS transistor
N58 respectively becomes off state.As a result, output signal OUT becomes H (=3.3V) level.
Finally, in Fig. 5 in the case where VOH=3.3V, VOL=1.8V, if input signal IN1 is L (=0V) electricity
It is flat, then the first PMOS transistor P51, the second PMOS transistor P52, the 5th PMOS transistor P55, the 8th PMOS transistor P58,
Third NMOS transistor N53, the 4th NMOS transistor N54, the 7th NMOS transistor N57 and the 8th NMOS transistor N58 points
Do not become on state, third PMOS transistor P53, the 4th PMOS transistor P54, the 6th PMOS transistor P56, the 7th PMOS
Transistor P57, the first NMOS transistor N51, the second NMOS transistor N52, the 5th NMOS transistor N55 and the 6th NMOS are brilliant
Body pipe N56 respectively becomes off state.As a result, output signal OUT becomes L (=1.8V) level.
Fig. 6 is the timing diagram for showing the working condition of the semiconductor integrated circuit in Fig. 1.In the pervious initial shape of moment t1
Under state, internal power source voltage VDD, second source voltage VDD2, the first supply voltage VDD1, output enable signal OE, input letter
Number IN, the first switch-over control signal SW1, the second switch-over control signal SW2, supply voltage output VOUT are all 0V.
Rise in moment t1, internal power source voltage VDD.So, it has just carried out and has cut input signal IN supply first
Change the preparation of control circuit 2, the second control switching circuit 3.
Rise in moment t2, second source voltage VDD2.As a result, becoming VOH=1.8V, VOL=0V.Because of OE=
L (=0V), so the first switch-over control signal SW1, the second switch-over control signal SW2 maintain 0V.At the moment, PMOS crystal
Pipe P1 is in the conductive state, NMOS transistor N1 is in off state, therefore maintains the state of VOUT=0V.PMOS transistor P1
Source electrode, drain electrode, grid and the respective voltage of back grid be respectively 0V, 0V, 0V, 1.8V.Moreover, the source of NMOS transistor N1
Pole, drain electrode, grid and the respective voltage of back grid are 1.8V, 0V, 0V, 0V.Therefore, PMOS transistor P1 and NMOS transistor N1
All meet 1.8V pressure resistance condition.Moreover, NMOS transistor N1 securely maintains off state in such side power supply,
Therefore even if being not provided with special perforation electric current prevents control circuit, perforation electric current will not occur from second source feeding terminal 12
The case where flowing to the first power supply terminal 11.
Rise in moment t3, the first supply voltage VDD1.As a result, become VOH=3.3V, VOL=1.8V.OE=L
(=0V) it is constant, but become with selection high voltage VOH in rear class level shifter LV21, LV22 and selection low-voltage VOL
Change, therefore the first switch-over control signal SW1, the second switch-over control signal SW2 become 1.8V.At the moment, PMOS transistor P1
In the conductive state, NMOS transistor N1 is in off state, therefore becomes VOUT=3.3V.The source electrode of PMOS transistor P1,
Drain electrode, grid and the respective voltage of back grid are 3.3V, 3.3V, 1.8V, 3.3V.Source electrode, drain electrode, the grid of NMOS transistor N1
It is 1.8V, 3.3V, 1.8V, 1.8V with the respective voltage of back grid.Therefore, PMOS transistor P1 and NMOS transistor N1 meet
1.8V pressure resistance condition.
In moment t4, exports enable signal OE and rise.Because IN=0V is constant, therefore other signals do not change.
Rise in moment t5, input signal IN.As a result, the first switch-over control signal SW1, the second switch-over control signal
SW2 becomes 3.3V.At the moment, PMOS transistor P1 changes towards off state, and NMOS transistor N1 is towards on state
Variation, therefore become VOUT=1.8V.Source electrode, drain electrode, grid and the respective voltage of back grid of PMOS transistor P1 be 3.3V,
1.8V,3.3V,3.3V.Source electrode, drain electrode, grid and the respective voltage of back grid of NMOS transistor N1 be 1.8V, 1.8V,
3.3V,1.8V.Therefore, PMOS transistor P1 and NMOS transistor N1 meets 1.8V pressure resistance condition.
Decline in moment t6, input signal IN, in moment t7, enable signal OE decline is exported, in moment t8, the first power supply
Voltage VDD1 decline declines in moment t9, second source voltage VDD2, declines in moment t10, internal power source voltage VDD, thus
Return to original state.
Fig. 7 is the circuit diagram for showing the variation of Fig. 5.The level shifter of the representation of Fig. 5 being discussed further below,
The output signal OUT1 of prime level shifter LV11, LV12 are received as input signal IN1 and high voltage VOH and choosing are selected in reception
It selects low-voltage VOL, generates output signal OUT as the first above-mentioned switch-over control signal SW1, the second switch-over control signal SW2,
The level shifter has the first PMOS transistor P71, the second PMOS transistor P72, third PMOS transistor P73, the 4th
PMOS transistor P74, the 5th PMOS transistor P75, the 6th PMOS transistor P76, the first NMOS transistor N71, the 2nd NMOS
Transistor N72, third NMOS transistor N73, the 4th NMOS transistor N74 and phase inverter INV71.Wherein, the 5th PMOS is brilliant
Body pipe P75, the 6th PMOS transistor P76 and phase inverter INV71 are made of 1.8V pressure resistance MOS transistor, the first PMOS crystal
The PMOS transistor P74 of pipe P71~the 4th, the first NMOS transistor N74 of NMOS transistor N71~the 4th all by LD (horizontal proliferation:
Laterally diffused) MOS transistor composition.Here, ldmos transistor means following MOS transistor, it may be assumed that can
It is electric between the voltage of application 3.3V the drain electrode of the source and drain interpolar of the MOS transistor, grid leak interpolar and back grid, but between other terminals
Pressure should but meet 1.8V pressure resistance condition.
Phase inverter INV71 allows the logic level reverse phase of input signal IN1.For the first PMOS transistor P71, source electrode with
The back grid of high voltage VOH, the back grid of itself and third PMOS transistor P73 is selected to be connected, drain electrode is brilliant with the 3rd PMOS
The drain electrode of the drain electrode of body pipe P73, the grid of the 5th PMOS transistor P75 and the first NMOS transistor N71 is connected, grid with it is defeated
Signal OUT, the source electrode of the 4th PMOS transistor P74, the source electrode of the 6th PMOS transistor P76 and back grid and the 4th NMOS out
The drain electrode of transistor N74 is connected.For the second PMOS transistor P72, source electrode and selection high voltage VOH, itself back grid,
The back grid of 4th PMOS transistor P74 is connected, drain electrode and the drain electrode of the 4th PMOS transistor P74, the 6th PMOS transistor P76
The drain electrode of grid and the second NMOS transistor N72 be connected, the source electrode of grid and the second PMOS transistor P72, the 5th PMOS crystalline substance
The source electrode of body pipe P75 is connected with the drain electrode of back grid and third NMOS transistor N73.Third PMOS transistor P73 and the 4th
The respective grid of PMOS transistor P74 is connected with selection low-voltage VOL.5th PMOS transistor P75 and the 6th PMOS transistor
The respective drain electrode of P76 is also connected with selection low-voltage VOL.For the first NMOS transistor N71, source electrode and earthing potential phase
Even, grid is connected with the grid of input signal IN1 and third NMOS transistor N73.For the second NMOS transistor N72, source
Pole is connected with earthing potential, and grid is connected with the grid of the output signal of phase inverter INV71 and the 4th NMOS transistor N74.The
Three NMOS transistor N73 and the 4th respective source electrode of NMOS transistor N74 are connected with selection low-voltage VOL.
In Fig. 7 in the case where VOH=1.8V, VOL=0V, if input signal IN1 is H (=1.8V) level, the
Two PMOS transistor P72, the 4th PMOS transistor P74, the 5th PMOS transistor P75, the first NMOS transistor N71 and third
NMOS transistor N73 respectively becomes on state, and the first PMOS transistor P71, third PMOS transistor P73, the 6th PMOS are brilliant
Body pipe P76, the second NMOS transistor N72 and the 4th NMOS transistor N74 respectively become off state.As a result, output letter
Number OUT becomes H (=1.8V) level.
In Fig. 7, in the case where VOH=1.8V, VOL=0V, if input signal IN1 be L (=0V) level, first
PMOS transistor P71, third PMOS transistor P73, the 6th PMOS transistor P76, the second NMOS transistor N72 and the 4th NMOS
Transistor N74 respectively becomes on state, the second PMOS transistor P72, the 4th PMOS transistor P74, the 5th PMOS transistor
P75, the first NMOS transistor N71 and third NMOS transistor N73 respectively become off state.As a result, output signal OUT
Become L (=0V) level.
Moreover, in Fig. 7 in the case where VOH=3.3V, VOL=1.8V, if input signal IN1 is H (=1.8V) electricity
Flat, then output signal OUT reforms into H (=3.3V) level.At this point, the second PMOS transistor P72, the 4th PMOS transistor P74,
5th PMOS transistor P75, the first NMOS transistor N71 and third NMOS transistor N73 respectively become on state, and first
PMOS transistor P71, third PMOS transistor P73, the 6th PMOS transistor P76, the second NMOS transistor N72 and the 4th NMOS
Transistor N74 respectively becomes off state.Although grid leak interpolar, the 3rd PMOS crystal of the first PMOS transistor P71 therein
Between the back grid and drain electrode of pipe P73, the grid leak of the grid leak interpolar of the second NMOS transistor N72 and the 4th NMOS transistor N74
The voltage of interpolar reaches 3.3V, but because the use of these transistors is all ldmos transistor, therefore pressure-resistant problem will not occur.
Finally, in Fig. 7 in the case where VOH=3.3V, VOL=1.8V, if input signal IN1 is L (=0V) electricity
Flat, output signal OUT reforms into L (=1.8V) level.At this point, the first PMOS transistor P71, third PMOS transistor P73,
Six PMOS transistor P76, the second NMOS transistor N72 and the 4th NMOS transistor N74 respectively become on state, the 2nd PMOS
Transistor P72, the 4th PMOS transistor P74, the 5th PMOS transistor P75, the first NMOS transistor N71 and the 3rd NMOS crystal
Pipe N73 respectively becomes off state.Although grid leak interpolar, the 4th PMOS transistor P74 of the second PMOS transistor P72 therein
Back grid drain electrode between, the electricity of the grid leak interpolar of the grid leak interpolar of the first NMOS transistor N71 and third NMOS transistor N73
Pressure reaches 3.3V, but because the use of these transistors is all ldmos transistor, therefore pressure-resistant problem will not occur.
According to the structure of Fig. 7, with the first PMOS transistor P74 of PMOS transistor P71~the 4th and the first NMOS transistor
N71~the 4th is compared the case where NMOS transistor N74 uses 3.3V pressure resistance MOS transistor, is made by using ldmos transistor
For above-mentioned transistor, it will be able to realize the lesser level shifter of circuit scale.
It should be noted that by the first PMOS transistor P71, the second PMOS transistor P72 and the first NMOS in Fig. 7
The NMOS transistor N74 of transistor N71~the 4th replaces with the cascade connection of two 1.8V pressure resistance MOS transistors respectively, and by
It is big that three PMOS transistor P73 and the 4th PMOS transistor P74 replace with the later structure of 1.8V pressure resistance MOS transistor respectively
Cause the structure for being equivalent to Fig. 5.
Fig. 8 is the circuit diagram for showing the variation of Fig. 4.The structure of Fig. 8 is that have the first PMOS transistor P81, second
PMOS transistor P82, third PMOS transistor P83, the 4th PMOS transistor P84, the first NMOS transistor N81, the 2nd NMOS
The structure of transistor N82, third NMOS transistor N83, the first phase inverter INV81, the second phase inverter INV82, i.e., as Fig. 4
Structure output stage on increase third phase inverter INV83 and constitute, the first PMOS transistor P81, the second PMOS transistor
P82, third PMOS transistor P83, the 4th PMOS transistor P84, the first NMOS transistor N81, the second NMOS transistor N82,
Third NMOS transistor N83, the first phase inverter INV81, the second phase inverter INV82, third phase inverter INV83 are only by 1.8V pressure resistance
MOS transistor is constituted.Third phase inverter INV83 is connected with second source voltage VDD2 and earthing potential, third phase inverter INV83
Output be to rear class level shifter LV21, LV22 export output signal XOUT.
According to the structure of Fig. 8, if output enable signal OE is L (=0V) level, no matter the logic of input signal IN
How is level, and output signal XOUT can be fixed on H (=1.8V) level.It is H (=1.8V) in output enable signal OE
In the case where level, if input signal IN is H (=0.9V) level, output signal XOUT just will become L (=0V) level, such as
Fruit input signal IN is L (=0V) level, and output signal XOUT just will become H (=1.8V) level.
As described above, side receives the control carried out using output enable signal OE according to the structure of Fig. 8, side receives amplitude
For the input signal IN of 0.9V, it will be able to obtain the output letter of the amplitude 1.8V with the logic level opposite with input signal IN
Number XOUT.
If allowing prime level shifter LV11 and the second switching control electricity in the first control switching circuit 2 in Fig. 1
Both prime level shifter LV12 in road 3 become structure shown in Fig. 8 from structure shown in Fig. 4, it will be able to make output
Supply voltage output VOUT in the case that energy signal OE is L level is changed to VDD2 from the first supply voltage VDD1 (=3.3V)
(=1.8V).
If the prime level shifter LV12 in the second control switching circuit 3 in Fig. 1 is made to keep structure shown in Fig. 4
It is constant, and the prime level shifter LV11 in the first control switching circuit 2 is allowed to be changed to shown in Fig. 8 from structure shown in Fig. 4
Structure, then, export enable signal OE be L level in the case where, both PMOS transistor P1 and NMOS transistor N1 are
Become off state, therefore supply voltage can be exported VOUT and be used as high impedance output.
As described above, according to first embodiment, low pressure-resistant MOS transistor being used only, that is, it is brilliant that 1.8V pressure resistance MOS is used only
Body pipe or ldmos transistor, it will be able to which realization does not allow the power supply switch circuit for generating useless electric current, and does not need particularly to pass through
Galvanization prevents control circuit.
<second embodiment>
Fig. 9 is the circuit diagram for showing semiconductor integrated circuit involved in second embodiment.Semiconductor in Fig. 9 is integrated
Circuit includes power supply switch circuit 1a, the first control switching circuit 2 and the second control switching circuit 3a.
NMOS transistor N1 in power supply switch circuit 1 in Fig. 1 is replaced with PMOS by the power supply switch circuit 1a in Fig. 9
Transistor P2, to reduce ESD (electrostatic discharge, static discharge) risk.In the following description, will
PMOS transistor P1 between the first power supply terminal 11 and power output terminal 13 is known as " the first PMOS transistor ",
PMOS transistor P2 between second source feeding terminal 12 and power output terminal 13 is known as " the 2nd PMOS crystal
Pipe ".First PMOS transistor P1 and the second respective back grid of PMOS transistor P2 are connected with selection high voltage VOH.
The first control switching circuit 2 in Fig. 9 has a case that first level shifter L1 of the structure as Fig. 1.
First switch-over control signal SW1 is fed to the grid of the first PMOS transistor P1 by the first level shifter L1.
The second control switching circuit 3a in Fig. 9 not only has a case that second electrical level displacement of the structure as Fig. 1
Device L2 also has third level shifter L3, third PMOS transistor P91, the 4th PMOS transistor P92 and the first NMOS brilliant
Body pipe N91, the second NMOS transistor N92.Third level shifter L3 by structure and above-mentioned prime level shifter LV11,
LV12 the same level shifter LV13 is constituted, and third level shifter L3 receives output the enable signal OE and 0V/ of 0V/1.8V
The input signal IN of 0.9V, generates the signal of 0V/1.8V.For third PMOS transistor P91, source electrode and selection high voltage
VOH is connected, and drain electrode is connected with the source electrode of the 4th PMOS transistor P92, the output signal phase of grid and second electrical level shift unit L2
Even.For the 4th PMOS transistor P92, the drain electrode of drain electrode and the second switch-over control signal SW2 and the second NMOS transistor N92
It is connected, grid is connected with second source voltage VDD2.For the first NMOS transistor N91, source electrode and earthing potential VSS phase
Even, drain electrode is connected with the source electrode of the second NMOS transistor N92, and grid is connected with the output signal of third level shifter L3.The
The grid of bi-NMOS transistor N92 is connected with second source voltage VDD2.Third PMOS transistor P91, the 4th PMOS transistor
P92 and the first NMOS transistor N91, the second NMOS transistor N92, which are constituted, allows the output signal of second electrical level shift unit L2
The phase inverter of logic level reverse phase.That is, second electrical level shift unit L2 in Fig. 9 is through the phase inverter by the second switching control
Signal SW2 supplies the grid of the second PMOS transistor P2.
Figure 10 is the timing diagram for showing the working condition of the semiconductor integrated circuit in Fig. 9.Figure 10 is compared with the waveform of Fig. 6
When difference be only that the waveform of the second switch-over control signal SW2 is different in Figure 10.
T2 to moment t3 and moment t8 are to moment t9, VDD1=0V, VDD2=1.8V at the time of in Figure 10, therefore become
VOH=1.8V, VOL=0V.In this case, the first switch-over control signal SW1 is L (=0V) level, the second switching control letter
Number SW2 is H (=1.8V) level, VOUT=0V.At this point, source electrode, drain electrode, grid and the back grid of the first PMOS transistor P1
Respective voltage is 0V, 0V, 0V, 1.8V.Moreover, source electrode, drain electrode, grid and the back grid of the second PMOS transistor P2 are respectively
Voltage be 1.8V, 0V, 1.8V, 1.8V.Therefore, the first PMOS transistor P1, that the second PMOS transistor P2 meets 1.8V is resistance to
Press strip part.Moreover, the second PMOS transistor P2 securely maintains off state in such side power supply, therefore even if not
Special perforation electric current, which is arranged, prevents control circuit, and perforation electric current will not occur from second source feeding terminal 12 and flow to first
The case where power supply terminal 11.
Moreover, t3 therefore becomes VOH=3.3V to moment t8, VDD1=3.3V, VDD2=1.8V at the time of in Figure 10,
VOL=1.8V.In this case, if the first switch-over control signal SW1 is L (=1.8V) level, the second switching control letter
Number SW2 is H (=3.3V) level, VOUT=3.3V.At this point, source electrode, drain electrode, grid and the backgate of the second PMOS transistor P2
Extremely respective voltage is 1.8V, 3.3V, 3.3V, 3.3V, meets 1.8V pressure resistance condition.On the other hand, if the first switching control
Signal SW1 is H (=3.3V) level, then the second switch-over control signal SW2 is L (=0V) level, becomes VOUT=1.8V.This
When, the second PMOS transistor P2 is in the conductive state, source electrode, drain electrode, grid and the back grid of second PMOS transistor P2
Respective voltage is that 1.8V, 1.8V, 0V, 3.3V also meet 1.8V pressure resistance condition in this case.
It should be noted that if third PMOS transistor P91 and the first NMOS transistor N91 in Fig. 9 are respectively adopted
Ldmos transistor, it will be able to save the 4th PMOS transistor P92 and the second NMOS transistor N92.In VDD1=3.3V, VDD2
=1.8V, so that the first NMOS transistor N91 is in off state, SW2=in the case where VOH=3.3V, VOL=1.8V
When 3.3V, the voltage of the grid leak interpolar of first NMOS transistor N91 becomes 3.3V, but because using LDMOS crystal
Pipe, therefore pressure-resistant problem will not occur.Moreover, third PMOS transistor P91 is in the case where VOH=3.3V, VOL=1.8V
When off state, SW2=0V, the source and drain interpolar of third PMOS transistor P91 and the voltage of grid leak interpolar become 3.3V, still
Because using ldmos transistor, therefore pressure-resistant problem will not occur.
As described above, low pressure-resistant MOS transistor is used only, that is, it is brilliant that 1.8V pressure resistance MOS is used only according to second embodiment
Body pipe or ldmos transistor also can be realized the power supply switch circuit for not allowing and generating useless electric current, and not need particularly to pass through
Galvanization prevents control circuit.
Industrial applicability-
It is realized in conclusion semiconductor integrated circuit involved in the disclosure has using only low pressure-resistant MOS transistor
It does not allow the power supply switch circuit for generating useless electric current, and do not need special perforation electric current to prevent the effect of control circuit, makees
It is that semiconductor integrated circuit for including power supply switch circuit etc. is very useful, above-mentioned power supply switch circuit, which has, switches supplied electricity
The function of source voltage.
Symbol description-
1,1a power supply switch circuit
2,3,3a control switching circuit
4,5 voltage selector
11,12 power supply terminal
13 power output terminals
IN input signal
L1, L2, L3, LV13 level shifter
LV11, LV12 prime level shifter
LV21, LV22 rear class level shifter
N1, N91, N92 NMOS transistor
OE exports enable signal
P1, P2, P91, P92 PMOS transistor
SW1, SW2 switch-over control signal
VDD internal power source voltage (0V/0.9V)
The first supply voltage of VDD1 (0V/3.3V)
VDD2 second source voltage (0V/1.8V)
VOH selects high voltage
VOL selects low-voltage
The output of VOUT supply voltage
VSS earthing potential (0V)
Claims (6)
1. a kind of semiconductor integrated circuit, it is characterised in that: include:
Ground terminal is applied earthing potential；
First power supply terminal is applied the first supply voltage, in the off state, first supply voltage indicate with it is described
The voltage of the equal ground voltage level of earthing potential, in the on-state, first supply voltage are indicated than the ground connection
The voltage of the first high mains voltage level of current potential；
Second source terminal is applied second source voltage, in the off state, connects described in the second source voltage expression
The voltage of ground voltage level, in the on-state, the second source voltage indicate higher than the ground voltage level and compare institute
State the voltage of the low second source voltage level of the first mains voltage level；
Third power supply terminal, exports first supply voltage being applied on first power supply terminal or output applies
The second source voltage on the second source terminal；
PMOS transistor connects first power supply terminal and the third power supply terminal；
NMOS transistor connects the second source terminal and the third power supply terminal；
First control switching circuit is connected with the grid of the PMOS transistor；And
Second control switching circuit is connected with the grid of the NMOS transistor,
When first supply voltage is in off state and the second source voltage is in the conductive state, described first is cut
Control circuit output is changed from the ground voltage level to the signal of the second source voltage level, when the first power supply electricity
When pressure and the second source voltage are all on state, the first control switching circuit output is electric from the second source
Thus voltage level controls the PMOS transistor on state or cut-off shape to the signal of first mains voltage level
State,
When first supply voltage is in off state and the second source voltage is in the conductive state, described second is cut
Control circuit output is changed from the ground voltage level to the signal of the second source voltage level, when the first power supply electricity
When pressure and the second source voltage are all on state, the second control switching circuit output is electric from the second source
Thus voltage level controls the NMOS transistor on state or cut-off shape to the signal of first mains voltage level
State.
2. semiconductor integrated circuit according to claim 1, it is characterised in that:
The semiconductor integrated circuit further include:
First voltage selector selects therein using first supply voltage and the second source voltage as power supply
The voltage of voltage level high voltage alternatively high-voltage level exports；And
Second voltage selector selects therein using first supply voltage and the second source voltage as power supply
The voltage of voltage level low voltage alternatively low voltage level exports,
The voltage of the selection high-voltage level is applied on the back grid of the PMOS transistor, the selection low voltage level
Voltage be applied on the back grid of the NMOS transistor.
3. semiconductor integrated circuit according to claim 2, it is characterised in that:
First control switching circuit and second control switching circuit are respectively provided with:
Prime level shifter, by from the ground voltage level to the input signal of internal power source voltage level be converted to from
Signal and output of the ground voltage level to the second source voltage level；And
Rear class level shifter is converted to the output signal of the prime level shifter from the selection low voltage level
To the signal of the selection high-voltage level.
4. a kind of semiconductor integrated circuit, it is characterised in that: include:
Ground terminal is applied earthing potential；
First power supply terminal is applied the first supply voltage, in the off state, first supply voltage indicate with it is described
The voltage of the equal ground voltage level of earthing potential, in the on-state, first supply voltage are indicated than the ground connection
The voltage of the first high mains voltage level of current potential；
Second source terminal is applied second source voltage, in the off state, connects described in the second source voltage expression
The voltage of ground voltage level, in the on-state, the second source voltage indicate higher than the ground voltage level and compare institute
State the voltage of the low second source voltage level of the first mains voltage level；
Third power supply terminal, exports first supply voltage being applied on first power supply terminal or output applies
The second source voltage on the second source terminal；
First PMOS transistor connects first power supply terminal and the third power supply terminal；
Second PMOS transistor connects the second source terminal and the third power supply terminal；
First control switching circuit is connected with the grid of first PMOS transistor；And
Second control switching circuit is connected with the grid of second PMOS transistor,
When first supply voltage is in off state and the second source voltage is in the conductive state, described first is cut
Control circuit output is changed from the ground voltage level to the signal of the second source voltage level, when the first power supply electricity
When pressure and the second source voltage are all on state, the first control switching circuit output is electric from the second source
Thus first PMOS transistor is controlled as on state or is cut to the signal of first mains voltage level by voltage level
Only state,
When first supply voltage is in off state and the second source voltage is in the conductive state, described second is cut
Control circuit output is changed from the ground voltage level to the signal of the second source voltage level, when the first power supply electricity
When pressure and the second source voltage are all on state, the second control switching circuit output is electric from the ground voltage
The signal of first mains voltage level is put down, thus controls second PMOS transistor on state or cut-off shape
State.
5. semiconductor integrated circuit according to claim 4, it is characterised in that:
The semiconductor integrated circuit further include:
First voltage selector selects therein using first supply voltage and the second source voltage as power supply
The voltage of voltage level high voltage alternatively high-voltage level exports；And
Second voltage selector selects therein using first supply voltage and the second source voltage as power supply
The voltage of voltage level low voltage alternatively low voltage level exports,
The back grid of first PMOS transistor and second PMOS transistor is all applied the selection high-voltage level
Voltage.
6. semiconductor integrated circuit according to claim 5, it is characterised in that:
First control switching circuit includes the first level shifter, and second control switching circuit includes that second electrical level moves
Position device, third level shifter and phase inverter,
First level shifter and the second electrical level shift unit are respectively provided with；
Prime level shifter, by from the ground voltage level to the input signal of internal power source voltage level be converted to from
Signal and output of the ground voltage level to the second source voltage level；And
Rear class level shifter is converted to the output signal of the prime level shifter from the selection low voltage level
To it is described selection high-voltage level signal,
The third level shifter has and will believe from the ground voltage level to the input of the internal power source voltage level
It number is converted to from the ground voltage level to the signal of the second source voltage level and the function that exports,
The phase inverter has the third being one another in series between the voltage and the earthing potential of the selection high-voltage level
PMOS transistor and the first NMOS transistor,
The output signal of the second electrical level shift unit is connected with the grid of the third PMOS transistor, and the third level moves
The output signal of position device is connected with the grid of first NMOS transistor.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016085236 | 2016-04-21 | ||
| JP2016-085236 | 2016-04-21 | ||
| PCT/JP2017/006200 WO2017183275A1 (en) | 2016-04-21 | 2017-02-20 | Semiconductor integrated circuit |
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| CN109075783A true CN109075783A (en) | 2018-12-21 |
| CN109075783B CN109075783B (en) | 2022-03-15 |
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| US (1) | US10644691B2 (en) |
| JP (1) | JP6871519B2 (en) |
| CN (1) | CN109075783B (en) |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111641407A (en) * | 2020-07-08 | 2020-09-08 | 湖南国科微电子股份有限公司 | Sectional type level conversion circuit, integrated chip and level conversion device |
| CN117318697A (en) * | 2023-09-15 | 2023-12-29 | 辰芯半导体（深圳）有限公司 | Level shift circuit and power supply device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110855285B (en) * | 2019-11-27 | 2023-09-15 | 西安紫光国芯半导体有限公司 | High frequency level shifter |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103492888A (en) * | 2011-04-21 | 2014-01-01 | 瑞萨电子株式会社 | Switch circuit, selection circuit, and voltage measurement device |
| JP2014052890A (en) * | 2012-09-07 | 2014-03-20 | Toshiba Corp | Power supply circuit |
| CN104521146A (en) * | 2012-09-06 | 2015-04-15 | 松下知识产权经营株式会社 | Semiconductor integrated circuit |
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| JP3701942B2 (en) * | 2003-01-21 | 2005-10-05 | 沖電気工業株式会社 | Level conversion circuit |
| JP4720704B2 (en) * | 2006-09-27 | 2011-07-13 | セイコーエプソン株式会社 | Power supply switching circuit |
| US7855574B2 (en) * | 2006-10-10 | 2010-12-21 | Altera Corporation | Programmable multiple supply regions with switched pass gate level converters |
| JP5710175B2 (en) * | 2010-08-04 | 2015-04-30 | ラピスセミコンダクタ株式会社 | Power switching circuit |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103492888A (en) * | 2011-04-21 | 2014-01-01 | 瑞萨电子株式会社 | Switch circuit, selection circuit, and voltage measurement device |
| CN104521146A (en) * | 2012-09-06 | 2015-04-15 | 松下知识产权经营株式会社 | Semiconductor integrated circuit |
| JP2014052890A (en) * | 2012-09-07 | 2014-03-20 | Toshiba Corp | Power supply circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111641407A (en) * | 2020-07-08 | 2020-09-08 | 湖南国科微电子股份有限公司 | Sectional type level conversion circuit, integrated chip and level conversion device |
| CN111641407B (en) * | 2020-07-08 | 2023-06-09 | 湖南国科微电子股份有限公司 | Sectional type level conversion circuit, integrated chip and level conversion device |
| CN117318697A (en) * | 2023-09-15 | 2023-12-29 | 辰芯半导体（深圳）有限公司 | Level shift circuit and power supply device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109075783B (en) | 2022-03-15 |
| US10644691B2 (en) | 2020-05-05 |
| US20190052259A1 (en) | 2019-02-14 |
| JPWO2017183275A1 (en) | 2019-02-28 |
| WO2017183275A1 (en) | 2017-10-26 |
| JP6871519B2 (en) | 2021-05-12 |
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