CN114840051A - Low-power-consumption high-transient-response low-dropout linear voltage regulator without off-chip capacitor - Google Patents
Low-power-consumption high-transient-response low-dropout linear voltage regulator without off-chip capacitor Download PDFInfo
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Abstract
The invention discloses a low-power consumption high-transient response low-dropout linear regulator without off-chip capacitance, wherein a grid direct current bias network is used for providing grid bias voltage required by the work of a power amplification transistor; the drain direct current bias network is used for providing drain bias voltage required by the work of the power amplification transistor; the input end impedance matching network comprises a microstrip line, a blocking capacitor and an RC parallel circuit; the output end impedance matching network comprises a harmonic control network and an elliptical low-pass filter matching network, wherein the harmonic control network selects two frequency points outside a passband to perform second harmonic control; the elliptical low-pass filter matching network is obtained by improving a six-order Chebyshev low-pass filter, two transmission zeros are generated outside a working frequency band, and conversion from fundamental wave impedance to second harmonic wave impedance is realized. The invention enables the power amplifier to realize high efficiency and high gain within the working bandwidth of over-five frequency multiplication.
Description
Technical Field
The invention belongs to the technical field of linear regulators, and particularly relates to a low-power-consumption high-transient-response low-dropout linear regulator without an off-chip capacitor.
Background
As integrated circuit designs and process flows continue to advance, more and more circuits are integrated together. Usually, a large-scale digital-analog hybrid chip includes a plurality of different digital/analog circuit modules, the analog circuit module needs to serve the digital module, for example, an analog power management module needs to provide a stable voltage for the digital module, and the most commonly used power management module is an LDO (low dropout regulator).
Nowadays, digital modules have higher and higher frequencies, which also brings challenges to analog module design, such as in ADC (analog to digital converter) applications, which require analog LDO to charge and discharge a capacitor array in a regulation phase, in which the switching time is in the order of a few nanoseconds and the recovery time for the LDO response is in the order of microseconds. This is difficult to achieve with conventional LDO circuits. Influenced by ADC characteristics, the LDO is required to have the characteristics of high transient response and high load capacity, the integration problem of a digital-analog hybrid circuit is considered, and the LDO is also required to have the characteristics of small area and low static power consumption.
However, in the design of the conventional LDO, a plurality of chip pins need to be reserved for the LDO, and an application engineer needs to select an external large capacitor having a specific ESR (equivalent series resistance) value range and a specific capacitance value range to ensure stable operation of the LDO and optimize the load transient characteristics of circuit output. However, due to the existence of the large off-chip capacitor, the conventional LDO cannot realize full on-chip integration, increases the area of the PCB, and is difficult to apply to the digital-analog hybrid integrated circuit.
With the development of integrated circuits, research on Capless-LDO (low dropout linear regulator without off-chip capacitance) has progressed. Classic Capless-LDO mostly adopts buffer driving type error amplifier and P type power output stage structure, adopts the buffer to reduce error amplifier's output impedance to raise the high order pole, guarantee LDO's stability. Having an output impedance of
The formula shows that in the application scene of low power consumption, the small quiescent current I D Will result in a small transconductance g m Further, a large output impedance r of the error amplifier is generated o And the distance between poles is too small, so that the stability of the LDO is difficult to ensure. Therefore, this buffer level driving type Capless-LDO structure is not suitable for low power consumption application scenarios. And the driving capability of the buffer stage is also very weak, so that the transient response of the LDO is poor, and the requirement of the work of the current high-speed digital-analog hybrid circuit cannot be met.
Disclosure of Invention
Therefore, there is a need for research and improvement to address the present needs and deficiencies in the art, and to provide a solution to address the needs and deficiencies in the art. Therefore, the LDO circuit without the off-chip capacitor has the characteristics of low power consumption, high transient response, low static power consumption, easiness in integration and the like.
In order to achieve the purpose, the invention provides a low-power-consumption high-transient-response low-dropout linear regulator without off-chip capacitor, which can be applied to a digital-analog hybrid integrated circuit, is stable in a full-load range, and realizes high transient response (switching time is 1 nanosecond, and recovery time is within 1 microsecond) on the premise of meeting low power consumption (static current is less than 5 microampere). The device specifically comprises a direct drive type error amplifier, an N-type power output stage, an adaptive impedance transient enhancement circuit and a compensation capacitor, wherein,
the direct drive type error amplifier comprises two input ends, the two input ends are respectively and directly connected with a feedback voltage node formed by a reference voltage and a resistor in the N-type power output stage, the output end of the direct drive type error amplifier is connected with the control end of the N-type power regulation stage, and the N-type power regulation stage is driven according to the voltage difference between the feedback voltage of the output voltage and the reference voltage;
the input end of the N-type power output stage is directly connected with the output end of the direct drive type error amplifier, and the output end of the N-type power output stage is the output end of the whole linear voltage stabilizer;
the input end of the adaptive impedance transient enhancement circuit is directly connected with the gate end of an NMOS current mirror in the direct-driven error amplifier, and the output end of the adaptive impedance transient enhancement circuit is directly connected with the output end of the N-type power output stage;
the input end of the compensation capacitor is directly connected with a feedback voltage node formed by the resistor of the N-type power output stage, the output end of the compensation capacitor is directly connected with the input end of the N-type power output stage, and the compensation capacitor and a feedback resistor circuit of the N-type power output stage form a compensation network.
Preferably, the direct drive type error amplifier employs a differential input, push-pull output architecture that generates rail-to-rail voltage signals.
Preferably, the direct drive error amplifier employs a modified OTA architecture that is based on a conventional OTA architecture by modifying its current mirror to a non-linear current mirror with a cross-coupled pair connected in parallel across a diode-connected MOS load.
Preferably, the direct drive type error amplifier includes 1 reference voltage Vref, 2 bias voltages Vb, Vp, 8 PMOS transistors: M4-M7, M11-M14, 5 NMOS tubes: M1-M3, M8 and M9, wherein M1 forms an NMOS tail current source, M2 and M3 form an NMOS differential pair transistor, M4-M7, M11 and M12 form a nonlinear current mirror, M13 and M14 form a cross-coupled pair, when the circuit is in a static state, all MOS transistors work in a saturation state, when a load changes, the gate voltage of M3 changes, wherein M4 and M5 work in a linear region, the nonlinearity of the current transfer ratio of the current mirror is realized, and other MOS transistors are still in the saturation region;
the M1 gate terminal is connected with a bias voltage Vb, the M2 gate terminal is connected with a feedback voltage Vfb, the M3 gate terminal is connected with a reference voltage Vref, the M11 and M12 gate terminals are connected with a bias voltage Vp, M1, M8 and M9 source terminal grounding terminals, the M4-M7, M13 and M14 source terminals are connected with a direct current power supply anode VDD, the M1 drain terminal is connected with the M2 and M3 source terminals, the M2 drain terminal is connected with the M11 drain terminal, the M4 gate terminal, the M6 gate terminal and the M14 gate terminal, the M3 drain terminal is connected with the M12 drain terminal, the M5 gate terminal, the M7 gate terminal and the M13 gate terminal, the M4 drain terminal is connected with the M11 and the M13 drain terminal, the M5 drain terminal is connected with the M12 and M14 drain terminal, the M6 drain terminal is connected with the M8 and the M7 drain terminal, and the M9 drain terminal is connected with the M9 drain terminal.
Preferably, the N-type power output stage includes 1 NMOS power adjusting transistor M10, 2 polysilicon resistors R1 and R2, which together form an NMOS common-drain amplifier, and when the NMOS power adjusting transistor M3878 is in a light load, M10 operates in a subthreshold region, and when the NMOS power adjusting transistor M10 is in a heavy load, M10 operates in a saturation region.
Preferably, the gate terminal of the NMOS power adjustment transistor M10 is the control terminal or the input terminal of the N-type power output stage, the drain terminal of M10 is connected to the dc power supply anode VDD, the source terminal is connected to the upper end of the resistor R1 to form the output voltage node Vo, the lower end of the resistor R1 is connected to the upper end of the resistor R2 to form the feedback voltage node Vfb, and the lower end of the resistor R2 is connected to the ground terminal.
Preferably, the adaptive impedance transient boosting circuit is formed by an NMOS bleeder tube M15, and a voltage signal with a trend opposite to that of the output voltage of the linear voltage regulator is input into the input of the NMOS bleeder tube M15.
Preferably, the specific connection relationship of the adaptive impedance transient enhancement circuit is as follows: the gate end of the NMOS bleeder tube M15 is connected with the output end of the self-adaptive bias circuit, the source end grounding end of the M15 and the drain end of the NMOS bleeder tube M15 are connected with the output voltage node Vo of the N-type power output stage, wherein the self-adaptive bias circuit is composed of M4, M6, M8 and M11 in the direct drive type error amplifier.
Preferably, the compensation capacitance is based on the principle of miller compensation.
Preferably, the anode of the compensation capacitor is connected with the output end of the direct drive type error amplifier, and the cathode of the compensation capacitor is connected with the feedback voltage node Vo of the N-type power output stage.
The beneficial effects of the invention at least comprise: compared with the existing low-dropout linear regulator, the invention reduces the number of circuit branches and improves the driving capability of the error amplifier by adopting the direct-drive type error amplifier, thereby improving the transient response capability on the premise of equal power consumption; by adopting the N-type power output stage, the pole of the output stage is raised, and the influence of load change on the pole is reduced, so that the bandwidth is increased, and the transient response is improved.
Meanwhile, the invention completes the specific circuit design based on the 130nm CMOS process. A transconductance operational amplifier is used for forming a direct drive type error amplifier, and on the basis of a traditional OTA circuit, a current transmission ratio is improved by using a nonlinear current mirror so as to improve slew rate and bandwidth; the transient performance of the circuit is improved by introducing cross coupling to improve the product of gain and gain bandwidth for the load; the slew rate of an output node is increased when heavy load jumps and light load by using the adaptive impedance transient enhancement circuit; the loop is stabilized by the compensation capacitor.
The beneficial effects of the invention relative to the prior art are further illustrated in terms of low power consumption and high transient response:
low power consumption: the power consumption is the product of the power supply voltage, the current and the time, and the static time is far longer than the dynamic time in the application of the digital-analog hybrid circuit; the power supply voltage is constant under the influence of the chip process. The design requirements for power consumption translate into a requirement for total quiescent current. The total quiescent current is the sum of the currents of the circuit branches in the quiescent state.
Compared with the prior art, the invention adopts the direct drive type error amplifier, simplifies the number of circuit branches, and can achieve the same driving capability only by smaller current. Meanwhile, the error amplifier adopts a nonlinear current mirror technology, so that the circuit can realize the performance under the condition of consuming smaller quiescent current. Thereby reducing the total quiescent current and achieving the purpose of low power consumption.
High transient response: transient response is the magnitude of the voltage at the output of the power supply that deviates from the set value and the time to recover to the set value at the instant of a jump in load current. The key to influence the transient response mainly depends on two points, the loop bandwidth (small signal) and the slew rate (large signal). Obviously, the higher the loop bandwidth, the more complete the harmonic components that the loop allows through. The better the rising edge of the step signal is maintained, the better the transient response is; the slew rate has the following functions: when the load jumps, the higher the slew rate is, the faster the charging and discharging speed of the power adjusting tube and the load is, and therefore the better the transient response is. These two criteria are defined as:
compared with the prior art, the invention adopts a direct drive type LDO architecture, reduces the number of poles, and increases the slew rate of the output node during light load jump and heavy load; the N-type power output stage is adopted, so that the position of the circuit secondary pole is raised, and the bandwidth is increased; and the slew rate of an output node is increased when heavy load jumps and light load occurs by adopting the self-adaptive impedance transient enhancement circuit. Therefore, the transient response performance of the circuit is improved from two aspects of bandwidth (small signal) and slew rate (large signal).
Drawings
In order to make the object, technical scheme and beneficial effect of the invention more clear, the invention provides the following drawings for explanation:
FIG. 1 is a schematic diagram of a low-power consumption high-transient response off-chip capacitance low dropout linear regulator according to an embodiment of the present invention;
FIG. 2 is a prior art LDO circuit diagram after a classical OTA circuit;
FIG. 3 is a cross-coupled vs. small signal diagram of a low-power consumption high transient response off-chip capacitance low dropout linear regulator in accordance with an embodiment of the present invention;
FIG. 4 is a diagram of an improved LDO circuit with low power consumption and high transient response without an off-chip capacitor for a low dropout linear regulator with low power consumption and high transient response without an off-chip capacitor according to an embodiment of the present invention.
Detailed Description
Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
Referring to fig. 1, a schematic diagram of a low power consumption high transient response off-chip capacitor-less low dropout linear regulator according to an embodiment of the present invention is shown, and fig. 4 is a corresponding circuit diagram, which includes a direct-drive error amplifier 10, an N-type power output stage 20, an adaptive impedance transient enhancement circuit 30 and a compensation capacitor 40, wherein,
the direct drive type error amplifier 10 includes two input terminals, the two input terminals are respectively directly connected to a feedback voltage node formed by a reference voltage and a resistor in the N-type power output stage 20, the output terminal thereof is connected to the control terminal of the N-type power adjustment stage, and the N-type power adjustment stage is driven according to a voltage difference between the feedback voltage of the output voltage and the reference voltage;
an N-type power output stage 20, the input terminal of which is directly connected to the output terminal of the direct-drive error amplifier 10, and the output terminal of which is the output terminal of the entire linear regulator;
an adaptive impedance transient enhancement circuit 30, the input terminal of which is directly connected to the gate terminal of the NMOS current mirror in the direct-driven error amplifier 10, and the output terminal of which is directly connected to the output terminal of the N-type power output stage 20;
and the input end of the compensation capacitor 40 is directly connected with a feedback voltage node formed by the resistor of the N-type power output stage 20, the output end of the compensation capacitor is directly connected with the input end of the N-type power output stage 20, and the compensation capacitor and the feedback resistor circuit of the N-type power output stage 20 form a compensation network.
The direct drive type error amplifier 10 employs a differential input, push-pull output structure that generates a rail-to-rail voltage signal.
The direct drive error amplifier 10 employs a modified OTA architecture that is based on a conventional OTA architecture by modifying its current mirror to a non-linear current mirror with a cross-coupled pair connected in parallel across a diode-connected MOS load.
The direct drive type error amplifier 10 includes 1 reference voltage Vref, 2 bias voltages Vb, Vp, 8 PMOS transistors: M4-M7, M11-M14, 5 NMOS tubes: M1-M3, M8 and M9, wherein M1 forms an NMOS tail current source, M2 and M3 form an NMOS differential pair transistor, M4-M7, M11 and M12 form a nonlinear current mirror, M13 and M14 form a cross-coupled pair, when the circuit is in a static state, all MOS transistors work in a saturation state, when a load changes, the gate voltage of M3 changes, wherein M4 and M5 work in a linear region, the nonlinearity of the current transfer ratio of the current mirror is realized, and other MOS transistors are still in the saturation region;
the M1 gate terminal is connected with a bias voltage Vb, the M2 gate terminal is connected with a feedback voltage Vfb, the M3 gate terminal is connected with a reference voltage Vref, the M11 and M12 gate terminals are connected with a bias voltage Vp, M1, M8 and M9 source terminal grounding terminals, the M4-M7, M13 and M14 source terminals are connected with a direct current power supply anode VDD, the M1 drain terminal is connected with the M2 and M3 source terminals, the M2 drain terminal is connected with the M11 drain terminal, the M4 gate terminal, the M6 gate terminal and the M14 gate terminal, the M3 drain terminal is connected with the M12 drain terminal, the M5 gate terminal, the M7 gate terminal and the M13 gate terminal, the M4 drain terminal is connected with the M11 and the M13 drain terminal, the M5 drain terminal is connected with the M12 and M14 drain terminal, the M6 drain terminal is connected with the M8 and the M7 drain terminal, and the M9 drain terminal is connected with the M9 drain terminal.
The N-type power output stage 20 includes 1 NMOS power adjusting transistor M10, 2 polysilicon resistors R1 and R2, which together form an NMOS common-drain amplifier, wherein M10 operates in a subthreshold region under light load, and M10 operates in a saturation region under heavy load. The gate terminal of the NMOS power adjusting transistor M10 is the control terminal or the input terminal of the N-type power output stage 20, the drain terminal of M10 is connected to the dc power supply anode VDD, the source terminal is connected to the upper end of the resistor R1 to form the output voltage node Vo, the lower end of the resistor R1 is connected to the upper end of the resistor R2 to form the feedback voltage node Vfb, and the lower end of the resistor R2 is connected to the ground terminal.
The adaptive impedance transient enhancement circuit 30 is formed by an NMOS bleeder M15, the input of which is connected to a voltage signal having a trend opposite to the output voltage of the linear regulator. The NMOS bleeder M15 and the adaptive bias circuit shared by the direct drive type error amplifier 10 are formed by directly connecting a current mirror and a diode-connected transistor, and when the load jumps from a heavy load to a light load, the direct drive type error amplifier 10 generates an increased current, which is copied by the current mirror and flows into the diode-connected transistor, and the gate-source voltage of the transistor is passively increased to adapt to the increased current, thereby generating a large bias for the bleeder NMOS and increasing the current of the bleeder, thereby achieving the capability of improving the transient response.
The connection relationship of the adaptive impedance transient enhancement circuit 30 is as follows: the gate terminal of the NMOS bleeder tube M15 is connected to the output terminal of the adaptive bias circuit, the source terminal ground terminal of M15, and the drain terminal is connected to the output voltage node Vo of the N-type power output stage 20, wherein the adaptive bias circuit is composed of M4, M6, M8, and M11 in the direct-drive error amplifier 10.
The compensation capacitor 40 is based on the principle of miller compensation and is used to stabilize the circuit, equalize overshoot voltage and over-charge recovery time. The anode of the compensation capacitor 40Cc is connected to the output of the direct drive error amplifier 10 and the cathode is connected to the feedback voltage node Vo of the N-type power output stage 20.
In the direct drive type error amplifier 10 and the N-type power output stage 20 of the present invention, when the circuit is in the working static state, the direct drive type error amplifier 10 and the N-type power output stage 20 form a negative feedback, under the action of the direct drive type error amplifier 10, two input ends of the direct drive type error amplifier 10 form a virtual short, and one end of the virtual short is connected with a fixed voltage V ref Therefore, the voltage at the node between the feedback resistors R1 and R2 is also equal to this voltage value. Under the action of the voltage division, the output voltage is
When the load changes, the LDO of the invention can adjust the response. The extreme load change can be divided into two types, namely light load jump heavy load and heavy load jump light load. When the light load jumps to the heavy load, because the output current suddenly becomes large, the output voltage drops, that is, the undershoot occurs, at this time, the voltage of the negative terminal of the direct-drive error amplifier 10 also drops, the output voltage increases, the gate voltage of the NMOS of the power regulating tube increases, the output current increases, and the output voltage recovers. In contrast, the phenomenon of heavy load, jump and light load can cause the phenomenon of overcharge.
The following is a specific embodiment of a low dropout linear regulator with low power consumption and high transient response and without off-chip capacitor, which is designed based on 130nm CMOS process and is described with reference to the accompanying drawings, but the invention is not limited to these embodiments.
Referring to fig. 4, the low-power consumption high transient response low dropout regulator circuit without off-chip capacitor according to the present invention includes a direct-drive error amplifier 10, an N-type power output stage 20, an adaptive impedance transient enhancement circuit 30 and a compensation capacitor 40.
The direct drive type error amplifier 10 is based on the traditional OTA circuit, and introduces the nonlinear current mirror technology and the cross-coupling pair technology, thereby meeting the requirements.
The conventional OTA circuit is shown in fig. 2, and the gain-bandwidth product is:
where M is the current transfer ratio, which is equal in value to the drain-to-source current ratio through transistors M4 and M6, in a conventional OTA, M is equal to the size ratio of transistors M4 to M6, I 1 Is the drain-source current, V, of the tail current source transistor M1 ov3 、V ov7 The overdrive voltages, g, of transistors M3, M7, respectively m5 Is the transconductance of transistor M5.
The slew rate is:
wherein, C GS10 Is the gate capacitance of transistor M10.
From the formula, it can be seen that there is an irreconcilable conflict between the quiescent power and the transient response.
Therefore, the invention adopts the following technical scheme to improve the traditional OTA:
nonlinear current mirror: the current mirrors (M4-M7) inside the OTA are replaced by the nonlinear current mirrors (M4-M7, M11 and M12), when the circuit is in a static state, the M4 works in a saturation region, the current transmission ratio M is equal to the size ratio of M4 to M6, the requirement of low power consumption is met, when the circuit is in a dynamic change, the M4 easily enters a linear region, the current transmission ratio M is changed, and the deeper the linear degree of the M4 is, the larger the M value is.
Cross-coupling pair: this is a negative conductance technique and as can be seen from the discussion of fig. 3, with the cross-coupled pair, transistors M5 and M14 can be equivalent to a voltage controlled voltage source and output impedance, respectively, where V in The small signal input voltage of the gate of M5 is-V due to the differential relation of the input signals in . gm is the small signal transconductance of the transistor, r o A small signal output impedance for the transistor. Conductance g between M14 and M5 m5 And g m14 In the opposite direction, it can be equivalent to M5 transconductance g m5 Reduction, combined with previous formula, g m5 When the gain is reduced, the amplification factor of the circuit is improved, the dominant pole is reduced, and the gain-bandwidth product is increased.
Through the two improvements, the current transmission ratio M and the transconductance g are successfully improved m5 And low power consumption and high transient response are realized.
The direct drive type error amplifier 10 comprises M1-M9 and M11-M14, wherein M1-M9 are traditional OTA circuits, M1 is a tail current source, M2 and M3 are differential pair transistors, M4 and M5 are loads adopting a diode connection method, M6 and M7 are current sources controlled by gate voltages of M4 and M5, and M8 and M9 are current mirrors; the introduction of M11, 12 realizes the nonlinearity of M4, 5 grid voltage change, forms a nonlinear current mirror with M6, 7, and M13, 14 are introduced cross-coupling pairs.
The N-type power output stage 20 includes an NMOS power transistor M10, and feedback resistors R1 and R2, which together form a common drain amplifier.
The direct drive type error amplifier 10 and the N-type power stage can increase the slew rate during light load jump and heavy load, and in order to solve the problem of insufficient slew rate during heavy load jump and light load, the invention provides the following technical scheme:
adaptive impedance transient enhancement techniques: when heavy load jumps and light load, the M15 gate voltage is increased, and the charge on the load capacitor at the output point can be quickly drained from the conductive channel of the M15. Thereby speeding up the recovery of the output voltage.
The adaptive impedance transient enhancement circuit 30 is based on the direct drive type error amplifier 10, and the grid voltage of M8 is extracted as a control signal, and the drain is connected with the source end of M10.
Finally, it is noted that the above-mentioned preferred embodiments illustrate rather than limit the invention, and that, although the invention has been described in detail with reference to the above-mentioned preferred embodiments, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the invention as defined by the appended claims.
Claims (10)
1. A low-power consumption high transient response low dropout linear regulator without off-chip capacitor is characterized in that the regulator comprises a direct drive type error amplifier, an N-type power output stage, a self-adaptive impedance transient enhancement circuit and a compensation capacitor, wherein,
the direct drive type error amplifier comprises two input ends, the two input ends are respectively and directly connected with a feedback voltage node formed by a reference voltage and a resistor in the N-type power output stage, the output end of the direct drive type error amplifier is connected with the control end of the N-type power regulation stage, and the direct drive type error amplifier drives the N-type power regulation stage according to the voltage difference between the feedback voltage of the output voltage and the reference voltage;
the input end of the N-type power output stage is directly connected with the output end of the direct drive type error amplifier, and the output end of the N-type power output stage is the output end of the whole linear voltage stabilizer;
the input end of the adaptive impedance transient enhancement circuit is directly connected with the gate end of an NMOS current mirror in the direct-driven error amplifier, and the output end of the adaptive impedance transient enhancement circuit is directly connected with the output end of the N-type power output stage;
the input end of the compensation capacitor is directly connected with a feedback voltage node formed by the resistor of the N-type power output stage, the output end of the compensation capacitor is directly connected with the input end of the N-type power output stage, and the compensation capacitor and a feedback resistor circuit of the N-type power output stage form a compensation network.
2. The low-power-consumption high-transient-response off-chip-capacitor-less linear voltage regulator of claim 1, wherein the direct-drive error amplifier employs a differential input, push-pull output architecture, and the push-pull output architecture generates a rail-to-rail voltage signal.
3. The low power consumption high transient response off-chip capacitor-less LDO linear regulator of claim 1, wherein the direct drive error amplifier employs a modified OTA architecture that is modified from a conventional OTA architecture by modifying its current mirror to a non-linear current mirror with a cross-coupled pair in parallel across a diode-connected MOS load.
4. The low-power-consumption high-transient-response off-chip-capacitor-less linear voltage regulator according to claim 3, wherein the direct-drive error amplifier comprises 1 reference voltage Vref, 2 bias voltages Vb, Vp, 8 PMOS transistors: M4-M7, M11-M14, 5 NMOS tubes: M1-M3, M8 and M9, wherein M1 forms an NMOS tail current source, M2 and M3 form an NMOS differential pair transistor, M4-M7, M11 and M12 form a nonlinear current mirror, M13 and M14 form a cross-coupled pair, when the circuit is in a static state, all MOS transistors work in a saturation state, when a load changes, the gate voltage of M3 changes, wherein M4 and M5 work in a linear region, the nonlinearity of the current transfer ratio of the current mirror is realized, and other MOS transistors are still in the saturation region;
the M1 gate terminal is connected with a bias voltage Vb, the M2 gate terminal is connected with a feedback voltage Vfb, the M3 gate terminal is connected with a reference voltage Vref, the M11 and M12 gate terminals are connected with a bias voltage Vp, M1, M8 and M9 source terminal grounding terminals, the M4-M7, M13 and M14 source terminals are connected with a direct current power supply anode VDD, the M1 drain terminal is connected with the M2 and M3 source terminals, the M2 drain terminal is connected with the M11 drain terminal, the M4 gate terminal, the M6 gate terminal and the M14 gate terminal, the M3 drain terminal is connected with the M12 drain terminal, the M5 gate terminal, the M7 gate terminal and the M13 gate terminal, the M4 drain terminal is connected with the M11 and the M13 drain terminal, the M5 drain terminal is connected with the M12 and M14 drain terminal, the M6 drain terminal is connected with the M8 and the M7 drain terminal, and the M9 drain terminal is connected with the M9 drain terminal.
5. The linear regulator of claim 4, wherein the N-type power output stage comprises 1 NMOS power adjustment transistor M10, and 2 polysilicon resistors R1 and R2, which together form an NMOS common-drain amplifier, wherein M10 operates in a subthreshold region under light load, and M10 operates in a saturation region under heavy load.
6. The low-power-consumption high-transient-response off-chip-capacitor-free low-dropout linear regulator of claim 5, wherein the gate terminal of the NMOS power regulating tube M10 is the control terminal or the input terminal of the N-type power output stage, the drain terminal of the M10 is connected to the anode VDD of the DC power supply, the source terminal is connected to the upper terminal of a resistor R1 to form an output voltage node Vo, the lower terminal of the resistor R1 is connected to the upper terminal of a resistor R2 to form a feedback voltage node Vfb, and the lower terminal of the resistor R2 is connected to the ground terminal.
7. The low power consumption high transient response off-chip capacitor-less LDO (linear regulator) according to claim 6, wherein the adaptive impedance transient boost circuit is composed of an NMOS bleeder tube M15, and the input of the NMOS bleeder tube M15 is connected with a voltage signal with a trend opposite to the output voltage of the linear regulator.
8. The low-power-consumption high-transient-response off-chip-capacitor-less linear voltage regulator of claim 7, wherein the adaptive impedance transient enhancement circuit has a specific connection relationship: the gate end of the NMOS bleeder tube M15 is connected with the output end of the self-adaptive bias circuit, the source end grounding end of the M15 and the drain end of the NMOS bleeder tube M15 are connected with the output voltage node Vo of the N-type power output stage, wherein the self-adaptive bias circuit is composed of M4, M6, M8 and M11 in the direct drive type error amplifier.
9. The low power consumption high transient response off-chip capacitor-less low dropout regulator of claim 1, wherein the compensation capacitor is based on the principle of miller compensation.
10. The low power consumption high transient response off-chip capacitor low dropout regulator of claim 8, wherein an anode of the compensation capacitor is connected to an output terminal of the direct drive type error amplifier, and a cathode of the compensation capacitor is connected to a feedback voltage node Vo of the N-type power output stage.
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| CN117631747A (en) * | 2023-12-01 | 2024-03-01 | 景略半导体(上海)有限公司 | Impedance matching circuit, system and self-terminating transmitter |
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| CN117631747A (en) * | 2023-12-01 | 2024-03-01 | 景略半导体(上海)有限公司 | Impedance matching circuit, system and self-terminating transmitter |
| CN117631747B (en) * | 2023-12-01 | 2024-05-28 | 景略半导体(上海)有限公司 | Impedance matching circuit, system and self-terminating transmitter |
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