CN112859984B - Linear voltage regulator circuit with high power supply rejection ratio and fast transient state - Google Patents
Linear voltage regulator circuit with high power supply rejection ratio and fast transient state Download PDFInfo
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- CN112859984B CN112859984B CN202110018965.3A CN202110018965A CN112859984B CN 112859984 B CN112859984 B CN 112859984B CN 202110018965 A CN202110018965 A CN 202110018965A CN 112859984 B CN112859984 B CN 112859984B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
Abstract
The invention provides a high power supply rejection ratio fast transient linear voltage regulator circuit, which changes the internal bias current of the linear voltage regulator by a current self-adaptive bias circuit along with the magnitude of load current; a differential operational amplifier circuit is arranged to increase the loop gain of the linear voltage regulator and improve the precision of the output voltage; the nested inverted voltage follower circuit module is arranged to serve as an output stage of the linear voltage regulator and is used for increasing the loop bandwidth of the linear voltage regulator; the finally obtained linear voltage regulator circuit has the advantages of fast transient response, high power supply rejection ratio, self-adaptive static power consumption, low load regulation rate, low linear regulation rate and the like, can provide a stable voltage source with high power supply rejection ratio for an integrated circuit, and improves the performance of an integrated chip.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a high power supply rejection ratio fast transient linear voltage regulator circuit.
Background
The low dropout regulator is an important component of modern analog integrated circuits, and with the development of intelligent devices, more and more devices are driven by batteries and work in complex environments, and the performances of high power supply rejection ratio and fast transient response become more important.
The power supply rejection ratio, transient response, linear regulation rate, load regulation rate, power consumption and other performances of the low dropout linear regulator are main performance indexes. The chinese invention patent application with publication number CN106354186A discloses a low dropout regulator in 2017, month 1 and 25, and the disclosed circuit effectively expands the loop bandwidth, improves the transient characteristics, is simple in implementation, but does not have the characteristics of high power supply rejection ratio, fast transient response and the like under the working condition of low power consumption, and may affect the device performance in the practical application process.
Disclosure of Invention
The invention provides a high-power-supply-rejection-ratio fast-transient linear voltage regulator circuit for overcoming the technical defect that the conventional low-dropout linear voltage regulator does not have high power supply rejection ratio and fast transient response characteristics under the working condition of low power consumption.
In order to solve the technical problems, the technical scheme of the invention is as follows:
a high power supply rejection ratio fast transient linear voltage regulator circuit comprises a differential operational amplifier, a nested inverted voltage follower circuit module and a current self-adaptive bias circuit module; wherein:
the differential operational amplifier is electrically connected with the nested inverted voltage follower circuit module;
the current self-adaptive bias circuit module is electrically connected with the differential operational amplifier and the nested inverted voltage follower circuit module;
the differential operational amplifier is used for increasing the loop gain of the linear voltage stabilizer and improving the precision of the output voltage;
the nested inverted voltage follower circuit module is used as an output stage of the linear voltage stabilizer and provides load carrying capacity; and is connected with the differential operational amplifier;
the differential operational amplifier further improves the linear voltage regulator performance.
The nested inverted voltage follower circuit module comprises an output stage voltage follower circuit and a nested stage voltage follower circuit; wherein:
the input end of the nested level voltage follower circuit is electrically connected with the current self-adaptive bias circuit module;
the nested level voltage follower circuit is electrically connected with the output level voltage follower circuit and is used as one part of an internal loop of the output level voltage follower circuit;
and the output end of the output-stage voltage follower circuit is electrically connected with the inverting input end of the differential operational amplifier and is used as the output end of the linear voltage stabilizer.
The output-stage voltage follower circuit and the nested-stage voltage follower circuit are both inverted voltage follower circuits, and the nested inverted voltage follower circuit module is formed in a nested mode.
The nested-stage voltage follower circuit comprises PMOS tubes M2 and M1 and an NMOS tube MB 4; the output stage voltage follower circuit comprises PMOS tubes MP, M11 and an NMOS tube MB 5; wherein:
the M2 source electrode, the MP source electrode and the power supply VDDElectrically connecting;
the M2 gate is electrically connected with the M1 drain and the MB4 source;
the drain of the M2 is electrically connected with the source of the M1 and the MP gate;
the MP drain is electrically connected with the source of the M11, and the connection point is used as the output end of the linear voltage stabilizer and is electrically connected with the inverting input end of the differential operational amplifier;
the M11 gate is electrically connected with the differential operational amplifier output end;
the M1 gate is electrically connected with the current adaptive bias circuit module input end, the M11 drain and the MB5 source;
the MB4 grid and the MB5 grid are electrically connected with the input end of the current self-adaptive bias circuit module; meanwhile, the MB4 grid and the MB5 grid are electrically connected with the input end of the differential operational amplifier;
the drain of MB4 and the drain of MB5 are grounded.
The MB4 gate, the MB5 gate and the MB6 gate are electrically connected with the drain of the current adaptive bias circuit module MB 3; the NMOS tube MB4, the NMOS tube MB5 and the NMOS tube MB6 are connected in a current mirror structure, and bias is provided by the current self-adaptive bias circuit module.
Wherein the current self-adaptive bias circuit module comprises PMOS tubes MB1, MB3, NMOS tube MB2 and a capacitor CB(ii) a Wherein:
the source of MB1 and a power supply VDDElectrically connecting;
the MB1 gate is electrically connected with the M1 gate;
the MB1 drain is electrically connected with the MB2 source, the MB3 gate, the MB3 source and the MB2 gate;
the drain of the MB3 is electrically connected with the gate of a bias current mirror MB6 of the differential operational amplifier;
the drain of the MB3 is electrically connected with the gates of bias current mirrors MB4 and MB5 of the nested inverted voltage follower circuit module;
the capacitor CBOne end of the resistor is electrically connected with the drain of the MB3, and the other end of the resistor is grounded;
the MB2 drain is connected to ground.
Wherein, in the current adaptive bias circuit module,the NMOS tube MB2 adopts a diode connection mode; the PMOS tube MB3 is connected with the capacitor C through a diodeBA low pass filter is constructed.
Wherein a resistor R is connected between the output of the nested inverted voltage follower circuit module and the output of the differential operational amplifierCAnd a capacitor CCTo generate a left half-plane zero to enhance the stability of the circuit.
Wherein a load capacitor C is connected across the output stage of the linear voltage regulatorLAnd an equivalent resistance RESRTo produce a left half-plane zero for circuit system stability.
Compared with the prior art, the technical scheme of the invention has the beneficial effects that:
the invention provides a high power supply rejection ratio fast transient linear voltage regulator circuit, which changes the internal bias current of the linear voltage regulator by a current self-adaptive bias circuit along with the magnitude of load current; a differential operational amplifier circuit is arranged to increase the loop gain of the linear voltage regulator and improve the precision of the output voltage; the nested inverted voltage follower circuit module is arranged to serve as an output stage of the linear voltage regulator and is used for increasing the loop bandwidth of the linear voltage regulator; the finally obtained linear voltage regulator circuit has the advantages of fast transient response, high power supply rejection ratio, self-adaptive static power consumption, low load regulation rate, low linear regulation rate and the like, can provide a stable voltage source with high power supply rejection ratio for an integrated circuit, and improves the performance of an integrated chip.
Drawings
FIG. 1 is a circuit diagram provided by an embodiment of the present invention;
FIG. 2 is a topology diagram of a linear regulator according to an embodiment of the present invention;
FIG. 3 is a diagram of a loop small signal model provided by an embodiment of the present invention;
wherein: 1. a differential operational amplifier; 2. the embedded inverted voltage follower circuit module; 3. and the current self-adaptive bias circuit module.
Detailed Description
The drawings are for illustrative purposes only and are not to be construed as limiting the patent;
for the purpose of better illustrating the embodiments, certain features of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product;
it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The technical solution of the present invention is further described below with reference to the accompanying drawings and examples.
Example 1
As shown in fig. 1, an embodiment of the present invention provides a linear regulator circuit with high power supply rejection ratio and fast transient, including: the circuit comprises a differential operational amplifier 1, a nested inverted voltage follower circuit module 2 and a current self-adaptive bias circuit module 3;
the differential operational amplifier 1 is connected with the nested inverted voltage follower circuit module 2, and the current self-adaptive bias circuit module 3 is connected with the differential operational amplifier 1 and the nested inverted voltage follower circuit module 2;
the differential operational amplifier 1 is used for increasing the loop gain of the linear voltage stabilizer and improving the precision of output voltage;
the nested inverted voltage follower circuit module 2 is used as an output stage of the linear voltage regulator and provides load carrying capacity; and is connected with the differential operational amplifier 1; wherein the differential operational amplifier 1 further improves the linear regulator performance;
the nested inverted voltage follower circuit module 2 comprises an output stage voltage follower circuit and a nested stage voltage follower circuit; the output stage voltage follower circuit consists of PMOS tubes MP, M11 and an NMOS tube MB 5; the nested-stage voltage follower circuit consists of PMOS tubes M2, M1 and an NMOS tube MB 4; the nested stage voltage follower circuit is used as one part of an inner loop of the output stage voltage follower circuit, namely the drain of the M11 is connected with the gate of the M1, and then the source of the M1 is connected with the gate of the MP; the output stage voltage following circuit and the nested stage voltage following circuit are both inverted voltage following circuits and are nestedThe nested inverted voltage follower circuit module is formed in a form; the MB4, MB5 and MB6 are connected in a current mirror structure, and are provided with bias by the current self-adaptive bias circuit module; the inverting input end of the differential operational amplifier 1 and the output V of the nested inverted voltage follower circuit module 2outThe output of the differential operational amplifier 1 is connected with the grid of the M11; meanwhile, R is bridged between the output of the nested inverted voltage follower circuit module 2 and the output of the differential operational amplifier 1CAnd CCTo generate a left half-plane zero to enhance the stability of the system; in addition, the output end of the linear voltage stabilizer is provided with a load capacitor CLAnd an equivalent series resistance RESRA left half-plane zero is generated to enhance system stability.
The current self-adaptive bias circuit module 3 is used for changing the internal bias current of the linear voltage regulator according to the magnitude of the load current, and achieving the purpose of system stability by controlling the bias current.
Further, the nested inverted voltage follower circuit module 2 helps to increase the loop bandwidth of the linear regulator; the rest MOS tubes except the MP of the nested inverted voltage follower circuit module 2 work in a saturation region, so that the better performance is ensured.
Further, the current adaptive bias circuit module 3 comprises PMOS transistors MB1, MB3, NMOS transistor MB2 and a capacitor CB(ii) a The gate of the MB1 is connected to the gate of the M1 so that the gate dc potential of the M1 changes when the load current changes, thereby changing the current of the MB1 and thus the current flowing through the MB 2; since the MB2 is diode-connected, it can be used as a current mirror to provide gate voltage to the MB4, MB5, MB6 of other circuit modules.
Further, a diode in the current adaptive bias circuit module is connected with the MOS transistor MB3 and the MOS transistor CBA low-pass filter is formed to provide a stable and effective bias for the current mirror of other modules; since the MB1 and M1 use the same gate connection, small messages are made in the circuitSignals flow through the MB1 and the MB2, so that other modules of the linear voltage regulator circuit form positive feedback to influence the stability of the system; and the MB3 and CBThe connections of (a) constitute a low-pass filter so that small signals cannot form excessive positive feedback interference.
Further, the current adaptive bias circuit module 3, the nested inverted voltage follower circuit module 2 and the differential operational amplifier 1 are connected in such a way that the quiescent current consumed by the linear regulator circuit changes under different load currents, so that the loop bandwidth of the linear regulator circuit also increases with the increase of the load current; since the loop bandwidth of the linear voltage regulator circuit is changed, the high power supply rejection ratio performance and the performance of quick transient response are realized.
In a specific implementation process, the embodiment of the invention provides a high power supply rejection ratio fast transient linear voltage regulator circuit, which comprises a differential operational amplifier 1, a nested inverted voltage follower circuit module 2 and a current self-adaptive bias circuit module 3; the differential operational amplifier circuit 1 is used for increasing the loop gain of the linear voltage regulator and improving the precision of output voltage; the nested inverted voltage follower circuit module 2 is used as an output stage of the linear voltage regulator and the nested structure is used for increasing the loop bandwidth of the linear voltage regulator; and the current self-adaptive bias circuit 3 is used for changing the internal bias current of the linear voltage regulator according to the load current. The embodiment of the invention has the advantages of fast transient response, high power supply rejection ratio, self-adaptive static power consumption, low load regulation rate, low linear regulation rate and the like, can provide a stable voltage source with high power supply rejection ratio for an integrated circuit, and improves the performance of the integrated chip.
Example 2
More specifically, on the basis of embodiment 1, the nested inverted voltage follower circuit module 2 has the gate of the PMOS transistor M11 as an input and the source as an output, and the output voltage V can be designed when a proper gate voltage of M11 is givenoutThe self-feedback loop of the nested inverted voltage follower circuit module is used as the internal stability of the output voltageA pressure regulation loop.
The differential operational amplifier 1 is connected to the nested inverted voltage follower circuit module 2, in this embodiment, as shown in fig. 1 and fig. 2. The connection mode enables the differential operational amplifier 1 and the nested inverted voltage follower circuit module 2 to form an external regulation loop, and as a result, the linear regulation rate and the load regulation rate of the low dropout linear regulator are further improved.
The current self-adaptive bias circuit module 3 is formed by a node V of the nested inverted voltage follower circuit module 2FPhase connection control, node V when load current changesFThe DC potential of the capacitor is changed accordingly. Load current increase node VFThe dc potential of (b) decreases, thereby increasing the current through MB1, MB2, and vice versa. To prevent the input of loop small signals to the gates of MB4, MB5 and MB6 from causing the loop to constitute positive feedback or making the system unstable, diode-connected PMOS transistors MB3 and C are usedBThe low-pass filter is formed to enable the current self-adaptive bias circuit module to only provide direct current bias.
Referring to fig. 3, which is a simplified small-signal model of the high supply rejection ratio fast transient linear regulator circuit, a key model of the circuit and key parasitic capacitances are depicted.
The loop transfer function can be derived according to the small signal simplified model as follows:
the loop transfer function reveals the pole-zero distribution of the circuit, which is helpful for analyzing and designing and adjusting circuit parameters to achieve the optimal performance.
It should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.
Claims (7)
1. A high power supply rejection ratio fast transient linear voltage regulator circuit is characterized by comprising a differential operational amplifier (1), a nested inverted voltage follower circuit module (2) and a current self-adaptive bias circuit module (3); wherein:
the differential operational amplifier (1) is electrically connected with the nested inverted voltage follower circuit module (2);
the current self-adaptive bias circuit module (3) is electrically connected with the differential operational amplifier (1) and the nested inverted voltage follower circuit module (2);
the differential operational amplifier (1) is used for increasing the loop gain of the linear voltage regulator and improving the precision of output voltage;
the nested inverted voltage follower circuit module (2) is used as an output stage of the linear voltage regulator and provides load capacity; and is connected with the differential operational amplifier (1);
the differential operational amplifier (1) further improves the performance of the linear voltage regulator;
wherein the nested inverted voltage follower circuit module (2) comprises an output stage voltage follower circuit and a nested stage voltage follower circuit; wherein:
the input end of the nested level voltage follower circuit is electrically connected with the current self-adaptive bias circuit module (3);
the nested level voltage follower circuit is electrically connected with the output level voltage follower circuit and is used as one part of an internal loop of the output level voltage follower circuit;
the output end of the output-stage voltage follower circuit is electrically connected with the inverting input end of the differential operational amplifier (1) and is used as the output end of the linear voltage stabilizer;
the nested stage voltage follower circuit comprises PMOS tubes M2, M1 and an NMOS tube MB 4; the output stage voltage follower circuit comprises PMOS tubes MP, M11 and an NMOS tube MB 5; wherein:
the M2 source electrode, the MP source electrode and the power supply VDDElectrically connecting;
the M2 gate is electrically connected with the M1 drain and the MB4 source;
the drain of the M2 is electrically connected with the source of the M1 and the MP gate;
the MP drain electrode is electrically connected with the source electrode of the M11, and the connection point is used as the output end of the linear voltage stabilizer and is electrically connected with the inverting input end of the differential operational amplifier (1);
the grid of the M11 is electrically connected with the output end of the differential operational amplifier (1);
the M1 grid is electrically connected with the input end of the current self-adaptive bias circuit module (3), the M11 drain and the MB5 source;
the MB4 grid and the MB5 grid are electrically connected with the input end of the current self-adaptive bias circuit module (3); meanwhile, the MB4 grid and the MB5 grid are electrically connected with the input end of the differential operational amplifier (1);
the drain of the MB4 and the drain of the MB5 are grounded;
the NMOS tube MB4 and the NMOS tube MB5 are connected in a current mirror structure, and the current self-adaptive bias circuit module (3) provides bias.
2. The linear regulator circuit with high power supply rejection ratio and fast transient state as claimed in claim 1, characterized in that said output stage voltage follower circuit and nested stage voltage follower circuit are inverted voltage follower circuits, and said nested inverted voltage follower circuit module (2) is formed by nesting.
3. The linear regulator circuit with high power supply rejection ratio and fast transient of claim 1, wherein the current adaptive bias circuit module (3) comprises PMOS transistors MB1, MB3 and NMOS transistors MB2 and a capacitor CB(ii) a Wherein:
the source of MB1 and a power supply VDDElectrically connecting;
the MB1 grid is electrically connected with the input end of the nested inverted voltage follower circuit module (2);
the MB1 drain is electrically connected with the MB2 source, the MB3 gate, the MB3 source and the MB2 gate;
the drain of the MB3 is electrically connected with the input end of the differential operational amplifier (1) and the input end of the current self-adaptive bias circuit module (3);
the capacitor CBOne end of the resistor is electrically connected with the drain of the MB3, and the other end of the resistor is grounded;
the MB2 drain is connected to ground.
4. The linear regulator circuit with high power supply rejection ratio and fast transient of claim 1, wherein the current adaptive bias circuit module (3) comprises PMOS transistors MB1, MB3 and NMOS transistors MB2 and a capacitor CB(ii) a Wherein:
the source of MB1 and a power supply VDDElectrically connecting;
the MB1 gate is electrically connected with the M1 gate;
the MB1 drain is electrically connected with the MB2 source, the MB3 gate, the MB3 source and the MB2 gate;
the MB3 drain is electrically connected with the input end of the differential operational amplifier (1), the MB4 gate and the MB5 gate;
the capacitor CBOne end of the resistor is electrically connected with the drain of the MB3, and the other end of the resistor is grounded;
the MB2 drain is connected to ground.
5. The linear regulator circuit with high power supply rejection ratio and fast transient state as claimed in claim 4, characterized in that in said current adaptive bias circuit module (3), said NMOS transistor MB2 is diode-connected; the PMOS tube MB3 is connected with the capacitor C through a diodeBA low pass filter is constructed.
6. A high supply rejection ratio fast transient linear regulator circuit as claimed in any one of claims 1 to 5, wherein said nested inverted voltage follower circuit block (2)) A resistor R is connected between the output and the output of the differential operational amplifier (1)CAnd a capacitor CCTo generate a left half-plane zero to enhance the stability of the circuit.
7. The linear regulator circuit according to claim 6, wherein a load capacitor C is connected across the output stage of the linear regulatorLAnd an equivalent resistance RESRTo produce a left half-plane zero for circuit system stability.
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| CN202110018965.3A CN112859984B (en) | 2021-01-07 | 2021-01-07 | Linear voltage regulator circuit with high power supply rejection ratio and fast transient state |
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| CN112859984B true CN112859984B (en) | 2021-11-26 |
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2021
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| US3949278A (en) * | 1974-12-31 | 1976-04-06 | International Business Machines Corporation | Document transfer device drive |
| CN102722213A (en) * | 2012-06-26 | 2012-10-10 | 昆明物理研究所 | Photovoltaic detector read-out unit circuit applying inverted voltage follower |
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