CN112859984A - Linear voltage regulator circuit with high power supply rejection ratio and fast transient state - Google Patents

Linear voltage regulator circuit with high power supply rejection ratio and fast transient state Download PDF

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CN112859984A
CN112859984A CN202110018965.3A CN202110018965A CN112859984A CN 112859984 A CN112859984 A CN 112859984A CN 202110018965 A CN202110018965 A CN 202110018965A CN 112859984 A CN112859984 A CN 112859984A
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electrically connected
voltage follower
gate
power supply
circuit module
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李儒国
谭洪舟
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Sun Yat Sen University
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    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
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    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
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Abstract

The invention provides a high power supply rejection ratio fast transient linear voltage regulator circuit, which changes the internal bias current of the linear voltage regulator by a current self-adaptive bias circuit along with the magnitude of load current; a differential operational amplifier circuit is arranged to increase the loop gain of the linear voltage regulator and improve the precision of the output voltage; the nested inverted voltage follower circuit module is arranged to serve as an output stage of the linear voltage regulator and is used for increasing the loop bandwidth of the linear voltage regulator; the finally obtained linear voltage regulator circuit has the advantages of fast transient response, high power supply rejection ratio, self-adaptive static power consumption, low load regulation rate, low linear regulation rate and the like, can provide a stable voltage source with high power supply rejection ratio for an integrated circuit, and improves the performance of an integrated chip.

Description

Linear voltage regulator circuit with high power supply rejection ratio and fast transient state
Technical Field
The invention relates to the field of integrated circuits, in particular to a high power supply rejection ratio fast transient linear voltage regulator circuit.
Background
The low dropout regulator is an important component of modern analog integrated circuits, and with the development of intelligent devices, more and more devices are driven by batteries and work in complex environments, and the performances of high power supply rejection ratio and fast transient response become more important.
The power supply rejection ratio, transient response, linear regulation rate, load regulation rate, power consumption and other performances of the low dropout linear regulator are main performance indexes. The chinese invention patent application with publication number CN106354186A discloses a low dropout regulator in 2017, month 1 and 25, and the disclosed circuit effectively expands the loop bandwidth, improves the transient characteristics, is simple in implementation, but does not have the characteristics of high power supply rejection ratio, fast transient response and the like under the working condition of low power consumption, and may affect the device performance in the practical application process.
Disclosure of Invention
The invention provides a high-power-supply-rejection-ratio fast-transient linear voltage regulator circuit for overcoming the technical defect that the conventional low-dropout linear voltage regulator does not have high power supply rejection ratio and fast transient response characteristics under the working condition of low power consumption.
In order to solve the technical problems, the technical scheme of the invention is as follows:
a high power supply rejection ratio fast transient linear voltage regulator circuit comprises a differential operational amplifier, a nested inverted voltage follower circuit module and a current self-adaptive bias circuit module; wherein:
the differential operational amplifier is electrically connected with the nested inverted voltage follower circuit module;
the current self-adaptive bias circuit module is electrically connected with the differential operational amplifier and the nested inverted voltage follower circuit module;
the differential operational amplifier is used for increasing the loop gain of the linear voltage stabilizer and improving the precision of the output voltage;
the nested inverted voltage follower circuit module is used as an output stage of the linear voltage stabilizer and provides load carrying capacity; and is connected with the differential operational amplifier;
the differential operational amplifier further improves the linear voltage regulator performance.
The nested inverted voltage follower circuit module comprises an output stage voltage follower circuit and a nested stage voltage follower circuit; wherein:
the input end of the nested level voltage follower circuit is electrically connected with the current self-adaptive bias circuit module;
the nested level voltage follower circuit is electrically connected with the output level voltage follower circuit and is used as one part of an internal loop of the output level voltage follower circuit;
and the output end of the output-stage voltage follower circuit is electrically connected with the inverting input end of the differential operational amplifier and is used as the output end of the linear voltage stabilizer.
The output-stage voltage follower circuit and the nested-stage voltage follower circuit are both inverted voltage follower circuits, and the nested inverted voltage follower circuit module is formed in a nested mode.
The nested-stage voltage follower circuit comprises PMOS tubes M2 and M1 and an NMOS tube MB 4; the output stage voltage follower circuit comprises PMOS tubes MP, M11 and an NMOS tube MB 5; wherein:
the M2 source electrode, the MP source electrode and the power supply VDDElectrically connecting;
the M2 gate is electrically connected with the M1 drain and the MB4 source;
the drain of the M2 is electrically connected with the source of the M1 and the MP gate;
the MP drain is electrically connected with the source of the M11, and the connection point is used as the output end of the linear voltage stabilizer and is electrically connected with the inverting input end of the differential operational amplifier;
the M11 gate is electrically connected with the differential operational amplifier output end;
the M1 gate is electrically connected with the current adaptive bias circuit module input end, the M11 drain and the MB5 source;
the MB4 grid and the MB5 grid are electrically connected with the input end of the current self-adaptive bias circuit module; meanwhile, the MB4 grid and the MB5 grid are electrically connected with the input end of the differential operational amplifier;
the drain of MB4 and the drain of MB5 are grounded.
The MB4 gate, the MB5 gate and the MB6 gate are electrically connected with the drain of the current adaptive bias circuit module MB 3; the NMOS tube MB4, the NMOS tube MB5 and the NMOS tube MB6 are connected in a current mirror structure, and bias is provided by the current self-adaptive bias circuit module.
Wherein the current self-adaptive bias circuit module comprises PMOS tubes MB1, MB3, NMOS tube MB2 and a capacitor CB(ii) a Wherein:
the source of MB1 and a power supply VDDElectrically connecting;
the MB1 gate is electrically connected with the M1 gate;
the MB1 drain is electrically connected with the MB2 source, the MB3 gate, the MB3 source and the MB2 gate;
the drain of the MB3 is electrically connected with the gate of a bias current mirror MB6 of the differential operational amplifier;
the drain of the MB3 is electrically connected with the gates of bias current mirrors MB4 and MB5 of the nested inverted voltage follower circuit module;
the capacitor CBOne end of the resistor is electrically connected with the drain of the MB3, and the other end of the resistor is grounded;
the MB2 drain is connected to ground.
In the current adaptive bias circuit module, the NMOS transistor MB2 is diode-connected; the PMOS tube MB3 is connected with the capacitor C through a diodeBA low pass filter is constructed.
Wherein a resistor R is connected between the output of the nested inverted voltage follower circuit module and the output of the differential operational amplifierCAnd a capacitor CCTo generate a left half-plane zero to enhance the stability of the circuit.
Wherein a load capacitor C is connected across the output stage of the linear voltage regulatorLAnd an equivalent resistance RESRTo produce a left half-plane zero for circuit system stability.
Compared with the prior art, the technical scheme of the invention has the beneficial effects that:
the invention provides a high power supply rejection ratio fast transient linear voltage regulator circuit, which changes the internal bias current of the linear voltage regulator by a current self-adaptive bias circuit along with the magnitude of load current; a differential operational amplifier circuit is arranged to increase the loop gain of the linear voltage regulator and improve the precision of the output voltage; the nested inverted voltage follower circuit module is arranged to serve as an output stage of the linear voltage regulator and is used for increasing the loop bandwidth of the linear voltage regulator; the finally obtained linear voltage regulator circuit has the advantages of fast transient response, high power supply rejection ratio, self-adaptive static power consumption, low load regulation rate, low linear regulation rate and the like, can provide a stable voltage source with high power supply rejection ratio for an integrated circuit, and improves the performance of an integrated chip.
Drawings
FIG. 1 is a circuit diagram provided by an embodiment of the present invention;
FIG. 2 is a topology diagram of a linear regulator according to an embodiment of the present invention;
FIG. 3 is a diagram of a loop small signal model provided by an embodiment of the present invention;
wherein: 1. a differential operational amplifier; 2. the embedded inverted voltage follower circuit module; 3. and the current self-adaptive bias circuit module.
Detailed Description
The drawings are for illustrative purposes only and are not to be construed as limiting the patent;
for the purpose of better illustrating the embodiments, certain features of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product;
it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The technical solution of the present invention is further described below with reference to the accompanying drawings and examples.
Example 1
As shown in fig. 1, an embodiment of the present invention provides a linear regulator circuit with high power supply rejection ratio and fast transient, including: the circuit comprises a differential operational amplifier 1, a nested inverted voltage follower circuit module 2 and a current self-adaptive bias circuit module 3;
the differential operational amplifier 1 is connected with the nested inverted voltage follower circuit module 2, and the current self-adaptive bias circuit module 3 is connected with the differential operational amplifier 1 and the nested inverted voltage follower circuit module 2;
the differential operational amplifier 1 is used for increasing the loop gain of the linear voltage stabilizer and improving the precision of output voltage;
the nested inverted voltage follower circuit module 2 is used as an output stage of the linear voltage regulator and provides load carrying capacity; and is connected with the differential operational amplifier 1; wherein the differential operational amplifier 1 further improves the linear regulator performance;
the nested inverted voltage follower circuit module 2 comprises an output stage voltage follower circuit and a nested stage voltage follower circuit; the output stage voltage follower circuit consists of PMOS tubes MP, M11 and an NMOS tube MB 5; the nested-stage voltage follower circuit consists of PMOS tubes M2, M1 and an NMOS tube MB 4; the nested stage voltage follower circuit is used as one part of an inner loop of the output stage voltage follower circuit, namely the drain of the M11 is connected with the gate of the M1, and then the source of the M1 is connected with the gate of the MP; the output-stage voltage following circuit and the nested-stage voltage following circuit are both inverted voltage following circuits, and a nested inverted voltage following circuit module is formed in a nested manner; the MB4, MB5 and MB6 are connected in a current mirror structure, and are provided with bias by the current self-adaptive bias circuit module; the inverting input end of the differential operational amplifier 1 and the output V of the nested inverted voltage follower circuit module 2outThe output of the differential operational amplifier 1 is connected with the grid of the M11; meanwhile, R is bridged between the output of the nested inverted voltage follower circuit module 2 and the output of the differential operational amplifier 1CAnd CCTo generate a left half-plane zero to enhance the stability of the system; in addition, the output end of the linear voltage stabilizer is provided with a load capacitor CLAnd an equivalent series resistance RESRA left half-plane zero is generated to enhance system stability.
The current self-adaptive bias circuit module 3 is used for changing the internal bias current of the linear voltage regulator according to the magnitude of the load current, and achieving the purpose of system stability by controlling the bias current.
Further, the nested inverted voltage follower circuit module 2 helps to increase the loop bandwidth of the linear regulator; the rest MOS tubes except the MP of the nested inverted voltage follower circuit module 2 work in a saturation region, so that the better performance is ensured.
Further, the current adaptive bias circuit module 3 comprises PMOS transistors MB1, MB3, NMOS transistor MB2 and a capacitor CB(ii) a The gate of the MB1 is connected to the gate of the M1 so that the gate dc potential of the M1 changes when the load current changes, thereby changing the current of the MB1 and thus the current flowing through the MB 2; since the MB2 is diode-connected, it can be used as a current mirror to provide gate voltage to the MB4, MB5, MB6 of other circuit modules.
Further, a diode in the current adaptive bias circuit module is connected with the MOS transistor MB3 and the MOS transistor CBA low-pass filter is formed to provide a stable and effective bias for the current mirror of other modules; since the MB1 and the M1 use the same gate connection, small signals in the circuit can flow through the MB1 and the MB2, so that other modules of the linear voltage regulator circuit form positive feedback to influence the stability of the system; and the MB3 and CBThe connections of (a) constitute a low-pass filter so that small signals cannot form excessive positive feedback interference.
Further, the current adaptive bias circuit module 3, the nested inverted voltage follower circuit module 2 and the differential operational amplifier 1 are connected in such a way that the quiescent current consumed by the linear regulator circuit changes under different load currents, so that the loop bandwidth of the linear regulator circuit also increases with the increase of the load current; since the loop bandwidth of the linear voltage regulator circuit is changed, the high power supply rejection ratio performance and the performance of quick transient response are realized.
In a specific implementation process, the embodiment of the invention provides a high power supply rejection ratio fast transient linear voltage regulator circuit, which comprises a differential operational amplifier 1, a nested inverted voltage follower circuit module 2 and a current self-adaptive bias circuit module 3; the differential operational amplifier circuit 1 is used for increasing the loop gain of the linear voltage regulator and improving the precision of output voltage; the nested inverted voltage follower circuit module 2 is used as an output stage of the linear voltage regulator and the nested structure is used for increasing the loop bandwidth of the linear voltage regulator; and the current self-adaptive bias circuit 3 is used for changing the internal bias current of the linear voltage regulator according to the load current. The embodiment of the invention has the advantages of fast transient response, high power supply rejection ratio, self-adaptive static power consumption, low load regulation rate, low linear regulation rate and the like, can provide a stable voltage source with high power supply rejection ratio for an integrated circuit, and improves the performance of the integrated chip.
Example 2
More specifically, on the basis of embodiment 1, the nested inverted voltage follower circuit module 2 has the gate of the PMOS transistor M11 as an input and the source as an output, and the output voltage V can be designed when a proper gate voltage of M11 is givenoutAnd the self-feedback loop of the nested inverted voltage follower circuit module is used as an internal voltage-stabilizing regulation loop of the output voltage.
The differential operational amplifier 1 is connected to the nested inverted voltage follower circuit module 2, in this embodiment, as shown in fig. 1 and fig. 2. The connection mode enables the differential operational amplifier 1 and the nested inverted voltage follower circuit module 2 to form an external regulation loop, and as a result, the linear regulation rate and the load regulation rate of the low dropout linear regulator are further improved.
The current self-adaptive bias circuit module 3 is formed by a node V of the nested inverted voltage follower circuit module 2FPhase connection control, node V when load current changesFThe DC potential of the capacitor is changed accordingly. Load current increase node VFThe dc potential of (b) decreases, thereby increasing the current through MB1, MB2, and vice versa. To prevent the input of loop small signals to the gates of MB4, MB5 and MB6 from causing the loop to constitute positive feedback or making the system unstable, diode-connected PMOS transistors MB3 and C are usedBThe low-pass filter is formed to enable the current self-adaptive bias circuit module to only provide direct current bias.
Referring to fig. 3, which is a simplified small-signal model of the high supply rejection ratio fast transient linear regulator circuit, a key model of the circuit and key parasitic capacitances are depicted.
The loop transfer function can be derived according to the small signal simplified model as follows:
Figure BDA0002887720170000061
the loop transfer function reveals the pole-zero distribution of the circuit, which is helpful for analyzing and designing and adjusting circuit parameters to achieve the optimal performance.
It should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.

Claims (10)

1.一种高电源抑制比快速瞬态的线性稳压器电路，其特征在于，包括差分运算放大器(1)、嵌套式倒置型电压跟随电路模块(2)和电流自适应偏置电路模块(3)；其中：1. A high power supply rejection ratio fast transient linear voltage regulator circuit, characterized in that it comprises a differential operational amplifier (1), a nested inverted voltage follower circuit module (2) and a current adaptive bias circuit module (3); of which: 所述差分运算放大器(1)与所述嵌套式倒置型电压跟随电路模块(2)电性连接；The differential operational amplifier (1) is electrically connected to the nested inverted voltage follower circuit module (2); 所述电流自适应偏置电路模块(3)与所述差分运算放大器(1)及所述嵌套式倒置型电压跟随电路模块(2)电性连接；The current adaptive bias circuit module (3) is electrically connected with the differential operational amplifier (1) and the nested inverted voltage follower circuit module (2); 所述差分运算放大器(1)用于增大线性稳压器环路增益提高输出电压的精度；The differential operational amplifier (1) is used to increase the loop gain of the linear regulator to improve the accuracy of the output voltage; 所述嵌套式倒置型电压跟随电路模块(2)用于作为线性稳压器的输出级，并提供带负载能力；并与所述的差分运算放大器(1)相连接；The nested inverted voltage follower circuit module (2) is used as an output stage of a linear voltage regulator and provides a load capacity; and is connected with the differential operational amplifier (1); 所述差分运算放大器(1)进一步改善线性稳压器性能。The differential operational amplifier (1) further improves the performance of the linear regulator. 2.根据权利要求1所述的一种高电源抑制比快速瞬态的线性稳压器电路，其特征在于，所述嵌套式倒置型电压跟随电路模块(2)包括输出级电压跟随电路和嵌套级电压跟随电路；其中：2. A high power supply rejection ratio fast transient linear regulator circuit according to claim 1, wherein the nested inverted voltage follower circuit module (2) comprises an output stage voltage follower circuit and Nested stage voltage follower circuit; where: 所述嵌套级电压跟随电路输入端与所述电流自适应偏置电路模块(3)电性连接；The input end of the nested stage voltage follower circuit is electrically connected to the current adaptive bias circuit module (3); 所述嵌套级电压跟随电路与所述输出级电压跟随电路电性连接，作为输出级电压跟随电路的内部环路的其中一部分；the nested stage voltage follower circuit is electrically connected to the output stage voltage follower circuit as a part of the inner loop of the output stage voltage follower circuit; 所述输出级电压跟随电路输出端与所述差分运算放大器(1)反相输入端电性连接，同时作为线性稳压器的输出端。The output terminal of the output stage voltage follower circuit is electrically connected to the inverting input terminal of the differential operational amplifier (1), and simultaneously serves as the output terminal of the linear regulator. 3.根据权利要求2所述的一种高电源抑制比快速瞬态的线性稳压器电路，其特征在于，所述输出级电压跟随电路和嵌套级电压跟随电路均为倒置型电压跟随电路，并通过嵌套形式构成所述嵌套式倒置型电压跟随电路模块(2)。3. The linear voltage regulator circuit of a high power supply rejection ratio fast transient according to claim 2, wherein the output stage voltage follower circuit and the nested stage voltage follower circuit are both inverted voltage follower circuits , and the nested inverted voltage follower circuit module (2) is formed in a nested form. 4.根据权利要求2所述的一种高电源抑制比快速瞬态的线性稳压器电路，其特征在于，所述嵌套级电压跟随电路包括PMOS管M2、M1和NMOS管MB4；所述输出级电压跟随电路包括PMOS管MP、M11和NMOS管MB5；其中：4. A high power supply rejection ratio fast transient linear regulator circuit according to claim 2, wherein the nested voltage follower circuit comprises PMOS transistors M2, M1 and NMOS transistor MB4; the The output stage voltage follower circuit includes PMOS transistors MP, M11 and NMOS transistors MB5; among them: 所述M2源极、MP源极与电源VDD电性连接；The M2 source electrode and the MP source electrode are electrically connected to the power supply V DD ; 所述M2栅极与所述M1漏极、MB4源极电性连接；the M2 gate is electrically connected to the M1 drain and the MB4 source; 所述M2漏极与所述M1源极、MP栅极电性连接；the M2 drain is electrically connected to the M1 source and the MP gate; 所述MP漏极与所述M11源极电性连接，此连接点作为线性稳压器输出端与所述差分运算放大器(1)反相输入端电性连接；The MP drain is electrically connected to the M11 source, and the connection point is used as the output terminal of the linear regulator and is electrically connected to the inverting input terminal of the differential operational amplifier (1); 所述M11栅极与所述差分运算放大器(1)输出端电性连接；The M11 gate is electrically connected to the output end of the differential operational amplifier (1); 所述M1栅极与所述电流自适应偏置电路模块(3)输入端、M11漏极、MB5源极电性连接；The M1 gate is electrically connected to the input end of the current adaptive bias circuit module (3), the M11 drain, and the MB5 source; 所述MB4栅极、MB5栅极与所述电流自适应偏置电路模块(3)输入端电性连接；同时，MB4栅极、MB5栅极与所述差分运算放大器(1)输入端电性连接；The gate of MB4 and gate of MB5 are electrically connected to the input terminal of the current adaptive bias circuit module (3); meanwhile, the gate of MB4 and the gate of MB5 are electrically connected to the input terminal of the differential operational amplifier (1). connect; 所述MB4漏极、MB5漏极接地。The drains of MB4 and MB5 are grounded. 5.根据权利要求4所述的一种高电源抑制比快速瞬态的线性稳压器电路，其特征在于，所述NMOS管MB4、NMOS管MB5以电流镜结构相连，由所述电流自适应偏置电路模块(3)提供偏置。5 . The linear regulator circuit with high power supply rejection ratio and fast transient according to claim 4 , wherein the NMOS transistor MB4 and NMOS transistor MB5 are connected by a current mirror structure, and are adapted by the current. 6 . A bias circuit module (3) provides bias. 6.根据权利要求1所述的一种高电源抑制比快速瞬态的线性稳压器电路，其特征在于，所述电流自适应偏置电路模块(3)包括PMOS管MB1、MB3和NMOS管MB2和电容CB；其中：6. The high power supply rejection ratio fast transient linear regulator circuit according to claim 1, wherein the current adaptive bias circuit module (3) comprises PMOS transistors MB1, MB3 and NMOS transistors MB2 and capacitor C B ; where: 所述MB1源极与电源VDD电性连接；The MB1 source is electrically connected to the power supply V DD ; 所述MB1栅极与所述嵌套式倒置型电压跟随电路模块(2)输入端电性连接；The MB1 gate is electrically connected to the input end of the nested inverted voltage follower circuit module (2); 所述MB1漏极与所述MB2源极、MB3栅极、MB3源极、MB2栅极电性连接；the MB1 drain is electrically connected to the MB2 source, the MB3 gate, the MB3 source, and the MB2 gate; 所述MB3漏极与所述差分运算放大器(1)输入端、所述电流自适应偏置电路模块(3)输入端电性连接；The MB3 drain is electrically connected to the input end of the differential operational amplifier (1) and the input end of the current adaptive bias circuit module (3); 所述电容CB一端与所述MB3漏极电性连接，另一端接地；One end of the capacitor C B is electrically connected to the drain of the MB3, and the other end is grounded; 所述MB2漏极接地。The MB2 drain is grounded. 7.根据权利要求5所述的一种高电源抑制比快速瞬态的线性稳压器电路，其特征在于，所述电流自适应偏置电路模块(3)包括PMOS管MB1、MB3和NMOS管MB2和电容CB；其中：7. A high power supply rejection ratio fast transient linear regulator circuit according to claim 5, wherein the current adaptive bias circuit module (3) comprises PMOS transistors MB1, MB3 and NMOS transistors MB2 and capacitor C B ; where: 所述MB1源极与电源VDD电性连接；The MB1 source is electrically connected to the power supply V DD ; 所述MB1栅极与所述M1栅极电性连接；the MB1 gate is electrically connected to the M1 gate; 所述MB1漏极与所述MB2源极、MB3栅极、MB3源极、MB2栅极电性连接；the MB1 drain is electrically connected to the MB2 source, the MB3 gate, the MB3 source, and the MB2 gate; 所述MB3漏极与所述差分运算放大器(1)输入端、所述MB4栅极、MB5栅极电性连接；The MB3 drain is electrically connected to the input end of the differential operational amplifier (1), the MB4 gate, and the MB5 gate; 所述电容CB一端与所述MB3漏极电性连接，另一端接地；One end of the capacitor C B is electrically connected to the drain of the MB3, and the other end is grounded; 所述MB2漏极接地。The MB2 drain is grounded. 8.根据权利要求6所述的一种高电源抑制比快速瞬态的线性稳压器电路，其特征在于，在所述电流自适应偏置电路模块(3)中，所述NMOS管MB2采用二极管连接方式；通过二极管连接PMOS管MB3与电容CB构成一个低通滤波器。8. A high power supply rejection ratio fast transient linear regulator circuit according to claim 6, characterized in that, in the current adaptive bias circuit module (3), the NMOS transistor MB2 adopts Diode connection mode; connect PMOS tube MB3 and capacitor CB through a diode to form a low-pass filter. 9.根据权利要求1-8任一项所述的一种高电源抑制比快速瞬态的线性稳压器电路，其特征在于，在所述嵌套式倒置型电压跟随电路模块(2)输出与所述差分运算放大器(1)输出之间跨接由电阻RC与电容CC的串联结构，以产生一个左半平面零点来增强电路的稳定性。9. A high power supply rejection ratio fast transient linear regulator circuit according to any one of claims 1-8, characterized in that, in the output of the nested inverted voltage follower circuit module (2) A series structure consisting of a resistor RC and a capacitor CC is connected across the output of the differential operational amplifier (1) to generate a left half-plane zero to enhance the stability of the circuit. 10.根据权利要求9所述的一种高电源抑制比快速瞬态的线性稳压器电路，其特征在于，在所述线性稳压器的输出级上跨接有负载电容CL以及等效电阻RESR的串联结构，以产生一个左半平面零点以电路系统稳定性。10. The linear regulator circuit with high power supply rejection ratio and fast transient according to claim 9, wherein a load capacitor CL and an equivalent are connected across the output stage of the linear regulator. The series structure of resistors R ESR to generate a left half plane zero for circuit system stability.
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