CN114035646A - Dynamic bias circuit of linear voltage stabilizer - Google Patents
Dynamic bias circuit of linear voltage stabilizer Download PDFInfo
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- 230000001052 transient effect Effects 0.000 abstract description 12
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
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Abstract
The invention relates to a dynamic bias circuit of a linear voltage regulator, belonging to the technical field of integrated circuits and linear voltage regulator design. The current reference circuit, the differentiator bias circuit, the differentiator and the linear voltage regulator bias circuit are included; the differentiator bias circuit is respectively connected with the current reference circuit and the differentiator; the differentiator is connected with a differentiator biasing circuit; the linear voltage regulator biasing circuit is connected with the differentiator. The output voltage of the linear voltage stabilizer is input into a differentiator; the differentiator differentiates the output voltage of the linear voltage stabilizer to obtain the change rate of the output voltage; and outputting the bias current of the linear voltage regulator by positive correlation with the output voltage change rate as a standard, and dynamically adjusting the bias circuit of the linear voltage regulator according to the bias current. The circuit can effectively increase the transient response performance of the LDO and realize self-adaptive power consumption adjustment.
Description
Technical Field
The invention relates to a dynamic bias circuit of a linear voltage regulator, belonging to the technical field of integrated circuits and linear voltage regulator design.
Background
In a System on Chip (SoC), a linear regulator is one of essential key components of all socs as a power supply of the SoC. With the development of integrated circuit technology in recent years, linear voltage regulators are also moving toward lower static power consumption, lower setup time, and no external capacitance. However, according to the design experience of the analog circuit, the static power consumption and the response speed are two mutually-constrained parameters, and the traditional method cannot optimize both the static power consumption and the response speed to the utmost extent. Considering that recent digital systems dynamically adjust clock frequency according to processing requirements to reduce power consumption, Low-Dropout linear regulators (LDO) also need to adaptively and dynamically adjust their power consumption.
There are two main types of methods for realizing low static power consumption and high response speed in the conventional LDO. One is output current sampling and the other is an auxiliary discharge loop for adjusting the grid of the tube. The output current sampling method generally obtains an output current value through a sampling resistor or by monitoring the grid voltage of an adjusting tube, and adds current into bias current according to a certain proportion to be used as compensation current. The characteristic of this mode is that the static current will change in proportion to the output current, which can greatly increase the transient response performance of the LDO. However, this method increases the quiescent current significantly at high output currents. The auxiliary discharge loop method for regulating tube grid is to add high speed low precision loop to the grid of regulating tube to raise transient response performance. However, this method has a higher complexity in circuit design due to the existence of multiple loops, and the auxiliary discharge loop also needs a quiescent current, which cannot be reduced to the maximum.
Disclosure of Invention
The invention aims to solve the technical defects that a low-power LDO (low dropout regulator) is difficult to realize extremely high transient response, loads in different working states cannot be realized, and self-adaptive static power consumption adjustment is realized, and provides a dynamic bias circuit of a linear voltage regulator.
In order to achieve the purpose, the invention adopts the following technical scheme:
the dynamic bias circuit of the linear voltage stabilizer comprises a current reference circuit, a differentiator bias circuit, a differentiator and a linear voltage stabilizer bias circuit;
under the 180nm analog circuit process, the whole area of the dynamic bias circuit is not more than 0.01 square millimeter, and the area is smaller;
the current reference circuit is used for generating a stable current reference;
the differentiator bias circuit is used for generating a bias voltage for the differentiator;
the differentiator is used for detecting the output voltage of the linear voltage stabilizer, sampling and carrying out differential calculation to generate a bias current reference of the linear voltage stabilizer;
the linear voltage regulator comprises a linear voltage regulator bias circuit, a load clock frequency self-adaptive equalizer and a differential device, wherein the linear voltage regulator bias circuit is a dynamic bias circuit for output level sampling, the bias circuit can self-adaptively level and smooth an average bias current according to the load clock frequency, and is used for generating a bias voltage for the linear voltage regulator by taking the bias current generated by the differential device as a reference;
the connection relation of each module in the linear voltage stabilizer is as follows:
the current reference circuit is connected with the differentiator bias circuit; the differentiator bias circuit is respectively connected with the current reference circuit and the differentiator and generates bias voltage for the differentiator; the differentiator is respectively connected with the differentiator bias circuit and the linear voltage regulator bias circuit; the linear voltage stabilizer biasing circuit is connected with the differentiator;
the working process of the linear voltage regulator, namely the dynamic bias adjustment process, specifically comprises the following steps:
a dynamic bias circuit formed by a differentiator is added, so that the bias current can be rapidly adjusted according to the output voltage of the linear voltage stabilizer;
and 3, adjusting the bias voltage output by the bias circuit of the linear voltage regulator according to the bias current obtained in the step 2.
Advantageous effects
Compared with the existing linear voltage stabilizer, the dynamic bias circuit of the linear voltage stabilizer has the following beneficial effects:
1. the dynamic bias circuit in the linear voltage regulator adopts the differentiator to sample the output voltage of the linear voltage regulator, can rapidly adjust the bias current according to the output voltage of the linear voltage regulator, greatly improves the transient response performance of the linear voltage regulator under the condition of low power consumption, is suitable for a circuit with high requirements on low power consumption and transient response, and can effectively increase the transient response performance of the LDO without increasing static power consumption;
2. the differentiator in the linear voltage stabilizer can automatically adjust the bias current according to the differentiation result of the output voltage, namely the voltage change rate, namely, the quiescent current can be automatically adjusted according to the load clock frequency, so that the linear voltage stabilizer has a simple structure, can be realized without digital control or resistance, and has small area and low cost;
3. the linear voltage regulator utilizes a dynamic bias circuit sampled by an output stage, can adaptively level and level the uniform bias current according to the frequency of a load clock, realizes adaptive power consumption adjustment, and is suitable for occasions where the load needs to frequently adjust the working state.
Drawings
FIG. 1 is a flow chart of a dynamic adjustment process of a dynamic bias circuit of the linear regulator according to the present invention;
FIG. 2 is a block diagram of a dynamic bias circuit of the linear regulator provided by the present invention;
FIG. 3 is a circuit schematic diagram of an embodiment of a dynamic bias circuit of the linear regulator provided by the present invention;
FIG. 4 is a graph of bias voltage versus current for a dynamic bias circuit of a linear regulator according to the present invention when a positive voltage pulse is input;
FIG. 5 is a graph of bias voltage versus current for a dynamic bias circuit of a linear regulator according to the present invention when a negative voltage pulse is input;
fig. 6 is a bias current curve of the dynamic bias circuit of the linear regulator provided by the present invention under different load frequencies.
Fig. 7 is a block diagram of a dynamic bias circuit of a linear regulator according to the present invention in a digital circuit configuration.
Detailed Description
The circuit modules and the operation of the dynamic bias circuit of the linear regulator according to the present invention will be further explained and described in detail with reference to the embodiments and the accompanying drawings.
Example 1
Compared with the biasing structure of the existing voltage stabilizer, the dynamic biasing circuit of the linear voltage stabilizer can realize low power consumption, ultrahigh transient response and self-adaptive bias adjustment. Fig. 1 is a flow chart of the operation process of the dynamic bias circuit of the linear regulator according to the present invention, and the adjustment process is as follows:
And 2, performing differential calculation on the output voltage obtained in the step 1 to obtain the change rate of the output voltage.
And 3, finally, adjusting the bias of the linear voltage regulator by taking the output voltage change rate obtained in the step 2 as a standard to realize dynamic bias.
Fig. 2 is a block diagram of a dynamic bias circuit of the linear regulator according to the present invention. The system is used for monitoring the output voltage of the LDO and dynamically adjusting the bias current according to the output voltage. Comprises a current reference circuit 101, a differentiator bias circuit 102, a differentiator circuit 103 and a linear regulator bias circuit 104;
the current reference circuit 101 is used for generating a stable current reference, and is implemented by using a PTAT current source;
the differentiator bias circuit 102 is used for generating a bias voltage for the differentiator circuit 103, and is realized by using a bias MOS (metal oxide semiconductor) tube and a current mirror;
the differentiator circuit 103 is used for detecting the output voltage of the linear voltage regulator and performing differentiation calculation to generate a bias current reference of the linear voltage regulator, and is realized by using an analog differentiator formed by a capacitor and a current buffer;
the linear regulator biasing circuit 104 is used for generating a bias voltage for the linear regulator by taking a bias current generated by the differentiator circuit 103 as a reference, and is realized by using a bias MOS (metal oxide semiconductor) tube and a current mirror;
the connection relation of each module in the dynamic bias circuit of the linear voltage stabilizer is as follows:
a current reference circuit 101 connected to a differentiator bias circuit 102;
a differentiator bias circuit 102 connected to the current reference circuit 101 and the differentiator circuit 103, respectively, for generating a bias voltage for the differentiator circuit 103;
a differentiator circuit 103 connected to the differentiator bias circuit 102 and the linear regulator bias circuit 104, respectively;
the linear regulator bias circuit 104 is connected to the differentiator circuit 103.
Fig. 3 is a circuit schematic diagram of a dynamic bias embodiment of the linear regulator provided by the present invention. The structure illustrated in connection with fig. 2, comprising:
the six MOS tubes M1, M2, M3, M4, M5 and M6 form a current reference circuit 101; six MOS tubes M7, M8, M9, M10, M11 and M12 form a differentiator bias circuit 102; eight MOS tubes: a first bias tube M13, a second bias tube M14, a third bias tube M15, a fourth bias tube M16, a first amplification tube M17, a second amplification tube M18, a fifth bias tube M19, a sixth bias tube M20, and two capacitors: the first differential capacitor C1 and the second differential capacitor C2 constitute a differentiator circuit 103; the six MOS tubes M21, M22, M23, M24, M25 and M26 form a linear regulator bias circuit 104.
One end of the differentiator circuit 103, the first differentiating capacitor C1 and one end of the second differentiating capacitor C2 are connected with the LDO output voltage;
the grid electrode of the first amplifying tube M17 is connected with the drain electrode of the first biasing tube M13, the source electrode of the second biasing tube M14 and the first differential capacitor C1, the source electrode is connected with a power supply, and the drain electrode is connected with a current output end;
the grid electrode of the second amplifying tube M18 is connected with the drain electrode of the third biasing tube M15, the source electrode of the fourth biasing tube M16 and the second differential capacitor C2, the source electrode is connected with a power supply, and the drain electrode is connected with a current mirror formed by the fifth biasing tube M19 and the sixth biasing tube M20;
the fifth bias tube M19 and the sixth bias tube M20 form an equal proportion current mirror, the drain electrode of the sixth bias tube M20 is connected with the current output end, and the current output end is added with the output current of the first amplifying tube M17 and then output.
Specifically, in this embodiment, the bias circuit of the conventional linear regulator is replaced with the dynamic bias circuit of this embodiment for testing.
FIG. 4 is a graph of bias voltage versus current for the dynamic bias circuit of the linear regulator according to the present invention when a positive voltage pulse is input, and FIG. 5 is a graph of bias voltage versus current for the dynamic bias circuit of the linear regulator according to the present invention when a negative voltage pulse is input; the method comprises the following steps: the first bias voltage is the voltage of a grid electrode node of the first amplifying tube; the second bias voltage is the voltage of a grid electrode node of the second amplifying tube; the first bias current is the drain current of the first amplifier tube; the second bias current is the drain current of the second amplifier tube; the total bias current is the output bias current. The curve in the figure shows that the bias changes along with the output voltage of the linear voltage regulator, the total bias current is 1.27nA under the static condition, when the output voltage of the linear voltage regulator generates transient change, the peak value of the total bias current can reach 20uA to 30uA, the dynamic adjustment function of the bias current is realized, the integral transient stability time of the linear voltage regulator is reduced to about 20nS, and high transient response and ultra-low power consumption are realized.
Fig. 6 is a bias current curve of the dynamic bias circuit of the linear regulator provided by the present invention under different load frequencies, and shows the change of the bias with the load frequency, it can be seen that when the load frequency is close to 0, the average bias current is only 3nA, the bias current rises rapidly with the rise of the load frequency, and when the load frequency is 1MHz, the average bias current reaches about 2500nA, so that the function of self-adaptive bias current adjustment is realized.
The present embodiment is designed for on-chip LDOs for applications with high requirements on power consumption, transient response, cost, and space, such as battery applications, e.g., embedded applications, and sensors using batteries. The linear regulator circuit is realized by using 180nM analog CMOS technology, and the whole area of the linear regulator circuit is 0.021 square millimeter, wherein the partial area of the dynamic bias circuit is only 0.005 square millimeter.
Example 2
The dynamic bias circuit of the linear voltage regulator can also be used as a bias circuit of an independent linear voltage regulator chip. In an independent chip design, the dynamic bias circuit of the linear regulator disclosed by the application is the same as that of the embodiment 1:
comprises a current reference circuit 101, a differentiator bias circuit 102, a differentiator circuit 103 and a linear regulator bias circuit 104;
the current reference circuit 101 is used for generating a stable current reference, and is implemented by using a band-gap current source to ensure the performance under the full-temperature condition;
the differentiator bias circuit 102 is used for generating a bias voltage for the differentiator circuit 103, and is realized by using a bias MOS (metal oxide semiconductor) tube and a current mirror;
the differentiator circuit 103 is used for detecting the output voltage of the linear voltage regulator and performing differentiation calculation to generate a bias current reference of the linear voltage regulator, and is realized by using an analog differentiator formed by a capacitor and a current buffer;
the linear regulator biasing circuit 104 is used for generating a bias voltage for the linear regulator by taking a bias current generated by the differentiator circuit 103 as a reference, and is realized by using a bias MOS (metal oxide semiconductor) tube and a current mirror;
the connection relationship among the modules in this embodiment is the same as that in embodiment 1;
considering that the chip area limitation is lower in the independent chip design, the area occupied by the capacitor in the differentiator of the dynamic bias circuit can be increased to improve the performance.
Example 3
The dynamic bias circuit of the linear voltage regulator described herein may also be constructed as a digital circuit to accomplish the same function. In the design of the digital dynamic bias structure, as shown in fig. 7, the structure diagram of the dynamic bias circuit of the linear regulator provided by the invention under the digital circuit structure is as follows:
the device comprises a clock source, an analog-to-digital converter, a digital differentiator, a bias current switch network and a linear voltage stabilizer bias circuit;
the clock source is used for generating a stable clock signal and is used for providing the stable clock signal for the analog-to-digital converter and the digital differentiator;
the analog-to-digital converter is used for sampling the output voltage of the linear voltage stabilizer and converting the output voltage into a digital signal for a subsequent processing circuit.
The digital differentiator is used for carrying out differential calculation according to a voltage signal output by the analog-to-digital converter to generate a control signal of the bias switch current network;
the bias current switch network is used for adjusting bias current according to a control signal given by the digital differentiator and consists of a plurality of current sources and switches;
the linear voltage stabilizer biasing circuit is used for generating a bias voltage for the linear voltage stabilizer by taking a bias current generated by the bias current switching network as a reference, and is realized by using a bias MOS (metal oxide semiconductor) tube and a current mirror;
the connection relation of each module in the dynamic bias circuit of the linear voltage stabilizer is as follows:
the clock source is respectively connected with the analog-to-digital converter and the digital differentiator;
the analog-to-digital converter is respectively connected with the clock source and the digital differentiator and is responsible for sampling the output voltage of the linear voltage stabilizer and providing the output voltage to the digital differentiator;
the digital differentiator is respectively connected with the analog-to-digital converter, the clock source and the bias current switch network, and is responsible for carrying out differential calculation on a voltage signal provided by the analog-to-digital converter and generating a current switch network control signal;
the bias current switch network is connected with the digital differentiator and the linear voltage stabilizer bias circuit and outputs bias current under the control of the digital differentiator;
and the linear voltage stabilizer biasing circuit is connected with the biasing current switch network.
Compared with the analog dynamic bias circuit in embodiment 1, the digital dynamic bias circuit provided in this embodiment has stronger digital circuit compatibility and is easier to manufacture in a digital process. Since there is no differential capacitance, the area is small, about 0.005 square millimeters. The response speed and the power consumption of the circuit depend on the clock frequency, and compared with the analog dynamic bias circuit in the embodiment 1, the circuit has lower corresponding speed and higher power consumption; but is composed primarily of digital circuitry so that its performance can be easily programmed. The digital dynamic bias circuit provided by the embodiment is suitable for LDOs with custom and controllable requirements under the digital integrated circuit technology.
The invention has been described in detail above with reference to three specific embodiments. While the preferred embodiments of the invention have been described, the invention should not be limited to the embodiments and drawings disclosed. Equivalents and modifications may be made without departing from the spirit of the disclosure, which is to be considered as within the scope of the invention.
Claims (9)
1. A linear voltage regulator based on a dynamic bias structure, characterized in that: the current reference circuit (101), the differentiator bias circuit (102), the differentiator (103) and the linear regulator bias circuit (104) are included;
the connection relation of each module in the linear voltage stabilizer is as follows:
the current reference circuit (101) is connected with the differentiator bias circuit (102); the differentiator bias circuit (102) is respectively connected with the current reference circuit (101) and the differentiator (103) and generates a bias voltage for the differentiator (103); the differentiator (103) is respectively connected with the differentiator bias circuit (102) and the linear regulator bias circuit (104); the linear voltage regulator biasing circuit (104) is connected with the differentiator (103);
the working process of the linear voltage regulator, namely the dynamic bias adjustment process, specifically comprises the following steps:
step 1, a differentiator bias circuit (102) provides bias voltage for a differentiator (103), and a current reference circuit (101) provides reference current for the differentiator bias circuit (102);
step 2, detecting the output voltage of the linear voltage stabilizer by a differentiator (103) and carrying out differential calculation to generate bias current of the linear voltage stabilizer;
and 3, adjusting the bias voltage output by the bias circuit of the linear voltage regulator according to the bias current obtained in the step 2.
2. The linear regulator according to claim 1, wherein: under the 180nm analog circuit process, the whole area of the dynamic bias circuit does not exceed 0.01 square millimeter.
3. The linear regulator according to claim 1, wherein: the linear regulator bias current is determined by the output voltage rate of change.
4. The linear regulator according to claim 1, wherein: the current reference circuit (101) is used for generating a reference current.
5. The linear regulator according to claim 1, wherein: the differentiator bias circuit (102) is configured to generate a bias voltage for the differentiator (103).
6. The linear regulator according to claim 1, wherein: the differentiator (103) is used for detecting the output voltage of the linear voltage stabilizer, sampling and carrying out differentiation calculation, and generating the bias current reference of the linear voltage stabilizer.
7. The linear regulator according to claim 1, wherein: the linear regulator biasing circuit (104) is a dynamic biasing circuit for sampling an output stage.
8. The linear regulator according to claim 7, wherein: a dynamic bias circuit of a linear regulator bias circuit (104) is capable of adaptively leveling an average bias current according to a load clock frequency for generating a bias voltage for the linear regulator with reference to the bias current generated by a differentiator.
9. The linear regulator according to claim 1, wherein: step 2 in the working process of the linear voltage stabilizer is to add a dynamic bias circuit formed by a differentiator, so that the bias current can be rapidly adjusted according to the output voltage of the linear voltage stabilizer.
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