CN104950976B - Voltage stabilizing circuit based on slew rate increasing - Google Patents
Voltage stabilizing circuit based on slew rate increasing Download PDFInfo
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- CN104950976B CN104950976B CN201510256206.5A CN201510256206A CN104950976B CN 104950976 B CN104950976 B CN 104950976B CN 201510256206 A CN201510256206 A CN 201510256206A CN 104950976 B CN104950976 B CN 104950976B
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Abstract
The invention discloses a voltage stabilizing circuit based on slew rate increasing. A capacitor device is utilized for directly connecting output voltage VOUT to an M4 transistor grid electrode, and zero-delay loop response is achieved. Quiescent voltage bias is provided for the M4 transistor grid electrode by means of M3, R1 and IB, quiescent voltage bias is provided with for an M4 transistor source electrode by means of a Native NMOS transistor, M2 and C2, it is ensured that the circuit achieves zero-delay loop response, and meanwhile the voltage stabilizing circuit has the advantages of being high in supply voltage rejection ratio, applicable to lower input voltage application environment and the like.
Description
Technical field
It is more particularly to a kind of to be based on the enhanced mu balanced circuit of Slew Rate the present invention relates to hardware design field.
Background technology
In low-power consumption OCL output capacitance-less low pressure difference linear voltage regulator（Capless Low Dropout Regulator,
Capless LDO）In system, typically there is a slew rate enhancing circuit（Slew Rate Enhancement Circuits,
SRE）, rung for strengthening the charging and discharging currents to LDO power tubes grid level when necessary, and then improving the transient state of LDO output voltages
Answer characteristic.
Fig. 1 gives the general modfel of the circuit block diagram of Capless LDO.The circuit block diagram chief component has：Work(
Rate metal-oxide-semiconductor MPOW, the feedback resistive network, error amplifier, load impedance RL and CL and the Slew Rate that are made up of RFB1 and RFB2
Enhancing circuit SRE.When the load current of LDO is undergone mutation or power tube output current is undergone mutation, LDO is caused to export electricity
The big ups and downs of pressure, so that the feedback voltage V FB also big ups and downs therewith produced via feedback resistive network.When VFB's
After magnitude of voltage exceedes the input voltage range of error amplifier, error amplifier enters saturation state, when error amplifier saturation
Afterwards, it can carry out discharge and recharge according to the Slew Rate of itself to the gate capacitance of power tube.Error amplifier is low work(in many applications
The design structure of consumption, the Slew Rate of its output is very small, fails to meet the demand of the big signal response speed of loop.SRE circuits can be with
By detecting the fluctuation of output voltage Vout, according to the charge or discharge correspondingly extra to MPOW pipes grid level supplement of fluctuation situation
Electric current, plays quickening loop response speed, reduces the effect of output voltage fluctuating range.
Slew rate enhancing circuit can be divided into from structure：Slew rate enhancing circuit with comparator as core, with differentiator as core
The slew rate enhancing circuit of the heart, zero propagation slew rate enhancing circuit.Slew rate enhancing circuit wherein with comparator as core with differential
All there is different degrees of operating lag in device, can not be rung at once after LDO loads occur saltus step for the slew rate enhancing circuit of core
Should.Existing zero propagation slew rate enhancing circuit can reach the characteristic of zero propagation, but there are some defects and use limitation, such as：
Be not suitable for high power supply voltage LDO circuit, need extra linear voltage regulator and extra feedback resistive network etc..
The content of the invention
Based on above-mentioned situation, the present invention provides a kind of based on the enhanced mu balanced circuit of Slew Rate, it is therefore an objective to so that Capless
The features such as LDO circuit possesses big signal response speed, low-power consumption, the high power supply voltage rejection ratio of zero-lag, while avoiding existing
There is zero-lag slew rate enhancing circuit to be not suitable for high power supply voltage LDO circuit, need extra linear voltage regulator and independent anti-
The shortcomings of feed resistance.
One kind is based on the enhanced mu balanced circuit of Slew Rate, by Native NMOS tubes M1, M2, PMOS M3, M4, operation amplifier
Device EA, resistance R1, R2, R3, electric capacity C1, C2 and current source IB are constituted, the drain electrode connection power port of Native NMOS tubes M1
The drain electrode of VDD and Native NMOS tubes M2, Native NMOS tube M1 source electrodes connection output port VOUT, the C12 of electric capacity C1
End and the R21 ends of resistance R2, output end ea_o, the PMOS of the grid concatenation operation amplifier EA of Native NMOS tubes M1
The drain electrode of M4；The R22 ends of resistance R2 connect the R31 ends of resistance R3 and the reverse input end of operational amplifier EA；Resistance R3's
R32 ends connection GND ports, the C22 ends of C2 and the negative terminal of IB；The positive input connection voltage input end of operational amplifier EA
Mouth VREF；The grid connection bias voltage input mouthful VB1 of Native NMOS tubes M2, Native NMOS tube M2 pipes source electrode connects
Connect the C21 ends of the source electrode, PMOS M4 pipes source electrode and electric capacity C2 of PMOS M3 pipes；The grid connection PMOS of PMOS M3 pipes
The drain electrode of M3 pipes, the R11 ends of R1, the anode of IB；M4 tube grids connect C11 ends, the R12 ends of R1 of C1.
Above-mentioned electric capacity C2 can also be substituted using open circuit.
Relative to a kind of voltage-stablizer based on slew rate enhancing circuit that prior art, the present invention are provided,
First, the circuit output stage using Native NMOS as power output metal-oxide-semiconductor, than existing scheme commonly use
PMOS, the advantage is that can obtain supply-voltage rejection ratio higher, this in OCL output capacitance-less type LDO particularly weigh
Will.
2nd, the circuit using zero-lag slew rate enhancing circuit, its big signal response speed better than based on comparator with it is micro-
Divide the existing slew rate enhancing circuit of device, greatly optimize the output transient response without capacitor type LDO.
3rd, VOUT and M4 grid level are coupled using electric capacity C1 directly in the program, it is to avoid existing zero-lag Slew Rate strengthens
Circuit is not suitable for the shortcoming of high power supply voltage LDO circuit, and does not need extra linear voltage regulator and independent feedback electricity
Resistance network, simplifies circuit, saves area.
4th, VB1, C2 and Native NMOS M2 are used to produce voltage bias for the source class of M3 and M4, it is ensured that should
Circuit has compared with high power supply voltage rejection ratio, and the characteristics of suitable for low supply voltage.
Brief description of the drawings
Fig. 1 is the structural representation of existing low-power consumption OCL output capacitance-less low pressure difference linear voltage regulator；
Fig. 2 is a kind of stabilizator structure schematic diagram based on slew rate enhancing circuit of the invention；
Fig. 3 is another embodiment of the present invention.
Specific embodiment
The present invention program is described in detail below in conjunction with better embodiment therein.The present invention is to utilize capacitor
Output voltage VO UT is directly connected to M4 pipes grid level by part, realizes the loop response of zero-lag.Simultaneously using M3, R1, IB to M4
Pipe grid level provides quiescent voltage biasing, and providing quiescent voltage to M4 tube source grades using Native NMOS tube M2 and C2 biases,
While ensureing the circuit realiration zero-lag loop response, with high power supply voltage rejection ratio, suitable for low input application
The advantages of environment.Output stage using Native NMOS as power output metal-oxide-semiconductor, than the PMOS that commonly uses of existing scheme
Pipe, the advantage is that can obtain supply-voltage rejection ratio higher.
A kind of stabilizator structure schematic diagram based on slew rate enhancing circuit is shown in Fig. 2.
Circuit structure of the present invention includes：Native NMOS tubes M1, M2, PMOS M3, M4, operational amplifier EA, resistance
R1, R2, R3, electric capacity C1, C2, current source IB；The drain electrode of M1 drain electrode connection power ports VDD and M2, the connection output of M1 source electrodes
The C12 ends of port VOUT, C1 and the R21 ends of R2, the leakage of output end ea_o, M4 of the grid concatenation operation amplifier EA of M1
Pole；The R22 ends of R2 connect R31 ends, the reverse input end of EA of R3；The R32 ends connection GND ports of R3, the C22 ends of C2, IB
Negative terminal；The positive input connection control source port VREF of operational amplifier EA；The grid connection bias voltage input of M2
Mouth VB1, M2 pipes source electrode connection M3 pipes source electrode, M4 pipes source electrode, the C21 ends of C2；The grid connection drain electrode of M3 pipes of M3 pipes, R1
R11 ends, the anode of IB；M4 tube grids connect C11 ends, the R12 ends of R1 of C1.
In this embodiment, whole circuit increases electric capacity C2, and the voltage of M4 source nodes can be made more steady, and then works as
When the voltage of VOUT ports occurs overshoot change downwards because load current is mutated, M4 grid step voltage is downward by c11 couplings
Change, the source class of M4 pipes is more stablized due to the effect of c2, and at this moment M4 drain terminals can export bigger compensation electric current, reduces VOUT
The downward overshoot amplitude of output voltage.
In actual applications, the C2 in above-described embodiment can be substituted directly with path, if as shown in figure 3, without C2,
M4 can equally export compensation electric current under some circumstances.
In the present embodiment, M1, R2, R3, EA constitute the conventional control loop of the LDO, M1 for power output device, R2,
R3 constitutes feedback resistive network.EA is error amplifier, M2, M3, M4, C1, C2, R1, IB composition slew rate enhancing circuit.
VOUT is output voltage port, and VREF is the input port of bandgap voltage reference, and VB1 is a bias voltage.
M1, M2 type of device are also referred to as " intrinsic NMOS tube " for Native NMOS, Native NMOS tubes, are a kind of direct
NMOS tube in manufacture and wafer Psub, it is that its threshold voltage is lower with the difference of common NMOS tube, is usually closer to 0V,
It is especially suitable for low voltage circuit structure.
When system is in stable state, slew rate enhancing circuit does not influence conventional control loop circuit, and VB1, M2, M3, IB are common
For M4 provides suitable static bias voltage, by the drain terminal current offset of M4 under a relatively small static working current.
VOUT output voltages and M4 gate voltages all keep static.
When in the load current short time of LDO from underloading saltus step for heavy duty, because VOUT node parasitic capacitances are smaller, and
The conventional control loop response speed of the circuit is slow, and downward voltage pulsation occur in VOUT voltages.Due to C1 coupled capacitors
Effect, and the resistance of R1 is relatively large, and M4 gate voltages produce almost zero-lag with the voltage pulsation of amplitude.Due to VB1, M2,
The effect of C2, M4 pipes source voltage terminal preserves relative constancy.The drain terminal of M4 produces the current increment of zero-lag since so, increases stream
To the electric current of M1 grids.There is the moment of fluctuation downwards, zero-lag ground supplement M1 pipes grid level electric charge, M1 grids electricity in VOUT voltages
Pressure rises, and then improves M1 pipes drain electrode output current, plays a part of the big signal response of zero-lag, farthest reduces
The voltage undershoot amplitude that VOUT voltages are produced because load current changes.
Example described above only expresses embodiments of the present invention, and its description is more specific and in detail, but can not be because
This and be interpreted as the limitation to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art,
On the premise of not departing from present inventive concept, various modifications and improvements can be made, these belong to protection scope of the present invention.
Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (2)
1. it is a kind of to be based on the enhanced mu balanced circuit of Slew Rate, by Native NMOS tube M1 and M2, PMOS M3 and M4, operation amplifier
Device EA, resistance R1, R2 and R3, electric capacity C1 and C2, and current source IB compositions, it is characterised in that the leakage of Native NMOS tubes M1
Pole connects the drain electrode of power port VDD and Native NMOS tube M2, Native NMOS tube M1 source electrodes connection output port
One end of VOUT, one end of electric capacity C1 and resistance R2, the output of the grid concatenation operation amplifier EA of Native NMOS tubes M1
Hold the drain electrode of ea_o and PMOS M4；One end of the other end connection resistance R3 of resistance R2 and operational amplifier EA's is reverse
Input；The negative terminal of the other end connection GND ports, one end of electric capacity C2 and current source IB of resistance R3；Operational amplifier EA
Positive input connection control source port VREF；The grid connection bias voltage input mouthful of Native NMOS tubes M2
VB1, Native NMOS tube M2 pipes source electrode connect the another of source electrode, PMOS M4 pipes source electrode and the electric capacity C2 of PMOS M3 pipes
End；The anode of the drain electrode, one end of resistance R1 and current source IB of the grid connection PMOS M3 pipes of PMOS M3 pipes；M4 is managed
The other end of grid connection electric capacity C1 and the other end of resistance R1.
2. mu balanced circuit according to claim 1, it is characterised in that the electric capacity C2 is open circuit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510256206.5A CN104950976B (en) | 2015-05-20 | 2015-05-20 | Voltage stabilizing circuit based on slew rate increasing |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510256206.5A CN104950976B (en) | 2015-05-20 | 2015-05-20 | Voltage stabilizing circuit based on slew rate increasing |
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| CN104950976A CN104950976A (en) | 2015-09-30 |
| CN104950976B true CN104950976B (en) | 2017-05-17 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106484020A (en) * | 2016-12-06 | 2017-03-08 | 珠海全志科技股份有限公司 | Low-dropout linear voltage-regulating circuit |
| EP3379369B1 (en) * | 2017-03-23 | 2021-05-26 | ams AG | Low-dropout regulator having reduced regulated output voltage spikes |
| CN106886243B (en) * | 2017-05-05 | 2018-03-06 | 电子科技大学 | A kind of low pressure difference linear voltage regulator with fast response characteristic |
| CN107291144B (en) * | 2017-05-23 | 2019-02-12 | 上海集成电路研发中心有限公司 | It is a kind of with transient state enhancing structure unit without capacitor LDO circuit outside piece |
| CN116166083B (en) * | 2023-04-23 | 2023-07-21 | 盈力半导体(上海)有限公司 | Low dropout linear voltage stabilizing circuit and buck circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7323853B2 (en) * | 2005-03-01 | 2008-01-29 | 02Micro International Ltd. | Low drop-out voltage regulator with common-mode feedback |
| EP2120123A1 (en) * | 2008-05-12 | 2009-11-18 | Stmicroelectronics SA | Slew rate control |
| CN102331807B (en) * | 2011-09-30 | 2013-06-12 | 电子科技大学 | Low-dropout (LDO) linear regulator of integrated slew rate enhancing circuit |
| CN102609025B (en) * | 2012-03-16 | 2013-12-11 | 电子科技大学 | Dynamic current doubling circuit and linear voltage regulator integrated with the circuit |
| US9256233B2 (en) * | 2013-06-12 | 2016-02-09 | Stmicroelectronics International N.V. | Generating a root of an open-loop freqency response that tracks an opposite root of the frequency response |
| CN104536506B (en) * | 2015-01-05 | 2016-06-01 | 武汉新芯集成电路制造有限公司 | Linear voltage regulator |
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Address after: 510530 Room 301 and 401, Building 42, Dongzhong Road, East District, Guangzhou Economic and Technological Development Zone, Guangdong Province Patentee after: TECHTOTOP MICROELECTRONICS Co.,Ltd. Address before: Two road 523808 in Guangdong province Dongguan City Songshan Lake high tech Industrial Development Zone headquarters No. 17 room A410-A411 Patentee before: TECHTOTOP MICROELECTRONICS Co.,Ltd. |
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Denomination of invention: Voltage stabilizing circuit based on slew rate increasing Effective date of registration: 20200331 Granted publication date: 20170517 Pledgee: China Co. truction Bank Corp Guangzhou Tianhe subbranch Pledgor: TECHTOTOP MICROELECTRONICS Co.,Ltd. Registration number: Y2020440000058 |
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Granted publication date: 20170517 Pledgee: China Co. truction Bank Corp Guangzhou Tianhe subbranch Pledgor: TECHTOTOP MICROELECTRONICS Co.,Ltd. Registration number: Y2020440000058 |