CN109164861A - A kind of low pressure difference linear voltage regulator of fast transient response - Google Patents
A kind of low pressure difference linear voltage regulator of fast transient response Download PDFInfo
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- CN109164861A CN109164861A CN201811291003.XA CN201811291003A CN109164861A CN 109164861 A CN109164861 A CN 109164861A CN 201811291003 A CN201811291003 A CN 201811291003A CN 109164861 A CN109164861 A CN 109164861A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/461—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using an operational amplifier as final control device
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
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Abstract
The invention belongs to IC design fields, in particular to a kind of low pressure difference linear voltage regulator of fast transient response, including reference voltage source, error amplifier, the resistance-feedback network of series connection adjustment pipe MNO and first resistor R1 and second resistance R2 composition, it further include the buffer being connected between error amplifier output and adjustment pipe MNO grid end of connecting, the load transient response enhancing circuit being connected between series connection adjustment pipe MNO grid end and source, the Adaptive Compensation Control circuit being connected between error amplifier and load transient response enhancing circuit, and provide the biasing circuit of operating current.Adaptive antenna zero compensates the loop stability for improving voltage-stablizer, NMOS series connection adjustment pipe and load transient response enhancing circuit enhance the load transient response of voltage-stablizer, outside no piece in the case where capacitor, unobvious increase quiescent dissipation, present invention obtains the promotions of low pressure difference linear voltage regulator load transient response performance.
Description
Technical field
The invention belongs to IC design field, in particular to the low pressure difference linearity pressure stabilizing of a kind of fast transient response
Device.
Background technique
Low pressure difference linear voltage regulator (LDO) because its structure is simple, low-power consumption, output ripple is small, peripheral cell is few the features such as,
It has a wide range of applications in SoC design, powers for different functional modules.As shown in Figure 1, typical low pressure difference linearity pressure stabilizing
The resistance-feedback network structure that device is generally made of reference voltage circuit, error amplifier, series connection adjustment pipe MP0 and resistance R1, R2
At, wherein CLIt is output load capacitance, ILIt is output load current.
With the progress of semiconductor fabrication process, the supply voltage of digital integrated electronic circuit is constantly reduced, to what is powered for it
The requirement of LDO load transient response correspondinglys increase.Circuit level is continuously improved simultaneously, and power consumption increases, and is further degrading LDO
Load transient response.Traditional LDO structure is difficult to meet design requirement, especially without the LDO of external capacitor, with greater need for raising
The technology of LDO load transient response.
So how to design a kind of low pressure difference linear voltage regulator of fast transient response, become what we currently to be solved
Problem.
Summary of the invention
For this purpose, the invention proposes a kind of low pressure difference linear voltage regulator of fast transient response, to solve the above problems.
To achieve the above object, the invention provides the following technical scheme: a kind of low pressure difference linearity of fast transient response is steady
Depressor is formed including reference voltage source, error amplifier, series connection adjustment pipe MNO and first resistor R1 and second resistance R2
Resistance-feedback network further includes the buffer being connected between the error amplifier output and adjustment pipe MNO grid end of connecting,
The load transient response enhancing circuit being connected between the series connection adjustment pipe MNO grid end and source, is connected to the error and puts
Adaptive Compensation Control circuit between big device and load transient response enhancing circuit, and the biased electrical of operating current is provided
Road.
Preferably, the biasing circuit includes current source IB, NMOS tube MN1, NMOS tube MN2 and PMOS tube MP0, it is described
Current source IBOne end connect power supply, the other end connects the NMOS tube MN1 drain terminal, the NMOS tube MN1 source ground connection,
Grid end is connected with drain terminal, and the NMOS tube MN2 grid end is connect with the NMOS tube MN1 grid end, source ground connection, drain terminal with it is described
The connection of PMOS tube MP0 drain terminal, the source PMOS tube MP0 termination power, grid end are connected with drain terminal.
Preferably, the non-inverting input terminal of the error amplifier connects reference voltage source, inverting input terminal connection first
The drain terminal at the common end of resistance R1 and second resistance R2, the series connection adjustment pipe MNO connects power supply, and source connects pressure stabilizing
One end of device output end VOUT and first resistor R1, one end ground connection of the second resistance R2
Preferably, the error amplifier circuit include PMOS tube MP1, grid end as inverting input terminal PMOS tube MP2,
PMOS tube MP3 of the grid end as normal phase input end, further include PMOS tube MP4, NMOS tube MN3, NMOS tube MN4, NMOS tube MN5,
NMOS tube MN6 and the source capacitor Cc, PMOS tube MP1 termination power, grid end are connect with PMOS tube MP0 grid end, drain terminal connection
PMOS tube MP2 source and PMOS tube MP3 source, the drain terminal of the drain terminal connection NMOS tube MN3 of PMOS tube MP2, NMOS tube MN3 source
Ground connection, grid end is connected with drain terminal, and connect with NMOS tube MN4 grid end, NMOS tube MN4 source ground connection, drain terminal and PMOS tube
The connection of MP3 drain terminal, the source PMOS tube MP4 termination power, grid end connect PMOS tube MP0 grid end, drain terminal and NMOS tube MN5 drain terminal
Connection, NMOS tube MN5 source ground connection, grid end connect NMOS tube MN4 drain terminal, the capacitor Cc with NMOS tube MN6 drain terminal jointly
Both ends connect respectively with NMOS tube MN5 drain terminal and NMOS tube MN6 source, NMOS tube MN6 grid end connect Adaptive Compensation Control
Circuit.
Preferably, the buffer circuits include grid end connection PMOS tube MP0 grid end, and source connects the PMOS tube of power supply
MP5 connects NMOS tube MN5 with grid end and PMOS tube MP4 is held jointly, the PMOS tube MP6 of drain terminal ground connection, and the PMOS tube MP5
Drain terminal and PMOS tube MP6 source are commonly connected to series connection adjustment pipe MNO grid end.
Preferably, the Adaptive Compensation Control circuit includes PMOS tube MP7, PMOS tube MP8, PMOS tube MP9, NMOS tube
MN7, NMOS tube MN8, NMOS tube MN9, the source NMOS tube MN10, PMOS tube MP7 termination power, grid end connect PMOS tube MP8 grid
End, drain terminal connects NMOS tube MN7 drain terminal, and PMOS tube MP7 grid end is connected with drain terminal, and NMOS tube MN7 source ground connection, grid end meets NMOS
Pipe MN1 grid end, the source PMOS tube MP8 termination power, drain terminal connect NMOS tube MN10 drain terminal, NMOS tube MN10 grid end be connected with drain terminal and
It is connect with NMOS tube MN6 grid end, source connects NMOS tube MN8 drain terminal, NMOS tube MN8 source ground connection, and grid end connects NMOS tube MN1
Grid end, the source PMOS tube MP9 termination power, drain terminal connect NMOS tube MN9 drain terminal, and grid end, which connects load transient response, enhances circuit,
NMOS tube MN9 source ground connection, grid end are connected with drain terminal and connect with NMOS tube MN8 drain terminal.
Preferably, the grid end of the NMOS tube MN6 is connect with the grid end of the NMOS tube MN10 and drain terminal.
Preferably, load transient response enhancing circuit include PMOS tube MP10, PMOS tube MP11, PMOS tube MP12,
PMOS tube MP13, NMOS tube MN11, NMOS tube MN12, NMOS tube MN13, NMOS tube MN14, the PMOS tube MP10 source connect electricity
Source, drain terminal connect series connection adjustment pipe MNO grid end, and grid end connects PMOS tube MP11 grid end, the source PMOS tube MP11 termination power, drain terminal and grid
End be connected and with Adaptive Compensation Control circuit connection, PMOS tube MP11 drain terminal also connect with NMOS tube MN11 drain terminal, NMOS tube
MN11 source ground connection, grid end connect NMOS tube MN12 grid end, NMOS tube MN12 source ground connection, and grid end is connected with drain terminal, drain terminal connection
PMOS tube MP12 drain terminal, PMOS tube MP12 source are connect with its substrate, and are connected to NMOS tube MN14 source, NMOS tube together
MN14 leaks termination power, grid end connection series connection adjustment pipe MNO grid end, and PMOS tube MP12 grid end is connect with PMOS tube MP13 grid end,
PMOS tube MP13 source and its substrate are commonly connected to output end of voltage stabilizer VOUT, and drain terminal is connected with grid end and and NMOS tube
The drain terminal of MN13 connects, and NMOS tube MN13 source ground connection, grid end connects NMOS tube MN1 grid end.
Preferably, the grid end of the PMOS tube MP9 is connect with the PMOS tube MP11 grid end and drain terminal.
In the present invention, a kind of low pressure difference linear voltage regulator of fast transient response, including the amplification of reference voltage source, error
The resistance-feedback network of device, series connection adjustment pipe MNO and first resistor R1 and second resistance R2 composition, further includes being connected to error
Buffer between amplifier out and adjustment pipe MNO grid end of connecting, is connected between series connection adjustment pipe MNO grid end and source
Load transient response enhance circuit, be connected to error amplifier and load transient response enhancing circuit between adaptive equalization
Control circuit, and the biasing circuit of operating current is provided.Compared with prior art, beneficial effects of the present invention at least that:
Adaptive antenna zero compensates the loop stability for improving voltage-stablizer, and NMOS series connection adjustment pipe and load transient response enhancing circuit increase
The strong load transient response of voltage-stablizer, outside no piece in the case where capacitor, unobvious increase quiescent dissipation, present invention obtains
The promotion of low pressure difference linear voltage regulator load transient response performance.
Detailed description of the invention
Fig. 1 is a kind of typical low pressure difference linear voltage regulator schematic diagram；
Fig. 2 is low pressure difference linear voltage regulator hardware connection diagram of the invention；
Fig. 3 is the embodiment of the present invention circuit diagram；
Fig. 4 is the load transient response schematic diagram of the embodiment of the present invention.
Specific embodiment
The embodiment of the present invention is described more fully below, the examples of the embodiments are shown in the accompanying drawings.Below by ginseng
The embodiment for examining attached drawing description is exemplary, and for explaining only the invention, and is not considered as limiting the invention.Phase
Instead, the embodiment of the present invention include the spirit for falling into attached claims and all changes within the scope of intension, modification and
Equivalent.
The present invention provides a kind of low pressure difference linear voltage regulator of fast transient response, with reference to the accompanying drawing to the present invention do into
One step detailed description:
As shown in Figure 1, inventor has studied a kind of typical low pressure difference linear voltage regulator comprising reference voltage circuit,
The resistance-feedback network of error amplifier, series connection adjustment pipe MP0 and resistance R1, R2 composition is constituted, wherein CL is output loading electricity
Hold, IL is output load current, and the reverse input end of error amplifier connects reference voltage circuit, positive input connection electricity
The common end of R1, R2 are hindered, the source of the series connection adjustment pipe MPO connects power supply, and drain terminal connects output end of voltage stabilizer
One end of VOUT and resistance R1, resistance R2 are grounded.
Specifically, feedback resistive network samples output voltage, it is added in error amplifier normal phase input end, and is added in negative
The reference voltage V of input terminalREFIt compares, the difference of the two controls the grid electricity of adjustment pipe MP0 after error amplifier amplifies
Pressure, to stabilize the output voltage；When load current increases, output voltage is reduced, sampling voltage VFBIt reduces, error amplifier is defeated
Voltage reduces out, and the gate source voltage of adjustment pipe MP0 increases, and output electric current increases, and output voltage is increased to nominal value；Similarly, when
When load current reduces, output voltage is increased, sampling voltage VFBIt increases, output voltage error amplifier increases, adjustment pipe MP0's
Gate source voltage reduces, and output electric current reduces, and output voltage is reduced to nominal value.Output voltage nominal value is as follows:
VOUT=(1+R1/R2) VREF
Low pressure difference linear voltage regulator load current is mutated the variation for causing output voltage, the referred to as load transient response of LDO.
Output voltage can be expressed as with load current variation:
ΔVtr=IO-max*Δt/CO, wherein Δ VtrIt is the changing value of output voltage, IO-maxIt is maximum given load electric current
Value, Δ t is the response time of LDO feedback control loop, COIt is output capacitance value.
Above-mentioned LDO can improve load transient response by external μ F grades of output capacitance, but this needs to increase a core
Piece pin increases the complexity and cost of application.Feedback can also be reduced by increasing the quiescent current of error amplifier
The reaction time of loop, to improve the load transient response performance of LDO, but which increase the quiescent dissipations of LDO.
Based on above-mentioned analysis, as shown in Fig. 2, the present invention provides a kind of low pressure difference linear voltage regulator of fast transient response,
The low pressure difference linear voltage regulator of this kind of fast transient response, including reference voltage source, error amplifier, series connection adjustment pipe MNO with
And first resistor R1 and second resistance R2 composition resistance-feedback network, further include be connected to the error amplifier output with
Buffer between series connection adjustment pipe MNO grid end, the load transient being connected between the series connection adjustment pipe MNO grid end and source
Response enhancing circuit, the Adaptive Compensation Control electricity being connected between the error amplifier and load transient response enhancing circuit
Road, and the biasing circuit of operating current is provided.
As shown in figure 3, the biasing circuit includes bias current sources I in the circuit of one embodiment of the inventionB、
NMOS tube MN1, NMOS tube MN2 and PMOS tube MP0, the bias current sources IBOne end connect power supply, the other end connection
NMOS tube MN1 drain terminal, NMOS tube MN1 source ground connection, grid end are connected with drain terminal, the NMOS tube MN2 grid end with it is described
The connection of NMOS tube MN1 grid end, source ground connection, drain terminal are connect with the PMOS tube MP0 drain terminal, and the PMOS tube MP0 source connects
Power supply, grid end are connected with drain terminal.
In one embodiment of the invention, the non-inverting input terminal of the error amplifier connects reference voltage source, anti-
Phase input terminal connects the common end of first resistor R1 and second resistance R2, the drain terminal connection power supply electricity of the series connection adjustment pipe MNO
Source, source connect one end (the non-common end) of output end of voltage stabilizer VOUT and first resistor R1, the second resistance R2
One end (the non-common end) ground connection.
Further, the error amplifier circuit includes the PMOS tube of PMOS tube MP1, grid end as inverting input terminal
MP2, PMOS tube MP3 of the grid end as normal phase input end further include PMOS tube MP4, NMOS tube MN3, NMOS tube MN4, NMOS tube
MN5, NMOS tube MN6 and capacitor Cc, connection type are as follows:
The source PMOS tube MP1 termination power, grid end are connect with PMOS tube MP0 grid end, and drain terminal connects PMOS tube MP2 source
With PMOS tube MP3 source, PMOS tube MP2 drain terminal connection NMOS tube MN3 drain terminal, NMOS tube MN3 source ground connection, grid end with
Drain terminal is connected, and connect with NMOS tube MN4 grid end, and NMOS tube MN4 source ground connection, drain terminal is connect with PMOS tube MP3 drain terminal,
The source PMOS tube MP4 termination power, grid end connect PMOS tube MP0 grid end, and drain terminal is connect with NMOS tube MN5 drain terminal, NMOS tube
MN5 source ground connection, grid end and NMOS tube MN6 drain terminal connect NMOS tube MN4 drain terminal jointly, the both ends of the capacitor Cc respectively with
NMOS tube MN5 drain terminal and NMOS tube MN6 source, NMOS tube MN6 grid end connect Adaptive Compensation Control circuit.
In one embodiment of the invention, the buffer circuits include grid end connection PMOS tube MP0 grid end, and source connects
NMOS tube MN5 is connected with grid end by the PMOS tube MP5 for connecing power supply and PMOS tube MP4 is held jointly, the PMOS tube MP6 of drain terminal ground connection, and
The PMOS tube MP5 drain terminal and PMOS tube MP6 source are commonly connected to series connection adjustment pipe MNO grid end.
In one embodiment of the invention, the Adaptive Compensation Control circuit include PMOS tube MP7, PMOS tube MP8,
PMOS tube MP9, NMOS tube MN7, NMOS tube MN8, NMOS tube MN9, NMOS tube MN10, connection type are as follows:
The source PMOS tube MP7 termination power, grid end connect PMOS tube MP8 grid end, and drain terminal connects NMOS tube MN7 drain terminal, and
PMOS tube MP7 grid end is connected with drain terminal, and NMOS tube MN7 source ground connection, grid end connects NMOS tube MN1 grid end, and PMOS tube MP8 source connects
Power supply, drain terminal connect NMOS tube MN10 drain terminal, and NMOS tube MN10 grid end is connected and connect with NMOS tube MN6 grid end, source with drain terminal
NMOS tube MN8 drain terminal, NMOS tube MN8 source ground connection are connected, grid end connects NMOS tube MN1 grid end, and PMOS tube MP9 source connects electricity
Source, drain terminal connect NMOS tube MN9 drain terminal, and grid end, which connects load transient response, enhances circuit, NMOS tube MN9 source ground connection, grid end with
Drain terminal is connected and connect with NMOS tube MN8 drain terminal.
Further, the grid end of the NMOS tube MN6 is connect with the grid end of the NMOS tube MN10 and drain terminal.
In one embodiment of the invention, the load transient response enhancing circuit includes PMOS tube MP10, PMOS tube
MP11, PMOS tube MP12, PMOS tube MP13, NMOS tube MN11, NMOS tube MN12, NMOS tube MN13, NMOS tube MN14, connection
Mode is as follows:
The source PMOS tube MP10 termination power, drain terminal connect series connection adjustment pipe MNO grid end, and grid end connects PMOS tube MP11 grid
End, the source PMOS tube MP11 termination power, drain terminal be connected with grid end and with Adaptive Compensation Control circuit connection, PMOS tube MP11 leak
End is also connect with NMOS tube MN11 drain terminal, and NMOS tube MN11 source ground connection, grid end connects NMOS tube MN12 grid end, the source NMOS tube MN12
End ground connection, grid end are connected with drain terminal, and drain terminal connects PMOS tube MP12 drain terminal, and PMOS tube MP12 source is connect with its substrate, and one
It rises and is connected to NMOS tube MN14 source, NMOS tube MN14 leaks termination power, grid end connection series connection adjustment pipe MNO grid end, PMOS tube
MP12 grid end is connect with PMOS tube MP13 grid end, and PMOS tube MP13 source and its substrate are commonly connected to output end of voltage stabilizer
VOUT, drain terminal are connected with grid end and connect with the drain terminal of NMOS tube MN13, and NMOS tube MN13 source ground connection, grid end connects NMOS tube
MN1 grid end.
Further, the grid end of the PMOS tube MP9 is connect with PMOS tube MP11 grid end and drain terminal.
Load transient response of the present invention enhances principle: when load current quickly reduces, output voltage increases, series connection adjustment
The gate source voltage of pipe MN0 reduces, and the electric current for flowing through MN0 reduces, and output voltage is inhibited to increase, while load transient response enhancing electricity
The grid voltage of MP13 is increased with output voltage in road, and the gate source voltage of MP12 reduces, and the electric current for flowing through MP12 and MN12 reduces,
MN11 and MN12, MP10 and MP11 constitute current mirror, therefore the electric current for flowing through MP10 reduces, under the voltage for causing MN0 grid VGN
The gate source voltage of drop, MN0 reduces, and the electric current for flowing through MN0 reduces, and further suppresses output voltage increase.
When load current quickly increases, output voltage reduces, and the gate source voltage of series connection adjustment pipe MN0 increases, and flows through MN0
Electric current increase, inhibit output voltage reduce, while load transient response enhancing circuit in MP13 grid voltage with output electricity
Pressure reduces, and the grid voltage of MP12 reduces, and the electric current for flowing through MP12 and MN12 increases, and the electric current for flowing through MP10 increases, and causes MN0
The voltage of grid VGN increases, and the gate source voltage of MN0 increases, and the electric current for flowing through MN0 increases, and further suppresses output voltage reduction.
Adaptive antenna zero compensation principle of the present invention: in order to allow LDO to keep loop stability in entire current load range,
It needs to compensate using adaptive antenna zero.Buffer improves the transient response speed of LDO major loop using one side, on the one hand
So that the pole at series connection adjustment pipe MN0 grid is located at very high frequency, increases loop stability.Two-stage with RC miller compensation
Error amplifier dominant pole is located at first order output, and secondary pole can be separated to higher frequency.When load current reduces,
MN0 mutual conductance reduces, and output terminal impedance increases, and output end pole shifts to origin, and the electric current for flowing through MN14 reduces, through MN11 and
The current mirror of MN12, MP9 and MP11 composition, the electric current for flowing through MP9 reduce, and the electric current for flowing through MN9 also reduces, the grid source electricity of MN9
Pressure reduces, VBR=VGSMN9+VGSMN10Reduce, the gate source voltage of MN6 reduces, and the equivalent conduction impedance of MN6 increases, and RC Muller is mended
The zero point for repaying introducing is mobile to origin, follows the variation of output pole, achievees the purpose that compensation output pole.
Fig. 4 is the load transient response schematic diagram of the embodiment of the present invention.As shown in figure 4, abscissa indicates the time in Fig. 4,
Top ordinate indicates that voltage-stablizer output load current, lower section ordinate indicate stabilizer output voltage.Load capacitance is 100nF
When, load current 10nS jumps to 100mA, output voltage undershoot 50mV by 100 μ A；Load current 10nS is jumped to by 100mA
100 μ A, output voltage overshoot 29mV.It can be seen that the low pressure difference linearity of fast transient response provided in an embodiment of the present invention is steady
Depressor has lesser output undershoot and overshoot.
It is understood that for the those of ordinary skill in field where the present invention, it can be with technology according to the present invention
Scheme and its design carry out corresponding equivalence transformation, without creative equivalence replacement all should belong to disclosed herein model
It encloses.
Claims (9)
1. a kind of low pressure difference linear voltage regulator of fast transient response, it is characterised in that: amplify including reference voltage source, error
The resistance-feedback network of device, series connection adjustment pipe MNO and first resistor R1 and second resistance R2 composition, further include be connected to it is described
Buffer between error amplifier output and adjustment pipe MNO grid end of connecting, be connected to series connection adjustment pipe MNO grid end and
Load transient response between source enhances circuit, is connected between the error amplifier and load transient response enhancing circuit
Adaptive Compensation Control circuit, and provide operating current biasing circuit.
2. a kind of low pressure difference linear voltage regulator of fast transient response according to claim 1, it is characterised in that: described inclined
Circuits include current source IB, NMOS tube MN1, NMOS tube MN2 and PMOS tube MP0, the current source IBOne end connect electricity
Source, the other end connect the NMOS tube MN1 drain terminal, and the NMOS tube MN1 source ground connection, grid end is connected with drain terminal, described
NMOS tube MN2 grid end is connect with the NMOS tube MN1 grid end, and source ground connection, drain terminal is connect with the PMOS tube MP0 drain terminal,
The source PMOS tube MP0 termination power, grid end are connected with drain terminal.
3. a kind of low pressure difference linear voltage regulator of fast transient response according to claim 1, it is characterised in that: the mistake
The non-inverting input terminal of poor amplifier connects reference voltage source, and inverting input terminal connection first resistor R1's and second resistance R2 is total to
With end, the drain terminal of the series connection adjustment pipe MNO connects power supply, and source connects output end of voltage stabilizer VOUT and first resistor
One end of R1, one end ground connection of the second resistance R2.
4. a kind of low pressure difference linear voltage regulator of fast transient response according to claim 1 or 3, it is characterised in that: institute
It states error amplifier circuit and includes PMOS tube MP1, grid end as the PMOS tube MP2 of inverting input terminal, grid end and inputted as positive
The PMOS tube MP3 at end further includes PMOS tube MP4, NMOS tube MN3, NMOS tube MN4, NMOS tube MN5, NMOS tube MN6 and capacitor
The source Cc, PMOS tube MP1 termination power, grid end are connect with PMOS tube MP0 grid end, drain terminal connect PMOS tube MP2 source and
PMOS tube MP3 source, the drain terminal of the drain terminal connection NMOS tube MN3 of PMOS tube MP2, NMOS tube MN3 source ground connection, grid end and leakage
End is connected, and connect with NMOS tube MN4 grid end, and NMOS tube MN4 source ground connection, drain terminal is connect with PMOS tube MP3 drain terminal, PMOS
The source pipe MP4 termination power, grid end connect PMOS tube MP0 grid end, and drain terminal is connect with NMOS tube MN5 drain terminal, the source NMOS tube MN5
End ground connection, grid end and NMOS tube MN6 drain terminal connect NMOS tube MN4 drain terminal jointly, the both ends of the capacitor Cc respectively with NMOS
Pipe MN5 drain terminal is connected with NMOS tube MN6 source, and NMOS tube MN6 grid end connects Adaptive Compensation Control circuit.
5. a kind of low pressure difference linear voltage regulator of fast transient response according to claim 4, it is characterised in that: described slow
Rushing device circuit includes grid end connection PMOS tube MP0 grid end, and the PMOS tube MP5 of source connection power supply connects NMOS tube MN5 with grid end
It is held jointly with PMOS tube MP4, the PMOS tube MP6 of drain terminal ground connection, and the PMOS tube MP5 drain terminal and PMOS tube MP6 source are common
It is connected to series connection adjustment pipe MNO grid end.
6. a kind of low pressure difference linear voltage regulator of fast transient response according to claim 4, it is characterised in that: it is described from
Adaptive compensation control circuit includes PMOS tube MP7, PMOS tube MP8, PMOS tube MP9, NMOS tube MN7, NMOS tube MN8, NMOS tube
MN9, the source NMOS tube MN10, PMOS tube MP7 termination power, grid end connect PMOS tube MP8 grid end, and drain terminal connects NMOS tube MN7 leakage
End, and PMOS tube MP7 grid end is connected with drain terminal, NMOS tube MN7 source ground connection, grid end meets NMOS tube MN1 grid end, PMOS tube MP8
Source termination power, drain terminal connect NMOS tube MN10 drain terminal, and NMOS tube MN10 grid end is connected with drain terminal and connects with NMOS tube MN6 grid end
It connects, source connects NMOS tube MN8 drain terminal, NMOS tube MN8 source ground connection, and grid end connects NMOS tube MN1 grid end, the source PMOS tube MP9
Termination power, drain terminal connect NMOS tube MN9 drain terminal, and grid end, which connects load transient response, enhances circuit, and NMOS tube MN9 source is grounded,
Grid end is connected with drain terminal and connect with NMOS tube MN8 drain terminal.
7. a kind of low pressure difference linear voltage regulator of fast transient response according to claim 6, it is characterised in that: described
The grid end of NMOS tube MN6 is connect with the grid end of the NMOS tube MN10 and drain terminal.
8. a kind of low pressure difference linear voltage regulator of fast transient response according to claim 6, it is characterised in that: described negative
Carry transient response enhancing circuit include PMOS tube MP10, PMOS tube MP11, PMOS tube MP12, PMOS tube MP13, NMOS tube MN11,
NMOS tube MN12, NMOS tube MN13, the source NMOS tube MN14, PMOS tube MP10 termination power, drain terminal meet series connection adjustment pipe MNO
Grid end, grid end connect PMOS tube MP11 grid end, the source PMOS tube MP11 termination power, drain terminal be connected with grid end and with adaptive equalization control
Circuit connection processed, PMOS tube MP11 drain terminal are also connect with NMOS tube MN11 drain terminal, and NMOS tube MN11 source ground connection, grid end meets NMOS
Pipe MN12 grid end, NMOS tube MN12 source ground connection, grid end are connected with drain terminal, and drain terminal connects PMOS tube MP12 drain terminal, PMOS tube
MP12 source is connect with its substrate, and is connected to NMOS tube MN14 source together, and NMOS tube MN14 leaks termination power, grid end connection
Series connection adjustment pipe MNO grid end, PMOS tube MP12 grid end are connect with PMOS tube MP13 grid end, and PMOS tube MP13 source and its substrate are total
With output end of voltage stabilizer VOUT is connected to, drain terminal is connected and connect with the drain terminal of NMOS tube MN13, NMOS tube MN13 with grid end
Source ground connection, grid end connect NMOS tube MN1 grid end.
9. a kind of low pressure difference linear voltage regulator of fast transient response according to claim 8, it is characterised in that: described
The grid end of PMOS tube MP9 is connect with the PMOS tube MP11 grid end and drain terminal.
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