CN104950976A

CN104950976A - Voltage stabilizing circuit based on slew rate increasing

Info

Publication number: CN104950976A
Application number: CN201510256206.5A
Authority: CN
Inventors: 朱吉涵
Original assignee: Techtotop Microelectronics Co Ltd
Current assignee: Techtotop Microelectronics Co Ltd
Priority date: 2015-05-20
Filing date: 2015-05-20
Publication date: 2015-09-30
Anticipated expiration: 2035-05-20
Also published as: CN104950976B

Abstract

The invention discloses a voltage stabilizing circuit based on slew rate increasing. A capacitor device is utilized for directly connecting output voltage VOUT to an M4 transistor grid electrode, and zero-delay loop response is achieved. Quiescent voltage bias is provided for the M4 transistor grid electrode by means of M3, R1 and IB, quiescent voltage bias is provided with for an M4 transistor source electrode by means of a Native NMOS transistor, M2 and C2, it is ensured that the circuit achieves zero-delay loop response, and meanwhile the voltage stabilizing circuit has the advantages of being high in supply voltage rejection ratio, applicable to lower input voltage application environment and the like.

Description

A kind of mu balanced circuit strengthened based on Slew Rate

Technical field

The present invention relates to hardware design field, particularly a kind of mu balanced circuit strengthened based on Slew Rate.

Background technology

At low-power consumption OCL output capacitance-less low pressure difference linear voltage regulator (Capless Low Dropout Regulator, Capless LDO) in system, generally there is a slew rate enhancing circuit (Slew Rate Enhancement Circuits, SRE), for strengthening the charging and discharging currents to LDO power tube grid level where necessary, and then improve the transient response characteristic of LDO output voltage.

Fig. 1 gives the general modfel of the circuit block diagram of Capless LDO.This circuit block diagram chief component has: power MOS pipe MPOW, the feedback resistive network be made up of RFB1 and RFB2, error amplifier, loaded impedance RL and CL and slew rate enhancing circuit SRE.When the load current of LDO is undergone mutation or power tube output current is undergone mutation, cause the big ups and downs of LDO output voltage, thus make the feedback voltage V FB also big ups and downs thereupon that produce via feedback resistive network.After the magnitude of voltage of VFB exceedes the input voltage range of error amplifier, error amplifier enters state of saturation, and after error amplifier is saturated, it can carry out discharge and recharge according to the Slew Rate of self to the gate capacitance of power tube.Error amplifier is the project organization of low-power consumption in many applications, and its Slew Rate exported is very little, fails to meet the demand of loop large-signal response speed.SRE circuit by detecting the fluctuation of output voltage Vout, according to fluctuation situation correspondingly to the charge or discharge electric current outside MPOW pipe grid level supplementary quota, can play and accelerating loop response speed, reducing the effect of output voltage fluctuating range.

Slew rate enhancing circuit can be divided into structure: take comparer as the slew rate enhancing circuit of core, take differentiator as slew rate enhancing circuit, the zero propagation slew rate enhancing circuit of core.Be wherein the operating lag that slew rate enhancing circuit and the slew rate enhancing circuit taking differentiator as core of core all exists in various degree with comparer, can not respond after LDO load generation saltus step at once.Existing zero propagation slew rate enhancing circuit can reach the characteristic of zero propagation, but there are some defects and use restriction, as: be not suitable for high power supply voltage LDO circuit, need extra linear voltage regulator and extra feedback resistive network etc.

Summary of the invention

Based on above-mentioned situation, the invention provides a kind of mu balanced circuit strengthened based on Slew Rate, object is the feature such as large-signal response speed, low-power consumption, high power supply voltage rejection ratio making Capless LDO circuit have zero-lag, avoids existing zero-lag slew rate enhancing circuit simultaneously and is not suitable for high power supply voltage LDO circuit, needs extra linear voltage regulator and the independently shortcoming such as feedback resistance.

A kind of mu balanced circuit strengthened based on Slew Rate, by Native NMOS tube M1, M2, PMOS M3, M4, operational amplifier EA, resistance R1, R2, R3, electric capacity C1, C2 and current source IB form, the drain electrode of Native NMOS tube M1 connects the drain electrode of power port VDD and Native NMOS tube M2, Native NMOS tube M1 source electrode connects output port VOUT, the C12 end of electric capacity C1 and the R21 end of resistance R2, the output terminal ea_o of grid concatenation operation amplifier EA of Native NMOS tube M1, the drain electrode of PMOS M4; The R22 of resistance R2 holds the R31 end of contact resistance R3 and the reverse input end of operational amplifier EA; The R32 end of resistance R3 connects GND port, the C22 end of C2 and the negative terminal of IB; The positive input of operational amplifier EA connects voltage input end mouth VREF; The grid of Native NMOS tube M2 connects bias voltage input mouth VB1, and Native NMOS tube M2 pipe source electrode connects the C21 end of the source electrode of PMOS M3 pipe, PMOS M4 pipe source electrode and electric capacity C2; The grid of PMOS M3 pipe connects the drain electrode of PMOS M3 pipe, the R11 of R1 holds, the anode of IB; M4 tube grid connects the C11 end of C1, the R12 end of R1.

Above-mentioned electric capacity C2 also can adopt open circuit to substitute.

Relative to prior art, a kind of voltage stabilizer based on slew rate enhancing circuit provided by the invention,

One, this circuit output stage adopts Native NMOS as output power metal-oxide-semiconductor, and than the PMOS that it existing scheme generally uses, its advantage is to obtain higher supply-voltage rejection ratio, and this is particularly important in OCL output capacitance-less type LDO.

Two, this circuit adopts the slew rate enhancing circuit of zero-lag, and its large-signal response speed is better than the existing slew rate enhancing circuit of device and differentiator based on the comparison, optimizes the output transient response without capacitor type LDO greatly.

Three, directly adopt electric capacity C1 by grade coupled for VOUT and M4 grid in the program, avoid the shortcoming that existing zero-lag slew rate enhancing circuit is not suitable for high power supply voltage LDO circuit, and do not need extra linear voltage regulator and independently feedback resistive network, simplify circuit, save area.

Four, employing VB1, C2 and Native NMOS M2 is the source class generation voltage bias of M3 and M4, can ensure that this circuit has comparatively high power supply voltage rejection ratio, and be applicable to the feature of low supply voltage.

Accompanying drawing explanation

Fig. 1 is the structural representation of existing low-power consumption OCL output capacitance-less low pressure difference linear voltage regulator;

Fig. 2 is a kind of stabilizator structure schematic diagram based on slew rate enhancing circuit of the present invention;

Fig. 3 is another embodiment of the present invention.

Embodiment

Below in conjunction with better embodiment wherein, the present invention program is described in detail.The present invention utilizes capacitor element directly output voltage VO UT to be connected to M4 pipe grid level, realizes the loop response of zero-lag.Utilize M3, R1, IB to provide quiescent voltage to be biased to M4 pipe grid level simultaneously, Native NMOS tube M2 and C2 is utilized to provide quiescent voltage to be biased to M4 tube source grade, while ensureing this circuit realiration zero-lag loop response, there is high power supply voltage rejection ratio, be applicable to the advantages such as low input applied environment.Output stage adopts Native NMOS as output power metal-oxide-semiconductor, and than the PMOS that it existing scheme generally uses, its advantage is to obtain higher supply-voltage rejection ratio.

A kind of stabilizator structure schematic diagram based on slew rate enhancing circuit has been shown in Fig. 2.

Circuit structure of the present invention comprises: Native NMOS tube M1, M2, PMOS M3, M4, operational amplifier EA, resistance R1, R2, R3, electric capacity C1, C2, current source IB; M1 drain electrode connects the drain electrode of power port VDD and M2, and M1 source electrode connects the C12 end of output port VOUT, C1 and the R21 end of R2, the drain electrode of output terminal ea_o, M4 of the grid concatenation operation amplifier EA of M1; The R22 end of R2 connects the R31 end of R3, the reverse input end of EA; The R32 end of R3 connects GND port, the C22 end of C2, the negative terminal of IB; The positive input of operational amplifier EA connects voltage input end mouth VREF; The grid of M2 connects bias voltage input mouth VB1, and M2 pipe source electrode connects the C21 end of M3 pipe source electrode, M4 pipe source electrode, C2; The grid of M3 pipe connects the drain electrode of M3 pipe, the R11 of R1 holds, the anode of IB; M4 tube grid connects the C11 end of C1, the R12 end of R1.

In this embodiment, whole circuit increases electric capacity C2, the voltage of M4 source node can be made more steady, and then when the voltage of VOUT port, because of load current sudden change, downward overshoot change occurs, M4 grid step voltage changes downwards by c11 coupling, the source class of M4 pipe due to the effect of c2 more stable, at this moment M4 drain terminal can export larger offset current, reduces the downward overshoot amplitude of VOUT output voltage.

In actual applications, the C2 in above-described embodiment can substitute by direct path, and as shown in Figure 3, if do not have C2, M4 equally can export offset current under some circumstances.

In the present embodiment, M1, R2, R3, EA form the conventional control loop of this LDO, M1 is output power device, R2, R3 form feedback resistive network.EA is error amplifier, and M2, M3, M4, C1, C2, R1, IB form slew rate enhancing circuit.

VOUT is output voltage port, and VREF is the input port of bandgap voltage reference, and VB1 is a bias voltage.

M1, M2 type of device is that Native NMOS, Native NMOS tube is also referred to as " intrinsic NMOS tube ", it is the NMOS tube on a kind of direct manufacture and wafer Psub, the difference of it and common NMOS tube is that its threshold voltage is lower, usually close to 0V, is very applicable to low voltage circuit structure.

When system is in stable state, slew rate enhancing circuit does not affect conventional control loop circuit, and VB1, M2, M3, IB provide suitable static bias voltage for M4 jointly, by the drain terminal current offset of M4 under a relatively little static working current.VOUT output voltage and M4 gate voltage all keep static.

Within the load current short time of LDO from underloading saltus step be heavy duty, because VOUT node stray capacitance is smaller, and the conventional control loop response speed of this circuit is slow, and downward voltage fluctuation appears in VOUT voltage.Due to the effect of C1 coupling capacitance, and the resistance of R1 is relatively large, and M4 gate voltage produces the voltage fluctuation of almost zero-lag with amplitude.Due to the effect of VB1, M2, C2, M4 pipe source voltage terminal preserves relative constancy.Like this, the drain terminal of M4 produces the current increment of zero-lag, increases the electric current flowing to M1 grid.The moment of fluctuation is downwards there is at VOUT voltage, supplement to zero-lag M1 pipe grid level electric charge, M1 grid voltage rises, and then improve M1 pipe drain electrode output current, play the effect of the large-signal response of zero-lag, farthest reduce the voltage undershoot amplitude that VOUT voltage produces due to load current change.

The above example only have expressed embodiments of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.

Claims

1. the mu balanced circuit strengthened based on Slew Rate, by Native NMOS tube M1, M2, PMOS M3, M4, operational amplifier EA, resistance R1, R2, R3, electric capacity C1, C2 and current source IB form, it is characterized in that, the drain electrode of Native NMOS tube M1 connects the drain electrode of power port VDD and Native NMOS tube M2, Native NMOS tube M1 source electrode connects output port VOUT, the C12 end of electric capacity C1 and the R21 end of resistance R2, the output terminal ea_o of grid concatenation operation amplifier EA of Native NMOS tube M1, the drain electrode of PMOS M4; The R22 of resistance R2 holds the R31 end of contact resistance R3 and the reverse input end of operational amplifier EA; The R32 end of resistance R3 connects GND port, the C22 end of C2 and the negative terminal of IB; The positive input of operational amplifier EA connects voltage input end mouth VREF; The grid of Native NMOS tube M2 connects bias voltage input mouth VB1, and Native NMOS tube M2 pipe source electrode connects the C21 end of the source electrode of PMOS M3 pipe, PMOS M4 pipe source electrode and electric capacity C2; The grid of PMOS M3 pipe connects the drain electrode of PMOS M3 pipe, the R11 of R1 holds, the anode of IB; M4 tube grid connects the C11 end of C1, the R12 end of R1.

2. mu balanced circuit according to claim 1, is characterized in that, described electric capacity C2 can adopt open circuit to substitute.