CN102880219B - Linear voltage regulator with dynamic compensation characteristic - Google Patents
Linear voltage regulator with dynamic compensation characteristic Download PDFInfo
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- CN102880219B CN102880219B CN201210374909.4A CN201210374909A CN102880219B CN 102880219 B CN102880219 B CN 102880219B CN 201210374909 A CN201210374909 A CN 201210374909A CN 102880219 B CN102880219 B CN 102880219B
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Abstract
The invention discloses a linear voltage regulator with a dynamic compensation characteristic. The linear voltage regulator comprises a level shift circuit, an error amplifier, a dynamic compensation circuit, a current suppressing and boosting circuit, a power tube and a divider resistor. An input preceding stage of the error amplifier is connected with the level shift circuit, a double-stage amplifier form is adopted for the error amplifier, a first stage is in a common-source differential amplifier form, and a load of a second stage is a PMOS (P-channel metal oxide semiconductor) tube in a diode connection form. A grid electrode of the power tube is connected with a grid electrode of another PMOS to realize a current mirror effect, a drain terminal of the PMOS tube is connected with a grid-drain electrode of an NMOS (N-channel metal oxide semiconductor) tube in a diode connection form, and the grid-drain electrode of the NMOS tube is also connected to an output end of the first stage of the error amplifier to be used as a load of the first stage of the error amplifier. The linear voltage regulator has the advantages that frequency stability of a negative feedback loop is automatically regulated under different load conditions so that the linear voltage regulator works stably, and the linear voltage regulator is simple in structure and applicable to universal CMOS (complementary metal oxide semiconductor) processes.
Description
Technical field
The present invention relates to integrated circuit (IC) design technical field, particularly, relate to and a kind ofly can realize the linear voltage regulator that carries out dynamic frequency compensation under different loads condition.
Background technology
Along with sharply expanding and the requirement of integrated circuit fields to level of integrated system increasingly stringent of portable mobile termianl market, increasing functional circuit module is integrated in a system, therefore need the power supply that provides dissimilar, as different magnitudes of voltage, different electrical power rejection ratio etc.Power management module has become ingredient indispensable in system, and wherein, linear voltage regulator is of paramount importance circuit, is conventionally connected on the rear class of Switching Power Supply, and it is realized level conversion and suppresses the function of power supply noise, for system provides, stablizes clean power supply.
Frequency stability is the key in linear voltage regulator design.Linear voltage regulator is to rely on feedback loop to keep the stable of output voltage, when loop does not meet frequency stability condition, in the moment of transient voltage or current break, will cause that vibration is even saturated, make circuit cisco unity malfunction, therefore need to carry out frequency compensation.
Conventional compensation way has the technology such as ESR compensation, miller compensation, nested miller compensation at present.ESR compensation way is the most traditional a kind of compensation technique, but it has limitation very much, situation about only holding for outer contact pin dispatch from foreign news agency, and the selection of electric capacity is restricted, and has certain contradiction in stability and transient response; The shortcoming of miller compensation and nested miller compensation technology maximum is that the bandwidth of feedback loop is very little, poor for the inhibition ability of slightly high-frequency power supply noise.Defect for these several technology when applying for some, also has some technology to be used, as zero limit is followed compensation way and voltage-controlled current source mode.The impact that voltage-controlled current source mode is received load variations is larger, and the zero limit technology of following can be similar to realize and adds the following of antipodal points at zero point, but also needs to adopt ESR compensate assisting to a certain degree simultaneously.
Another function of linear voltage regulator is the inhibition to power supply noise.Along with the raising of chip integration, increasing dissimilar functional module is integrated on chip piece, or more chip is integrated on the pcb board that area is more and more less, therefore the coupling in different electrical power becomes more and more obvious, mutually crosstalking of noise can cause the even capability error of decline of circuit performance, therefore, the power supply of different grouping all needs certain noise inhibiting ability.
Summary of the invention
The object of the invention is to, the linear voltage regulator with dynamic compensation characteristic that a kind of stability is not affected by load variations is proposed, this voltage stabilizer has good power supply noise and suppresses ability, and especially the inhibition ability to high frequency electric source noise, can effectively reduce the impact of transient state power supply noise.
According to technical scheme provided by the invention, the described linear voltage regulator with dynamic compensation characteristic comprises: the 8th NMOS pipe source electrode and the 9th NMOS pipe source electrode connect respectively bias current, the 8th NMOS tube grid connects reference voltage, the 8th NMOS pipe and the 9th NMOS pipe form two source followers, the 8th NMOS pipe source electrode output connects the positive input terminal of the error amplifier first order, the i.e. grid of a PMOS pipe, the 9th NMOS pipe source electrode output connects the negative input end of the error amplifier first order, the i.e. grid of the 2nd PMOS pipe; The one PMOS pipe is common source differential pair with the 2nd PMOS pipe, and source electrode is connected to biasing tail current; The drain electrode of the one PMOS pipe is connected with grid, the drain electrode of the 3rd PMOS pipe, and the drain electrode of the 2nd PMOS pipe is connected with the drain electrode of the 4th PMOS pipe, and the 3rd PMOS manages, the 4th gate pmos is extremely shared; The drain electrode of the 4th PMOS pipe is the output of first order error amplifier, be connected to the input of second level amplifier, the i.e. grid of the 5th NMOS pipe, the drain electrode of the 5th NMOS pipe is connected with grid, the drain electrode of the 6th PMOS pipe, and the grid of the 6th PMOS pipe is connected to the grid of the 7th gate pmos utmost point and the first power tube; The drain electrode of the 7th PMOS pipe is connected with grid, the drain electrode of the second power tube, the grid of the second power tube, the drain electrode that drain electrode connects the 4th PMOS pipe simultaneously; The second power tube is the frequency compensation pipe of a diode type of attachment; The drain electrode of the first power tube is the output terminal of linear voltage regulator, connects with divider resistance series winding; Described divider resistance string is composed in series by the first resistance, the second resistance, the first power tube drain electrode is first connected to the first resistance, then by the second resistance eutral grounding, the common terminal of the first resistance and the second resistance produces feedback voltage, be connected to the 9th NMOS tube grid, composition negative feedback loop; Described the 3rd PMOS pipe source electrode, the 4th PMOS pipe source electrode, the second power tube source electrode, the 5th NMOS pipe source ground; Described the 8th NMOS pipe drain electrode, the 9th NMOS pipe drain electrode, the 6th PMOS pipe source electrode, the 7th PMOS pipe source electrode, the first power tube source electrode connect supply voltage.
Described the first power tube drain electrode, connects load capacitance between the output terminal of linear voltage regulator and ground, for load provides voltage stabilizing.
Described the 8th NMOS pipe and the 9th NMOS pipe, two pipe sizes and bias current are strict keeps equal, to realize equal gate source voltage.
Described load capacitance adopts the form of the outer electric capacity of sheet to realize, or adopts mos capacitance on sheet to realize, and realizes the function of voltage regulation filtering.
Advantage of the present invention is: the linear voltage regulator with dynamic compensation characteristic that the present invention proposes can be realized according to the function of load variations dynamic adjustments stability, and increased on this basis the inhibition ability to power supply noise, meet the application of low supply voltage simultaneously.The circuit structure that the present invention proposes is simple, is convenient to realize.
Accompanying drawing explanation
Fig. 1 is the circuit structure diagram of the embodiment of the present invention.
Fig. 2 is the signal flow diagram of the feedback control loop that circuit is corresponding described in the embodiment of the present invention.
Fig. 3 is that circuit power suppresses principle schematic described in the embodiment of the present invention.
Embodiment
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
The linear voltage regulator with dynamic compensation characteristic of the present invention mainly comprises: level shift circuit, and error amplifier, dynamics compensation circuits, power supply suppresses to promote circuit, and power tube and divider resistance.Wherein, error amplifier input prime connects level shift circuit, and level shift circuit adopts source follower form to realize, and also can adopt emitter follower to realize, to meet low supply voltage condition of work.Error amplifier adopts two-stage amplifier form to realize, the first order is common source differential amplifier form, second level load is the PMOS pipe of diode type of attachment, the bias PMOS pipe that the grid voltage of this pipe is power tube and compensating pipe provides grid bias, realize electric current and be scaled mirror, its role is to promote Power Supply Rejection Ratio.Power tube grid is connected and realizes current mirror with another PMOS grid, this PMOS pipe drain terminal is connected to the NMOS pipe grid leak utmost point that diode form connects, this NMOS pipe grid leak utmost point is also connected to the output terminal of the error amplifier first order simultaneously, as the load of first order error amplifier.Dynamics compensation circuits adopts the metal-oxide-semiconductor of bias current diode type of attachment proportional to load current to realize, and power supply inhibition lifting circuit is adopted as power tube provides the PMOS pipe of the diode type of attachment of grid voltage to realize.
As shown in Figure 1, according to embodiments of the invention, circuit adopts CMOS technique to realize.Concrete structure comprises: error amplifier prime is two source followers, the 8th NMOS pipe M8 and the 9th NMOS pipe M9 source electrode meet respectively bias current Ib, the 8th NMOS pipe M8 grid connects reference voltage, be generally bandgap voltage reference, be about 1.25V left and right, the 9th NMOS pipe M9 grid connects the output voltage stabilizing of feeding back after electric resistance partial pressure, the 8th NMOS pipe M8 source electrode output connects the positive input terminal of the error amplifier first order, the i.e. grid of a PMOS pipe M1, the 9th NMOS pipe M9 source electrode output connects the negative input end of the error amplifier first order, the i.e. grid of the 2nd PMOS pipe M2.The one PMOS pipe M1 and the 2nd PMOS pipe M2 are common source differential pair, source electrode is connected to biasing tail current Id, the drain electrode of the one PMOS pipe M1 is connected with the grid leak utmost point of the 3rd PMOS pipe M3, the drain electrode of the 2nd PMOS pipe M2 is connected with the drain electrode of the 4th PMOS pipe M4, and the 3rd PMOS pipe M3, the 4th PMOS pipe M4 grid share.The drain electrode of the 4th PMOS pipe M4 is the output of first order error amplifier, be connected to the input of second level amplifier, the i.e. grid of the 5th NMOS pipe M5, the drain electrode of the 5th NMOS pipe M5 is connected with grid, the drain electrode of the 6th PMOS pipe M6, and the grid of the 6th PMOS pipe M6 is connected to the grid of the 7th PMOS pipe M7 and the first power tube MP.The drain electrode of the 7th PMOS pipe M7 is connected with the grid leak utmost point of the second power tube MC, and the grid leak utmost point of the second power tube MC is connected to the output of first order error amplifier simultaneously, i.e. the drain electrode of the 4th PMOS pipe M4.The drain electrode of the first power tube MP is output end of voltage stabilizer, connects with the divider resistance series winding of the form of connecting.Divider resistance string is composed in series by the first resistance R 1, the second resistance R 2, second resistance R 2 one end ground connection, first resistance R 1 one termination the first power tube MP drain electrodes, the first resistance R 1, the second resistance R 2 common terminal produce feedback voltage, be connected to the 9th NMOS pipe M9 grid, composition negative feedback loop.The first power tube MP drain electrode is that output end of pressure-stabilizing connects large capacitor C L, is load I
lvoltage stabilizing is provided.Capacitor C L is generally the outer electric capacity of sheet, also can adopt mos capacitance on sheet to realize.
The present invention is by adopting proportional mirror image with the 7th PMOS pipe M7 of the first power tube MP common gate to load current, biasing using sample rate current as the second power tube MC simultaneously, the second power tube MC is the frequency compensation pipe of a diode type of attachment, make the MC can the regulating error amplifier gain with load variations as the output of first order error amplifier, thus the frequency stability of dynamic adjustments voltage stabilizer; By introducing, improved the inhibition ability of the first power tube MP to power supply noise with the 6th PMOS pipe M6 of the diode type of attachment of the first power tube MP common gate; By introducing level shift circuit, can meet output voltage stabilizing and the application of supply voltage low voltage difference and the application of low supply voltage.
As shown in Figure 2, have in the signal flow diagram of linear voltage regulator feedback loop of dynamic compensation characteristic, follower small-signal gain is+1, and first order error amplifier gain is G
m1, output resistance is r
o1, output capacitance Co1, the equivalent resistance of the compensating pipe MC of diode type of attachment is g
mC, g
mPfor power tube mutual conductance, g
m5, g
m6for M5, the mutual conductance of M6 pipe, linear voltage regulator pull-up resistor
i
lfor load current, CL is load capacitance, and intrinsic standoff ratio is
set M7, the breadth length ratio of M6 and power tube MP is
m7, M6, MP common gate, composition current mirror, is therefore I by the electric current of M7 and MC
l/ m.According to signal flow diagram, the transport function of loop can be expressed as:
This loop has three limits:
for the dominant pole of output end of voltage stabilizer, wherein, R12=R1||R2;
For loop time limit, i.e. the output terminal limit of first order amplifier;
for loop the 3rd limit, i.e. second level amplifier out limit, C
gPfor power tube grid stray capacitance.It should be noted that structure that the present invention proposes is mainly used in being respectively internal module voltage stabilizing is provided, therefore fully loaded ability is several milliamperes of levels, power tube moderate dimensions, therefore grid stray capacitance C
gPnot quite, need to meet m<<n simultaneously, under these application conditions, the 3rd limit f
pn2be positioned at upper frequency place, on the impact of stability, can ignore.This structure is not suitable for the more voltage stabilizer of heavy load Capability Requirement.
Because the output stage of first order error amplifier has adopted the compensating pipe MC of diode connected mode as load, therefore output impedance diminishes, loop gain also diminishes thereupon, and power supply inhibition ability is subject to the impact of feedback loop gain, so having weakened the power supply of linear voltage regulator, dynamics compensation circuits suppresses ability.The type of attachment of second level error amplifier is not substantially introduced and is gained for loop, but can improve the inhibition to power supply noise, reduces compensating circuit suppresses ability impact on power supply.
As shown in Figure 3, the load of power tube grid and second level error amplifier is the M6 pipe of diode type of attachment, and grid provides grid voltage for power tube MP.When sudden change noise appears in power supply, because the loop response time is long, the curent change that therefore flows through M6 lags behind, when supply voltage sudden change, remain unchanged, according to
the poor V of M6 pipe gate source voltage
dd-V
gPremain unchanged, i.e. M6 grid voltage V
gPfollow supply voltage V
ddvariation, therefore, the grid voltage of power tube MP is also followed the variation of supply voltage, thereby makes the output current of power tube MP keep stable, is not subject to the impact of supply voltage, therefore the output voltage stabilizing of linear voltage regulator keeps stable.This structure can make effectively to promote linear voltage regulator the inhibition ability to power supply noise, the especially inhibition to high frequency noise.
In sum, technical solution of the present invention has following characteristics:
1, compensating circuit is adjusted linear voltage regulator feedback control loop pole distribution dynamically, make can meet frequency stability requirement under different loads condition, and it is simple to implement circuit structure, and area occupied is little.
2, the introducing of level shift circuit makes voltage regulator circuit can meet the situation that pressure reduction is less or supply voltage is lower, is suitable for the circuit under low-voltage circuit or small-feature-size process conditions.
3, power supply inhibition ability is especially improved to the inhibition ability of high frequency electric source noise, has overcome the long shortcoming that has weakened transient state power supply noise inhibition ability of traditional structure intermediate ring road response time.
4, in the applicable structure of the present invention, fully loaded ability corresponding to power tube size, several milliamperes of levels, is not suitable for the more application of heavy load Capability Requirement.
5, the circuit structure that the present invention proposes is applicable to CMOS technique.
Claims (4)
1. one kind has the linear voltage regulator of dynamic compensation characteristic, it is characterized in that comprising: the 8th NMOS pipe (M8) source electrode and the 9th NMOS pipe (M9) source electrode connect respectively bias current (Ib), the 8th NMOS pipe (M8) grid connects reference voltage (VREF), the 8th NMOS pipe (M8) and the 9th NMOS pipe (M9) form two source followers, the 8th NMOS pipe (M8) source electrode output connects the positive input terminal of the error amplifier first order, the i.e. grid of a PMOS pipe (M1), the 9th NMOS pipe (M9) source electrode output connects the negative input end of the error amplifier first order, the i.e. grid of the 2nd PMOS pipe (M2), the one PMOS pipe (M1) is common source differential pair with the 2nd PMOS pipe (M2), and source electrode is connected to biasing tail current (Id), the drain electrode of the one PMOS pipe (M1) is connected with grid, drain electrode that the 3rd PMOS manages (M3), and the drain electrode of the 2nd PMOS pipe (M2) is connected with the drain electrode that the 4th PMOS manages (M4), and the 3rd PMOS pipe (M3), the 4th PMOS pipe (M4) grid share, the drain electrode of the 4th PMOS pipe (M4) is the output of first order error amplifier, be connected to the input of second level amplifier, the i.e. grid of the 5th NMOS pipe (M5), the drain electrode of the 5th NMOS pipe (M5) is connected with grid, drain electrode that the 6th PMOS manages (M6), and the grid of the 6th PMOS pipe (M6) is connected to the grid of the 7th PMOS pipe (M7) grid and the first power tube (MP), the 7th PMOS pipe drain electrode of (M7) is connected with the grid of the second power tube (MC), drain electrode, the grid of the second power tube (MC), the drain electrode that drain electrode connects the 4th PMOS pipe (M4) simultaneously, the second power tube (MC) is the frequency compensation pipe of a diode type of attachment, the output terminal that the drain electrode of the first power tube (MP) is linear voltage regulator, connects with divider resistance series winding, described divider resistance string is composed in series by the first resistance (R1), the second resistance (R2), the first power tube (MP) drain electrode is first connected to the first resistance (R1), again by the second resistance (R2) ground connection, the common terminal of the first resistance (R1) and the second resistance (R2) produces feedback voltage, be connected to the 9th NMOS pipe (M9) grid, composition negative feedback loop, described the 3rd PMOS pipe (M3) source electrode, the 4th PMOS pipe (M4) source electrode, the second power tube (MC) source electrode, the 5th NMOS pipe (M5) source ground, described the 8th NMOS pipe (M8) drain electrode, the 9th NMOS pipe (M9) drain electrode, the 6th PMOS pipe (M6) source electrode, the 7th PMOS pipe (M7) source electrode, the first power tube (MP) source electrode connect supply voltage (VDD).
2. the linear voltage regulator with dynamic compensation characteristic according to claim 1, is characterized in that, described the first power tube (MP) drain electrode, connects load capacitance (CL) between the output terminal of linear voltage regulator and ground, be load (I
l) voltage stabilizing is provided.
3. the linear voltage regulator with dynamic compensation characteristic according to claim 1, is characterized in that, described the 8th NMOS pipe (M8) and the 9th NMOS pipe (M9), and two pipe sizes and bias current are strict keeps equal, to realize equal gate source voltage.
4. the linear voltage regulator with dynamic compensation characteristic according to claim 2, is characterized in that, described load capacitance (CL) adopts the form of the outer electric capacity of sheet to realize, or adopts mos capacitance on sheet to realize, and realizes the function of voltage regulation filtering.
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| KR20170075892A (en) * | 2015-12-23 | 2017-07-04 | 에스케이하이닉스 주식회사 | Differential amplifier circuit, voltage regulator and semiconductor memory device including the same |
| EP3709123A1 (en) | 2019-03-12 | 2020-09-16 | ams AG | Voltage regulator, integrated circuit and method for voltage regulation |
| CN110082584B (en) * | 2019-05-24 | 2024-01-30 | 深圳市思远半导体有限公司 | Low-voltage wide-bandwidth high-speed current sampling circuit |
| CN110274703A (en) * | 2019-07-12 | 2019-09-24 | 广州芯世物科技有限公司 | A kind of the CMOS temperature-sensitive circuit and temperature sensor of high sensitivity |
| US10996699B2 (en) * | 2019-07-30 | 2021-05-04 | Stmicroelectronics Asia Pacific Pte Ltd | Low drop-out (LDO) voltage regulator circuit |
| CN113342110B (en) * | 2021-06-21 | 2022-04-22 | 电子科技大学 | Error amplifier circuit with dynamic zero compensation |
| CN113641206B (en) * | 2021-10-15 | 2021-12-28 | 成都时识科技有限公司 | Integrated circuit with filtering function |
| CN113970949B (en) * | 2021-12-27 | 2022-03-29 | 江苏长晶科技股份有限公司 | High-speed linear voltage stabilizer with quick response |
| CN114564067B (en) * | 2022-02-18 | 2024-05-24 | 上海灿瑞科技股份有限公司 | Low-dropout linear voltage regulator with high power supply rejection ratio |
| CN114840050A (en) * | 2022-03-16 | 2022-08-02 | 上海华虹宏力半导体制造有限公司 | Loop circuit compensation circuit |
| CN115664408B (en) * | 2022-11-10 | 2023-11-21 | 江苏谷泰微电子有限公司 | Level shifter of unknown voltage domain |
| CN117590890B (en) * | 2024-01-18 | 2024-04-09 | 江苏云途半导体有限公司 | Bidirectional rapid response method and circuit based on vehicle-mounted LDO |
| CN117631741B (en) * | 2024-01-25 | 2024-04-09 | 苏州锴威特半导体股份有限公司 | LDO circuit with current-limiting output |
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| FR2881537B1 (en) * | 2005-01-28 | 2007-05-11 | Atmel Corp | STANDARD CMOS REGULATOR WITH LOW FLOW, HIGH PSRR, LOW NOISE WITH NEW DYNAMIC COMPENSATION |
| CN100403632C (en) * | 2005-04-15 | 2008-07-16 | 矽创电子股份有限公司 | Fast restoring low voltage drop linear voltage stabilizer |
| CN101957628B (en) * | 2009-07-17 | 2014-01-29 | 上海沙丘微电子有限公司 | Self-adaption zero-frequency compensation circuit in low-voltage difference linear voltage regulator |
| CN101963820B (en) * | 2009-07-21 | 2013-11-06 | 意法半导体研发（上海）有限公司 | Self-adapting Miller compensation type voltage regulator |
| CN102566634B (en) * | 2010-12-13 | 2014-03-19 | 联芯科技有限公司 | Linear voltage stabilizing circuit |
| CN202372876U (en) * | 2011-12-20 | 2012-08-08 | 上海贝岭股份有限公司 | Low-dropout linear voltage regulator with frequency compensating function |
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