CN102880219A - Linear voltage regulator with dynamic compensation characteristic - Google Patents
Linear voltage regulator with dynamic compensation characteristic Download PDFInfo
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- CN102880219A CN102880219A CN2012103749094A CN201210374909A CN102880219A CN 102880219 A CN102880219 A CN 102880219A CN 2012103749094 A CN2012103749094 A CN 2012103749094A CN 201210374909 A CN201210374909 A CN 201210374909A CN 102880219 A CN102880219 A CN 102880219A
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Abstract
The invention discloses a linear voltage regulator with a dynamic compensation characteristic. The linear voltage regulator comprises a level shift circuit, an error amplifier, a dynamic compensation circuit, a current suppressing and boosting circuit, a power tube and a divider resistor. An input preceding stage of the error amplifier is connected with the level shift circuit, a double-stage amplifier form is adopted for the error amplifier, a first stage is in a common-source differential amplifier form, and a load of a second stage is a PMOS (P-channel metal oxide semiconductor) tube in a diode connection form. A grid electrode of the power tube is connected with a grid electrode of another PMOS to realize a current mirror effect, a drain terminal of the PMOS tube is connected with a grid-drain electrode of an NMOS (N-channel metal oxide semiconductor) tube in a diode connection form, and the grid-drain electrode of the NMOS tube is also connected to an output end of the first stage of the error amplifier to be used as a load of the first stage of the error amplifier. The linear voltage regulator has the advantages that frequency stability of a negative feedback loop is automatically regulated under different load conditions so that the linear voltage regulator works stably, and the linear voltage regulator is simple in structure and applicable to universal CMOS (complementary metal oxide semiconductor) processes.
Description
Technical field
The present invention relates to the integrated circuit (IC) design technical field, particularly, relate to and a kind ofly can be implemented in the linear voltage regulator that carries out dynamic frequency compensation under the different loads condition.
Background technology
Along with the requirement to the level of integrated system increasingly stringent of the rapid expansion in portable mobile termianl market and integrated circuit fields, increasing functional circuit module is integrated in the system, therefore need to provide dissimilar power supplys, such as different magnitudes of voltage, different electrical power rejection ratio etc.Power management module has become ingredient indispensable in the system, and wherein, linear voltage regulator is of paramount importance circuit, usually is connected on the rear class of Switching Power Supply, and it is realized level conversion and suppress the function of power supply noise, stablizes clean power supply for system provides.
Frequency stability is the key in the linear voltage regulator design.Linear voltage regulator is to rely on feedback loop to keep the stable of output voltage, when loop does not satisfy the frequency stability condition, will cause vibration even saturated in the moment of transient voltage or current break, make the circuit cisco unity malfunction, therefore need to carry out frequency compensation.
Compensation way commonly used has the technology such as ESR compensation, miller compensation, nested miller compensation at present.The ESR compensation way is the most traditional a kind of compensation technique, but it has limitation very much, situation about only holding for outer contact pin dispatch from foreign news agency, and the selection of electric capacity is restricted, and has certain contradiction in stability and transient response; The shortcoming of miller compensation and nested miller compensation technology maximum is that the bandwidth of feedback loop is very little, and is relatively poor for the inhibition ability of slightly high-frequency power supply noise.For the defective of these several technology when using for some, also have some technology to be used, follow compensation way and voltage-controlled current source mode such as zero limit.The impact that the voltage-controlled current source mode is received load variations is larger, and the zero limit technology of following can be similar to and realizes adding following of antipodal points at zero point, but also needs to adopt simultaneously to a certain degree auxiliary of ESR compensation.
Another function of linear voltage regulator is the inhibition to power supply noise.Raising along with chip integration, increasing dissimilar functional module is integrated on the chip piece, or more chip is integrated on the more and more less pcb board of area, therefore the coupling on the different electrical power becomes more and more obvious, decline even the capability error of mutually crosstalking and to cause circuit performance of noise, therefore, the power supply of different grouping all needs certain noise inhibiting ability.
Summary of the invention
The object of the invention is to, the linear voltage regulator with dynamic compensation characteristic that a kind of stability is not affected by load variations is proposed, this voltage stabilizer has preferably power supply noise inhibition ability, especially to the inhibition ability of high frequency electric source noise, can effectively reduce the impact of transient state power supply noise.
According to technical scheme provided by the invention, described linear voltage regulator with dynamic compensation characteristic comprises: the 8th NMOS pipe source electrode and the 9th NMOS pipe source electrode connect respectively bias current, the 8th NMOS tube grid connects reference voltage, the 8th NMOS pipe and the 9th NMOS pipe consist of two source followers, the output of the 8th NMOS pipe source electrode connects the positive input terminal of the error amplifier first order, the i.e. grid of a PMOS pipe, the output of the 9th NMOS pipe source electrode connects the negative input end of the error amplifier first order, the i.e. grid of the 2nd PMOS pipe; The one PMOS pipe is the common source differential pair with the 2nd PMOS pipe, and source electrode is connected to the biasing tail current; The drain electrode of the one PMOS pipe is connected with grid, the drain electrode of the 3rd PMOS pipe, and the drain electrode of the 2nd PMOS pipe is connected with the drain electrode of the 4th PMOS pipe, and the 3rd PMOS manages, the 4th gate pmos is extremely shared; The drain electrode of the 4th PMOS pipe is the output of first order error amplifier, be connected to the input of second level amplifier, the i.e. grid of the 5th NMOS pipe, the grid of the 5th NMOS pipe is connected with grid, the drain electrode of the 6th PMOS pipe, and the grid of the 6th PMOS pipe is connected to the grid of the 7th gate pmos utmost point and power tube; The drain electrode of the 7th PMOS pipe is connected with grid, the drain electrode of a NMOS pipe, and the grid of a NMOS pipe, drain electrode connect the drain electrode of the 4th PMOS pipe simultaneously; The one NMOS pipe is the frequency compensation pipe of a diode type of attachment; The drain electrode of power tube is the output terminal of linear voltage regulator, connects with the divider resistance series winding; Described divider resistance string is composed in series by the first resistance, the second resistance, the power tube drain electrode is connected to first the first resistance, and again by the second resistance eutral grounding, the common terminal of the first resistance and the second resistance produces feedback voltage, be connected to the 9th NMOS tube grid, form negative feedback loop; Described the 3rd PMOS pipe source electrode, the 4th PMOS pipe source electrode, NMOS pipe source electrode, the 5th NMOS manage source ground; The drain electrode of described the 8th NMOS pipe, the drain electrode of the 9th NMOS pipe, the 6th PMOS pipe source electrode, the 7th PMOS pipe source electrode, power tube source electrode connect supply voltage.
Described power tube drain electrode namely connects load capacitance between the output terminal of linear voltage regulator and the ground, for load provides voltage stabilizing.
Described the 8th NMOS pipe and the 9th NMOS pipe, the strict maintenance of two pipe sizes and bias current equates, with the gate source voltage of realizing equating.
Described load capacitance adopts the form of the outer electric capacity of sheet to realize, or adopts mos capacitance realization on the sheet, realizes the function of voltage regulation filtering.
Advantage of the present invention is: the linear voltage regulator with dynamic compensation characteristic that the present invention proposes can be realized the function according to load variations dynamic adjustments stability, and increased on this basis inhibition ability to power supply noise, satisfy simultaneously the application of low supply voltage.The circuit structure that the present invention proposes is simple, is convenient to realize.
Description of drawings
Fig. 1 is the circuit structure diagram of the embodiment of the invention.
Fig. 2 is the signal flow diagram of feedback control loop corresponding to the described circuit of the embodiment of the invention.
Fig. 3 is that the described circuit power of the embodiment of the invention suppresses principle schematic.
Embodiment
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Linear voltage regulator with dynamic compensation characteristic of the present invention mainly comprises: level shift circuit, and error amplifier, dynamics compensation circuits, power supply suppresses to promote circuit, and power tube and divider resistance.Wherein, error amplifier input prime connects level shift circuit, and level shift circuit adopts the source follower form to realize, also can adopt emitter follower to realize, to satisfy the low supply voltage condition of work.Error amplifier adopts the two-stage amplifier form to realize, the first order is common source differential amplifier form, second level load is the PMOS pipe of diode type of attachment, the grid voltage of this pipe provides grid bias for the bias PMOS pipe of power tube and compensating pipe, realize that electric current is scaled mirror, its role is to promote Power Supply Rejection Ratio.The power tube grid is connected with another PMOS grid realizes current mirror, this PMOS pipe drain terminal is connected to the NMOS pipe grid leak utmost point that the diode form connects, this NMOS pipe grid leak utmost point also is connected to the output terminal of the error amplifier first order simultaneously, as the load of first order error amplifier.Dynamics compensation circuits adopts the metal-oxide-semiconductor of bias current and the proportional diode type of attachment of load current to realize, power supply inhibition lifting circuit is adopted as power tube provides the PMOS pipe of the diode type of attachment of grid voltage to realize.
As shown in Figure 1, according to embodiments of the invention, circuit adopts CMOS technique to realize.Concrete structure comprises: the error amplifier prime is two source followers, the 8th NMOS pipe M8 and the 9th NMOS pipe M9 source electrode meet respectively bias current Ib, the 8th NMOS pipe M8 grid connects reference voltage, be generally bandgap voltage reference, be about about 1.25V, the 9th NMOS pipe M9 grid connects the output voltage stabilizing of feeding back behind electric resistance partial pressure, the output of the 8th NMOS pipe M8 source electrode connects the positive input terminal of the error amplifier first order, namely a PMOS manages the grid of M1, the output of the 9th NMOS pipe M9 source electrode connects the negative input end of the error amplifier first order, the i.e. grid of the 2nd PMOS pipe M2.The one PMOS pipe M1 and the 2nd PMOS pipe M2 are the common source differential pair, source electrode is connected to biasing tail current Id, the drain electrode of the one PMOS pipe M1 is connected with the grid leak utmost point of the 3rd PMOS pipe M3, the drain electrode of the 2nd PMOS pipe M2 is connected with the drain electrode of the 4th PMOS pipe M4, and the 3rd PMOS pipe M3, the 4th PMOS pipe M4 grid shares.The drain electrode of the 4th PMOS pipe M4 is the output of first order error amplifier, be connected to the input of second level amplifier, namely the 5th NMOS manages the grid of M5, the grid of the 5th NMOS pipe M5 is connected with the grid leak utmost point of the 6th PMOS pipe M6, and the grid of the 6th PMOS pipe M6 is connected to the grid of the 7th PMOS pipe M7 and power tube MP.The drain electrode of the 7th PMOS pipe M7 is connected with the grid leak utmost point of NMOS pipe MC, and the grid leak utmost point of NMOS pipe MC is connected to the output of first order error amplifier, the i.e. drain electrode of the 4th PMOS pipe M4 simultaneously.The drain electrode of power tube MP is output end of voltage stabilizer, connects with the divider resistance series winding of the form of connecting.The divider resistance string is composed in series by the first resistance R 1, the second resistance R 2, the second resistance R 2 one end ground connection, the first resistance R 1 one termination power tube MP drain electrode, the first resistance R 1, the second resistance R 2 common terminal produce feedback voltage, be connected to the 9th NMOS pipe M9 grid, form negative feedback loop.Power tube MP drain electrode is that output end of pressure-stabilizing connects large capacitor C L, is load I
LVoltage stabilizing is provided.Capacitor C L is generally the outer electric capacity of sheet, also can adopt on the sheet mos capacitance to realize.
The present invention adopts proportional mirror image by the 7th PMOS pipe M7 with power tube MP common gate to load current, simultaneously with the biasing of sample rate current as NMOS pipe MC, the one NMOS pipe MC is the frequency compensation pipe of a diode type of attachment, so that MC can the regulating error amplifier gain with load variations as the output of first order error amplifier, thereby the frequency stability of dynamic adjustments voltage stabilizer; Improved the inhibition ability of power tube MP to power supply noise by the 6th PMOS pipe M6 that introduces with the diode type of attachment of power tube MP common gate; By introducing level shift circuit, can satisfy output voltage stabilizing and the application of supply voltage low voltage difference and the application of low supply voltage.
As shown in Figure 2, have in the signal flow diagram of linear voltage regulator feedback loop of dynamic compensation characteristic, the follower small-signal gain is+1, and first order error amplifier gain is G
M1, output resistance is r
O1, output capacitance Co1, the equivalent resistance of the compensating pipe MC of diode type of attachment is g
MC, g
MPBe power tube mutual conductance, g
M5, g
M6Be M5, the mutual conductance of M6 pipe, linear voltage regulator pull-up resistor
I
LBe load current, CL is load capacitance, and intrinsic standoff ratio is
Set M7, the breadth length ratio of M6 and power tube MP is
M7, M6, the MP common gate forms current mirror, and therefore the electric current by M7 and MC is I
L/ m.According to signal flow diagram, the transport function of loop can be expressed as:
This loop has three limits:
Be the dominant pole of output end of voltage stabilizer, wherein, R12=R1||R2;
Be loop time limit, i.e. the output terminal limit of first order amplifier;
Be loop the 3rd limit, i.e. second level amplifier out limit, C
GPBe power tube grid stray capacitance.It should be noted that structure that the present invention proposes is mainly used in being respectively internal module voltage stabilizing is provided, therefore fully loaded ability is several milliamperes of levels, power tube moderate dimensions, so grid stray capacitance C
GPNot quite, need satisfy simultaneously m＜＜n, under these application conditions, the 3rd limit f
Pn2Be positioned at the upper frequency place, can ignore the impact of stability.This structure is not suitable for the more voltage stabilizer of heavy load Capability Requirement.
Because the output stage of first order error amplifier has adopted the compensating pipe MC of diode connected mode as load, therefore output impedance diminishes, loop gain also diminishes thereupon, and power supply inhibition ability is subject to the impact of feedback loop gain, suppresses ability so dynamics compensation circuits has weakened the power supply of linear voltage regulator.The type of attachment of second level error amplifier is not introduced gain for loop substantially, but can improve the inhibition to power supply noise, reduces compensating circuit suppresses ability on power supply impact.
As shown in Figure 3, the load of power tube grid and second level error amplifier is the M6 pipe of diode type of attachment, and grid provides grid voltage for power tube MP.When the sudden change noise appearred in power supply, because the loop response time is long, the curent change that therefore flows through M6 lagged behind, when supply voltage sudden change, remain unchanged, according to
The poor V of M6 pipe gate source voltage
Dd-V
GPRemain unchanged, i.e. M6 grid voltage V
GPFollow supply voltage V
DdVariation, therefore, the grid voltage of power tube MP is also followed the variation of supply voltage, thereby so that the output current of power tube MP keeps stable, is not subjected to the impact of supply voltage, it is stable that therefore the output voltage stabilizing of linear voltage regulator keeps.This structure can make effective lifting linear voltage regulator to the inhibition ability of power supply noise, especially to the inhibition of high frequency noise.
In sum, technical solution of the present invention has following characteristics:
1, compensating circuit is adjusted linear voltage regulator feedback control loop pole distribution dynamically, so that under the different loads condition, can both satisfy the frequency stability requirement, and it is simple to implement circuit structure, and area occupied is little.
2, the introducing of level shift circuit makes voltage regulator circuit can satisfy the situation that pressure reduction is less or supply voltage is lower, is suitable for the circuit under low-voltage circuit or the small-feature-size process conditions.
3, power supply inhibition ability especially is improved to the inhibition ability of high frequency electric source noise, has overcome the shortcoming of the long transient state power supply noise inhibition ability that weakened of traditional structure intermediate ring road response time.
4, fully loaded ability corresponding to power tube size is not suitable for the more application of heavy load Capability Requirement several milliamperes of levels in the structure that is suitable for of the present invention.
5, the circuit structure of the present invention's proposition is applicable to CMOS technique.
Claims (4)
1. linear voltage regulator with dynamic compensation characteristic, it is characterized in that comprising: the 8th NMOS pipe (M8) source electrode and the 9th NMOS pipe (M9) source electrode connect respectively bias current (Ib), the 8th NMOS pipe (M8) grid connects reference voltage (VREF), the 8th NMOS pipe (M8) and the 9th NMOS pipe (M9) consist of two source followers, the output of the 8th NMOS pipe (M8) source electrode connects the positive input terminal of the error amplifier first order, namely a PMOS manages the grid of (M1), the output of the 9th NMOS pipe (M9) source electrode connects the negative input end of the error amplifier first order, the i.e. grid of the 2nd PMOS pipe (M2); The one PMOS pipe (M1) is the common source differential pair with the 2nd PMOS pipe (M2), and source electrode is connected to biasing tail current (Id); The drain electrode of the one PMOS pipe (M1) is connected with grid, drain electrode that the 3rd PMOS manages (M3), and the drain electrode of the 2nd PMOS pipe (M2) is connected with the drain electrode that the 4th PMOS manages (M4), and the 3rd PMOS pipe (M3), the 4th PMOS pipe (M4) grid share; The drain electrode of the 4th PMOS pipe (M4) is the output of first order error amplifier, be connected to the input of second level amplifier, namely the 5th NMOS manages the grid of (M5), the grid of the 5th NMOS pipe (M5) is connected with grid, drain electrode that the 6th PMOS manages (M6), and the grid of the 6th PMOS pipe (M6) is connected to the grid of the 7th PMOS pipe (M7) grid and the first power tube (MP); The drain electrode of the 7th PMOS pipe (M7) is connected with the grid of the second power tube (MC), drain electrode, and the grid of the second power tube (MC), drain electrode connect the drain electrode of the 4th PMOS pipe (M4) simultaneously; The second power tube (MC) is the frequency compensation pipe of a diode type of attachment; The drain electrode of the first power tube (MP) is the output terminal of linear voltage regulator, connects with the divider resistance series winding; Described divider resistance string is composed in series by the first resistance (R1), the second resistance (R2), the first power tube (MP) drain electrode is connected to first the first resistance (R1), again by the second resistance (R2) ground connection, the common terminal of the first resistance (R1) and the second resistance (R2) produces feedback voltage, be connected to the 9th NMOS pipe (M9) grid, form negative feedback loop; Described the 3rd PMOS pipe (M3) source electrode, the 4th PMOS pipe (M4) source electrode, the second power tube (MC) source electrode, the 5th NMOS manage (M5) source ground; Described the 8th NMOS pipe (M8) drain electrode, the 9th NMOS pipe (M9) drain electrode, the 6th PMOS pipe (M6) source electrode, the 7th PMOS pipe (M7) source electrode, the first power tube (MP) source electrode connect supply voltage (VDD).
2. the linear voltage regulator with dynamic compensation characteristic according to claim 1 is characterized in that, described the first power tube (MP) drain electrode namely connects load capacitance (CL) between the output terminal of linear voltage regulator and the ground, be load (I
L) voltage stabilizing is provided.
3. the linear voltage regulator with dynamic compensation characteristic according to claim 1 is characterized in that, described the 8th NMOS pipe (M8) and the 9th NMOS pipe (M9), and the strict maintenance of two pipe sizes and bias current equates, with the gate source voltage of realizing equating.
4. the linear voltage regulator with dynamic compensation characteristic according to claim 2 is characterized in that, described load capacitance (CL) adopts the form of the outer electric capacity of sheet to realize, or adopts mos capacitance realization on the sheet, realizes the function of voltage regulation filtering.
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106911315A (en) * | 2015-12-23 | 2017-06-30 | 爱思开海力士有限公司 | Differential amplifier circuit, voltage regulator and the semiconductor storage unit including it |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060170404A1 (en) * | 2005-01-28 | 2006-08-03 | Hafid Amrani | Standard CMOS low-noise high PSRR low drop-out regulator with new dynamic compensation |
| CN1848018A (en) * | 2005-04-15 | 2006-10-18 | 矽创电子股份有限公司 | Fast restoring low voltage drop linear voltage stabilizer |
| CN101957628A (en) * | 2009-07-17 | 2011-01-26 | 上海沙丘微电子有限公司 | Self-adaption zero-frequency compensation circuit in low-voltage difference linear voltage regulator |
| US20110018510A1 (en) * | 2009-07-21 | 2011-01-27 | Stmicroelectronics R&D (Shanghai) Co., Ltd. | Adaptive miller compensated voltage regulator |
| CN102566634A (en) * | 2010-12-13 | 2012-07-11 | 联芯科技有限公司 | Linear voltage stabilizing circuit |
| CN202372876U (en) * | 2011-12-20 | 2012-08-08 | 上海贝岭股份有限公司 | Low-dropout linear voltage regulator with frequency compensating function |
-
2012
- 2012-09-29 CN CN201210374909.4A patent/CN102880219B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060170404A1 (en) * | 2005-01-28 | 2006-08-03 | Hafid Amrani | Standard CMOS low-noise high PSRR low drop-out regulator with new dynamic compensation |
| CN1848018A (en) * | 2005-04-15 | 2006-10-18 | 矽创电子股份有限公司 | Fast restoring low voltage drop linear voltage stabilizer |
| CN101957628A (en) * | 2009-07-17 | 2011-01-26 | 上海沙丘微电子有限公司 | Self-adaption zero-frequency compensation circuit in low-voltage difference linear voltage regulator |
| US20110018510A1 (en) * | 2009-07-21 | 2011-01-27 | Stmicroelectronics R&D (Shanghai) Co., Ltd. | Adaptive miller compensated voltage regulator |
| CN102566634A (en) * | 2010-12-13 | 2012-07-11 | 联芯科技有限公司 | Linear voltage stabilizing circuit |
| CN202372876U (en) * | 2011-12-20 | 2012-08-08 | 上海贝岭股份有限公司 | Low-dropout linear voltage regulator with frequency compensating function |
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| CN106911315A (en) * | 2015-12-23 | 2017-06-30 | 爱思开海力士有限公司 | Differential amplifier circuit, voltage regulator and the semiconductor storage unit including it |
| CN113853562A (en) * | 2019-03-12 | 2021-12-28 | ams有限公司 | Voltage regulator, integrated circuit and voltage regulating method |
| US11886215B2 (en) | 2019-03-12 | 2024-01-30 | Ams Ag | Voltage regulator, integrated circuit and method for voltage regulation |
| CN110082584B (en) * | 2019-05-24 | 2024-01-30 | 深圳市思远半导体有限公司 | Low-voltage wide-bandwidth high-speed current sampling circuit |
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| CN112306130A (en) * | 2019-07-30 | 2021-02-02 | 意法半导体亚太私人有限公司 | Low Dropout (LDO) voltage regulator circuit |
| CN113342110A (en) * | 2021-06-21 | 2021-09-03 | 电子科技大学 | Error amplifier circuit with dynamic zero compensation |
| CN113342110B (en) * | 2021-06-21 | 2022-04-22 | 电子科技大学 | Error amplifier circuit with dynamic zero compensation |
| CN113641206A (en) * | 2021-10-15 | 2021-11-12 | 成都时识科技有限公司 | Integrated circuit with filtering function |
| CN113641206B (en) * | 2021-10-15 | 2021-12-28 | 成都时识科技有限公司 | Integrated circuit with filtering function |
| CN113970949B (en) * | 2021-12-27 | 2022-03-29 | 江苏长晶科技股份有限公司 | High-speed linear voltage stabilizer with quick response |
| CN113970949A (en) * | 2021-12-27 | 2022-01-25 | 江苏长晶科技股份有限公司 | High-speed linear voltage stabilizer with quick response |
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| CN115664408B (en) * | 2022-11-10 | 2023-11-21 | 江苏谷泰微电子有限公司 | Level shifter of unknown voltage domain |
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| CN117590890B (en) * | 2024-01-18 | 2024-04-09 | 江苏云途半导体有限公司 | Bidirectional rapid response method and circuit based on vehicle-mounted LDO |
| CN117631741A (en) * | 2024-01-25 | 2024-03-01 | 苏州锴威特半导体股份有限公司 | LDO circuit with current-limiting output |
| CN117631741B (en) * | 2024-01-25 | 2024-04-09 | 苏州锴威特半导体股份有限公司 | LDO circuit with current-limiting output |
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| CN102880219B (en) | 2014-04-16 |
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