CN107463196B - A kind of LDO circuit improving loop stability - Google Patents
A kind of LDO circuit improving loop stability Download PDFInfo
- Publication number
- CN107463196B CN107463196B CN201710668824.XA CN201710668824A CN107463196B CN 107463196 B CN107463196 B CN 107463196B CN 201710668824 A CN201710668824 A CN 201710668824A CN 107463196 B CN107463196 B CN 107463196B
- Authority
- CN
- China
- Prior art keywords
- circuit
- tube
- nmos tube
- grid
- drain electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
- Amplifiers (AREA)
Abstract
The present invention relates to integrated chip technology fields, more particularly to a kind of novel LDO circuit for improving loop stability, including reference voltage generating circuit and bias current generating circuit, the reference voltage generating circuit provides reference voltage for error amplifier circuit, the bias current generating circuit provides bias current for the error amplifier circuit, the output end of the error amplifier circuit connects secondary amplifier circuit, the secondary amplifier circuit connects auxiliary circuit, the output end of the secondary amplifier circuit connects power tube, the output end of the power tube connects electric resistance partial pressure feed circuit, load and external capacitor, the error amplifier circuit receives the feedback voltage of electric resistance partial pressure feed circuit.The present invention improves on the basis of conventional low difference linear constant voltage regulator, provides the loop stability of LDO circuit.
Description
Technical field
The present invention relates to integrated chip technology field more particularly to a kind of LDO circuits for improving loop stability.
Background technique
Consumer electronics product has become a part indispensable in people's daily life, and power management chip exists
Important duty is responsible in electronic equipment, the superiority and inferiority of performance has direct influence to the energy consumption of entire circuit.And power management
The type of chip is relatively more, and wherein linear voltage regulator, switching regulator (DC/DC), driving chip and Power Management Unit account for
According to more than half rivers and mountains.And in these main species, linear voltage regulator occupies the maximum market share again.Low pressure difference linearity
Voltage-stablizer, abbreviation LDO (low dropout voltage), due to its high conversion efficiency, small in size, low noise, outward element
Less, low-cost feature becomes the power management chip being most widely used at present.Traditional LDO circuit is in different loads electricity
Frequency compensated difficulty is larger when stream, and stability is poor.
Summary of the invention
Stability that the purpose of the present invention is to solve LDO circuits in the prior art in different load currents difference is asked
Topic provides a kind of LDO circuit for improving loop stability.
The present invention provides a kind of LDO circuits for improving loop stability, including reference voltage generating circuit and biased electrical
Generation circuit is flowed, the reference voltage generating circuit provides reference voltage for error amplifier circuit, and the bias current generates
Circuit provides bias current Ibias for the error amplifier circuit, and the output end of the error amplifier circuit connects secondary
Amplifier circuit, the secondary amplifier circuit connect auxiliary circuit, and the auxiliary circuit includes thermal-shutdown circuit and short circuit
Circuit is protected, the output end of the secondary amplifier circuit connects power tube, and the output end of the power tube connects electric resistance partial pressure
Feed circuit, load and external capacitor, the error amplifier circuit receive the feedback voltage of electric resistance partial pressure feed circuit.
Wherein, the bias current of the grid connection bias current generating circuit generation of the first PMOS tube, the second PMOS tube
Ibias, source electrode are all connected with supply voltage VIN, and the drain electrode of the first PMOS tube connects the drain electrode of the first NMOS tube and the second NMOS tube,
The reference voltage Vref that the grid connection reference voltage generating circuit of first NMOS tube generates, source electrode connect the leakage of third NMOS tube
Pole, grid and the 4th NMOS tube grid, second NMOS tube grid connection electric resistance partial pressure feed circuit generate feedback
Voltage Vfb, source electrode connect drain electrode, the drain electrode of the 5th NMOS tube and the grid of the 6th NMOS tube of the 4th NMOS tube；The third
The source electrode of PMOS connects supply voltage VIN, the grid of drain electrode the 5th NMOS tube of connection and the source electrode of the 4th PMOS tube；4th PMOS
The grounded drain of pipe, grid connect the source electrode of the 5th NMOS tube and one end of internal capacitance, the other end connection the of internal capacitance
The grid of three PMOS tube, the drain electrode of the second PMOS tube, the drain electrode of the 6th NMOS tube and power tube grid, the 3rd NMOS
The source grounding of pipe, the 4th NMOS tube and the 6th NMOS tube；The source electrode of the power tube connects supply voltage VIN, and drain electrode is
For the output end VOUT of LDO circuit, and one end of electric resistance partial pressure feed circuit and one end of external capacitor are connected, electric resistance partial pressure is anti-
The other end of current feed circuit and external capacitor is grounded, and the electric resistance partial pressure feed circuit is by concatenated first resistor and second resistance
It constitutes, the partial pressure between two resistance is feedback voltage Vfb.
A kind of LDO circuit improving loop stability provided by the present invention, efficiently solves LDO electricity in the prior art
The problem of road stability difference in different loads electric current, improves on the basis of conventional low difference linear constant voltage regulator, provides
The stability of LDO loop.
Detailed description of the invention
Fig. 1 is a kind of LDO circuit general structure schematic diagram for improving loop stability provided by the invention.
Fig. 2 is a kind of core circuit structural schematic diagram of LDO circuit for improving loop stability provided by the invention.
Specific embodiment
The present invention provides a kind of LDO circuits for improving loop stability, to make the purpose of the present invention, technical solution and excellent
Point is clearer, clear, and the present invention is described in more detail as follows in conjunction with drawings and embodiments.It should be appreciated that this place
The specific embodiment of description is only used to explain the present invention, is not intended to limit the present invention.
Figure of description 1 is a kind of LDO circuit general structure schematic diagram for improving loop stability provided by the invention.Such as
Shown in 1 figure, a kind of LDO circuit improving loop stability, including reference voltage generating circuit and bias current generating circuit, institute
It states reference voltage generating circuit and provides reference voltage Vref for error amplifier circuit, the bias current generating circuit is described
Error amplifier circuit provides bias current Ibias, and the output end of the error amplifier circuit connects secondary amplifier circuit,
The secondary amplifier circuit connects auxiliary circuit, and the auxiliary circuit includes thermal-shutdown circuit and short-circuit protection circuit, institute
State the output end connection electric resistance partial pressure feedback electricity of output end connection the power tube Mp, the power tube Mp of secondary amplifier circuit
Road, load and external capacitor CL, the error amplifier circuit receive the feedback voltage Vfb of electric resistance partial pressure feed circuit.
Figure of description 2 gives a kind of nuclear structure schematic diagram of the LDO circuit of raising loop stability of the invention
(since reference voltage generating circuit, bias current generating circuit, short-circuit protection circuit and current foldback circuit are not of the invention
Key point, and those skilled in the art can obtain from the prior art, therefore not do emphasis elaboration in the present embodiment),
Wherein, the bias current Ibias of the grid connection bias current generating circuit generation of the first PMOS tube P1, the second PMOS tube P2,
Source electrode is all connected with supply voltage VIN, and the drain electrode of the first PMOS tube P1 connects the drain electrode of the first NMOS tube M1 and the second NMOS tube M2,
The reference voltage Vref that the grid connection reference voltage generating circuit of first NMOS tube M1 generates, source electrode connect third NMOS tube M3
Drain electrode, grid and the 4th NMOS tube M4 grid, the second NMOS tube M2 grid connection electric resistance partial pressure feed circuit produce
Raw feedback voltage Vfb, source electrode connect the drain electrode of the 4th NMOS tube M4, the drain electrode of the 5th NMOS tube Mz and the 6th NMOS tube M6
Grid；The source electrode of 3rd PMOS connects supply voltage VIN, the grid and the 4th PMOS tube of the 5th NMOS tube Mz of drain electrode connection
The source electrode of P4；The grounded drain of 4th PMOS tube P4, grid connect the source electrode of the 5th NMOS tube Mz and one end of internal capacitance Cz,
The other end of internal capacitance Cz connects the grid of third PMOS tube P3, the drain electrode of the second PMOS tube P2, the leakage of the 6th NMOS tube M6
The grid of pole and power tube Mp, the source grounding of the third NMOS tube M3, the 4th NMOS tube M4 and the 6th NMOS tube M6；Institute
The source electrode connection supply voltage VIN of power tube Mp is stated, drain electrode is the output end VOUT of LDO circuit, and it is anti-to connect electric resistance partial pressure
The other end of one end of current feed circuit and one end of external capacitor CL, electric resistance partial pressure feed circuit and external capacitor CL are grounded, institute
It states electric resistance partial pressure feed circuit to be made of concatenated first resistor Rf1 and second resistance Rf2, the partial pressure between two resistance is as anti-
Feedthrough voltage Vfb.
In foregoing circuit, when the electric current that power tube Mp is flowed through in load current increase increases, the resistance of equivalent load
Reduce, output pole is larger, and the electric current of third PMOS tube P3 sampling also increases, and the drain terminal voltage of third PMOS tube P3 increases therewith
Greatly, the grid voltage of the 5th NMOS tube Mz rises, so the equivalent resistance of the 5th NMOS tube Mz reduces, the zero of compensation circuit generation
Point increases approximately equal with the pole that LDO is exported；When load current reduces, that is, when flowing through the electric current reduction of power tube Mp, etc.
It imitates load resistance to increase, output pole is smaller, and the electric current of the sampling of third PMOS tube P3 also reduces, the drain terminal of third PMOS tube P3
Voltage reduces, and the grid voltage decline of the 5th NMOS tube Mz, so the equivalent resistance of the 5th NMOS tube Mz increases, compensation circuit is produced
Raw zero point reduction is approximately equal with LDO output pole, so as to improve the stability of LDO loop.
It should be understood that the application of the present invention is not limited to the above for those of ordinary skills can
With improvement or transformation based on the above description, all these modifications and variations all should belong to the guarantor of appended claims of the present invention
Protect range.
Claims (1)
1. a kind of LDO circuit for improving loop stability, which is characterized in that miscarry including reference voltage generating circuit and biased electrical
Raw circuit, the reference voltage generating circuit provide reference voltage Vref for error amplifier circuit, and the bias current generates
Circuit provides bias current Ibias for the error amplifier circuit, and the output end of the error amplifier circuit connects secondary
Amplifier circuit, the secondary amplifier circuit connect auxiliary circuit, and the auxiliary circuit includes thermal-shutdown circuit and short circuit
Circuit is protected, the output end of the secondary amplifier circuit connects power tube, and the output end of the power tube connects electric resistance partial pressure
Feed circuit, load and external capacitor, the error amplifier circuit receive the feedback voltage Vfb of electric resistance partial pressure feed circuit；
Wherein, the bias current Ibias of the grid connection bias current generating circuit generation of the first PMOS tube, the second PMOS tube, source electrode
It is all connected with supply voltage VIN, the drain electrode of drain electrode connection the first NMOS tube and the second NMOS tube of the first PMOS tube, the first NMOS tube
The reference voltage Vref that generates of grid connection reference voltage generating circuit, source electrode connect the drain electrode of third NMOS tube, grid and
The grid of 4th NMOS tube, the feedback voltage Vfb that the grid connection electric resistance partial pressure feed circuit of second NMOS tube generates, source
Pole connects drain electrode, the drain electrode of the 5th NMOS tube and the grid of the 6th NMOS tube of the 4th NMOS tube；The source electrode of 3rd PMOS
Connect supply voltage VIN, the grid of drain electrode the 5th NMOS tube of connection and the source electrode of the 4th PMOS tube；The drain electrode of 4th PMOS tube connects
Ground, grid connect the source electrode of the 5th NMOS tube and one end of internal capacitance, the other end connection third PMOS tube of internal capacitance
Grid, the drain electrode of the second PMOS tube, the drain electrode of the 6th NMOS tube and power tube grid, the third NMOS tube, the 4th NMOS
The source grounding of pipe and the 6th NMOS tube；The source electrode of the power tube connects supply voltage VIN, and drain electrode is LDO circuit
Output end VOUT, and connect one end of electric resistance partial pressure feed circuit and one end of external capacitor, electric resistance partial pressure feed circuit and outer
The other end for connecing capacitor is grounded, and the electric resistance partial pressure feed circuit is made of concatenated first resistor and second resistance, two electricity
Partial pressure between resistance is feedback voltage Vfb.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710668824.XA CN107463196B (en) | 2017-08-24 | 2017-08-24 | A kind of LDO circuit improving loop stability |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710668824.XA CN107463196B (en) | 2017-08-24 | 2017-08-24 | A kind of LDO circuit improving loop stability |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107463196A CN107463196A (en) | 2017-12-12 |
| CN107463196B true CN107463196B (en) | 2019-04-26 |
Family
ID=60548529
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710668824.XA Active CN107463196B (en) | 2017-08-24 | 2017-08-24 | A kind of LDO circuit improving loop stability |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107463196B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111290462A (en) * | 2020-03-25 | 2020-06-16 | 上海洺太电子科技有限公司 | LDO (low dropout regulator) voltage stabilizer with high current and high power supply rejection ratio |
| CN114879792B (en) * | 2022-05-24 | 2024-04-19 | 中国人民解放军国防科技大学 | Double-loop low-dropout linear voltage regulator with turnover voltage follower structure |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3318161B2 (en) * | 1995-08-24 | 2002-08-26 | シャープ株式会社 | Low voltage operation type amplifier and optical pickup using the same |
| CN102323842B (en) * | 2011-05-13 | 2013-07-17 | 电子科技大学 | Band-gap voltage reference source for high-order temperature compensation |
| CN102385408B (en) * | 2011-09-21 | 2013-06-12 | 电子科技大学 | Low dropout linear voltage regulator |
| CN105138064A (en) * | 2015-08-04 | 2015-12-09 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | Low differential pressure linear voltage regulator circuit with high bandwidth high power supply ripple inhibition ratio |
-
2017
- 2017-08-24 CN CN201710668824.XA patent/CN107463196B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN107463196A (en) | 2017-12-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104460802B (en) | The low pressure difference linear voltage regulator of one self-adaptive current multiple circuit and this circuit integrated | |
| CN104407662B (en) | A kind of underloading transient state strengthens the low pressure difference linear voltage regulator of circuit and this circuit integrated | |
| CN102880219B (en) | Linear voltage regulator with dynamic compensation characteristic | |
| CN103066851B (en) | Control circuit for primary side flyback type converter | |
| CN102495656A (en) | Low dropout linear regulator | |
| CN107272808B (en) | A kind of LDO circuit applied to integrated chip | |
| CN107463196B (en) | A kind of LDO circuit improving loop stability | |
| CN202362691U (en) | Low dropout linear regulator | |
| CN104950976A (en) | Voltage stabilizing circuit based on slew rate increasing | |
| CN103592989A (en) | Low quiescent dissipation rapid transient response non-output capacitance LDO (low drop out regulator) circuit | |
| CN202533828U (en) | Linear voltage stabilizer with low voltage difference | |
| CN202103576U (en) | Switch converter and control circuit thereof | |
| CN109725673A (en) | A kind of fully integrated multi output stack low pressure difference linear voltage regulator | |
| CN109149944A (en) | A kind of on piece suitable for flyback converter integrates active negative pressure clamp circuit | |
| CN209132655U (en) | A kind of voltage regulator circuit | |
| CN101763134A (en) | Parallel voltage stabilizing circuit | |
| CN203014698U (en) | Constant current control circuit with high power factor | |
| CN203084588U (en) | Voltage stabilizer | |
| CN108762360A (en) | A kind of power transfer circuitry | |
| CN210985935U (en) | Ripple injection circuit for constant on-time control mode switching power supply | |
| CN107368139A (en) | Low-noise LDO (low dropout regulator) of integrated chip circuit | |
| CN108649798A (en) | A kind of high-power linear power supply and its control circuit | |
| CN206211841U (en) | A kind of DC D/C powers manager | |
| CN104820459A (en) | LDO circuit | |
| CN110320953A (en) | A kind of adjustable reference voltage source of output voltage |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20190326 Address after: 312500 Building A 1104, Wanfeng Plaza, Qixing Street, Xinchang County, Shaoxing City, Zhejiang Province Applicant after: Xinchang Liguo Machinery Co.,Ltd. Address before: 404300 No. 11 Xiangshan Second Road, Zhongzhou Town, Zhongxian County, Chongqing City, with No. 2 33-1 Applicant before: Peng Xiaoxiong |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20171212 Assignee: Jiaxing kopuno Machinery Technology Co.,Ltd. Assignor: Xinchang Liguo Machinery Co.,Ltd. Contract record no.: X2021330000234 Denomination of invention: LDO circuit for improving loop stability Granted publication date: 20190426 License type: Common License Record date: 20210903 |
|
| EC01 | Cancellation of recordation of patent licensing contract | ||
| EC01 | Cancellation of recordation of patent licensing contract |
Assignee: Jiaxing kopuno Machinery Technology Co.,Ltd. Assignor: Xinchang Liguo Machinery Co.,Ltd. Contract record no.: X2021330000234 Date of cancellation: 20221103 |