CN107463196A

CN107463196A - A kind of new LDO circuit for improving loop stability

Info

Publication number: CN107463196A
Application number: CN201710668824.XA
Authority: CN
Inventors: 彭枭雄
Original assignee: Individual
Current assignee: Xinchang Liguo Machinery Co ltd
Priority date: 2017-08-24
Filing date: 2017-08-24
Publication date: 2017-12-12
Anticipated expiration: 2037-08-24
Also published as: CN107463196B

Abstract

The present invention relates to integrated chip technology field, a kind of more particularly to new LDO circuit for improving loop stability, including reference voltage generating circuit and bias current generating circuit, the reference voltage generating circuit provides reference voltage for error amplifier circuit, the bias current generating circuit provides bias current for the error amplifier circuit, the output end of the error amplifier circuit connects secondary amplifier circuit, the secondary amplifier circuit connection auxiliary circuit, the output end connection power tube of the secondary amplifier circuit, the output end connection electric resistance partial pressure feedback circuit of the power tube, load and external capacitor, the error amplifier circuit receives the feedback voltage of electric resistance partial pressure feedback circuit.The present invention is improved on the basis of conventional low difference linear constant voltage regulator, there is provided the loop stability of LDO circuit.

Description

A kind of new LDO circuit for improving loop stability

Technical field

The present invention relates to integrated chip technology field, more particularly to a kind of new LDO electricity for improving loop stability Road.

Background technology

Consumer electronics product has become a part indispensable in people's daily life, and power management chip exists Important duty is responsible in electronic equipment, the quality of its performance has direct influence to the energy consumption of whole circuit.And power management The species of chip is relatively more, and wherein linear voltage regulator, switching regulator (DC/DC), driving chip and PMU account for According to more than half rivers and mountains.And in these main species, linear voltage regulator occupies the market share of maximum again.Low pressure difference linearity Voltage-stablizer, abbreviation LDO (low dropout voltage), due to its high conversion efficiency, small volume, low noise, outward element Less, low-cost feature, the power management chip being most widely used at present is turned into.Traditional LDO circuit is in different loads electricity Frequency compensated difficulty is larger during stream, and stability is poor.

The content of the invention

The invention aims to solve, LDO circuit stability in different load currents is poor in the prior art asks A kind of topic, there is provided new LDO circuit for improving loop stability.

The invention provides it is a kind of improve loop stability new LDO circuit, including reference voltage generating circuit and partially Current generating circuit is put, the reference voltage generating circuit provides reference voltage, the bias current for error amplifier circuit Generation circuit provides bias current Ibias, the output end connection of the error amplifier circuit for the error amplifier circuit Secondary amplifier circuit, the secondary amplifier circuit connection auxiliary circuit, the auxiliary circuit include thermal-shutdown circuit and Short-circuit protection circuit, the output end connection power tube of the secondary amplifier circuit, the output end connection resistance of the power tube Partial pressure feedback circuit, load and external capacitor, the error amplifier circuit receive the feedback voltage of electric resistance partial pressure feedback circuit.

Wherein, bias current caused by the grid connection bias current generating circuit of the first PMOS, the second PMOS Ibias, source electrode are all connected with supply voltage VIN, drain electrode the first NMOS tube of connection of the first PMOS and the drain electrode of the second NMOS tube, Reference voltage V ref caused by the grid connection reference voltage generating circuit of first NMOS tube, source electrode connect the leakage of the 3rd NMOS tube The grid of pole, grid and the 4th NMOS tube, feedback caused by the grid connection electric resistance partial pressure feedback circuit of second NMOS tube Voltage Vfb, source electrode connect drain electrode, the drain electrode of the 5th NMOS tube and the grid of the 6th NMOS tube of the 4th NMOS tube；Described 3rd PMOS source electrode connection supply voltage VIN, the grid of drain electrode the 5th NMOS tube of connection and the source electrode of the 4th PMOS；4th PMOS The grounded drain of pipe, grid connect the source electrode of the 5th NMOS tube and one end of internal capacitance, the other end connection the of internal capacitance The grid of three PMOSs, the drain electrode of the second PMOS, the grid of the drain electrode of the 6th NMOS tube and power tube, the 3rd NMOS The source grounding of pipe, the 4th NMOS tube and the 6th NMOS tube；The source electrode connection supply voltage VIN of the power tube, drain electrode are For the output end VOUT of LDO circuit, and one end of electric resistance partial pressure feedback circuit and one end of external capacitor are connected, electric resistance partial pressure is anti- The other end of current feed circuit and external capacitor is grounded, and the electric resistance partial pressure feedback circuit is by the first resistor and second resistance connected Form, the partial pressure between two resistance is feedback voltage Vfb.

A kind of new LDO circuit for improving loop stability provided by the present invention, is efficiently solved in the prior art LDO circuit the problem of stability difference, is improved in different loads electric current on the basis of conventional low difference linear constant voltage regulator, Provide the stability of LDO loops.

Brief description of the drawings

Fig. 1 is a kind of new LDO circuit general structure schematic diagram for improving loop stability provided by the invention.

Fig. 2 is a kind of core circuit structural representation of new LDO circuit for improving loop stability provided by the invention.

Embodiment

The invention provides a kind of new LDO circuit for improving loop stability, to make the purpose of the present invention, technical scheme And advantage is clearer, clear and definite, the present invention is described in more detail for the embodiment that develops simultaneously referring to the drawings.It should be appreciated that this The specific embodiment of place description is not intended to limit the present invention only to explain the present invention.

Figure of description 1 is a kind of new LDO circuit general structure signal for improving loop stability provided by the invention Figure.As shown in fig. 1, a kind of new LDO circuit for improving loop stability, including reference voltage generating circuit and biased electrical miscarriage Raw circuit, the reference voltage generating circuit provide reference voltage V ref for error amplifier circuit, and the bias current produces Circuit provides bias current Ibias for the error amplifier circuit, and the output end connection of the error amplifier circuit is secondary Amplifier circuit, the secondary amplifier circuit connection auxiliary circuit, the auxiliary circuit include thermal-shutdown circuit and short circuit Protection circuit, output end connection the power tube Mp, the power tube Mp of the secondary amplifier circuit output end connection resistance Partial pressure feedback circuit, load and external capacitor CL, the error amplifier circuit receive the feedback electricity of electric resistance partial pressure feedback circuit Press Vfb.

The core texture that Figure of description 2 gives a kind of new LDO circuit of raising loop stability of the present invention shows It is intended to (because reference voltage generating circuit, bias current generating circuit, short-circuit protection circuit and current foldback circuit are not this hairs Bright key point, and those skilled in the art can obtain from the prior art, therefore do not do emphasis in the present embodiment and explain State), wherein, the first PMOS P1, the second PMOS P2 grid connect bias current caused by bias current generating circuit Ibias, source electrode are all connected with supply voltage VIN, the first PMOS P1 drain electrode connection the first NMOS tube M1 and the second NMOS tube M2 Drain electrode, the first NMOS tube M1 grid connection reference voltage generating circuit caused by reference voltage V ref, source electrode connection the 3rd The grid of NMOS tube M3 drain electrode, grid and the 4th NMOS tube M4, the grid connection electric resistance partial pressure of the second NMOS tube M2 are anti- Feedback voltage Vfb caused by current feed circuit, source electrode connect the 4th NMOS tube M4 drain electrode, the 5th NMOS tube Mz drain electrode and the 6th NMOS tube M6 grid；3rd PMOS source electrode connection supply voltage VIN, drain electrode connection the 5th NMOS tube Mz grid and 4th PMOS P4 source electrode；4th PMOS P4 grounded drain, grid connect the 5th NMOS tube Mz source electrode and inside electricity Hold Cz one end, the internal capacitance Cz other end connects the drain electrode of the 3rd PMOS P3 grid, the second PMOS P2, the 6th NMOS tube M6 drain electrode and power tube Mp grid, the 3rd NMOS tube M3, the 4th NMOS tube M4 and the 6th NMOS tube M6's Source grounding；The source electrode connection supply voltage VIN of the power tube Mp, drain electrode is the output end VOUT of LDO circuit, and even One end of connecting resistance partial pressure feedback circuit and external capacitor CL one end, electric resistance partial pressure feedback circuit and external capacitor CL's is another End is grounded, and the electric resistance partial pressure feedback circuit is made up of the first resistor Rf1 and second resistance Rf2 to connect, between two resistance Partial pressure be feedback voltage Vfb.

In foregoing circuit, when power tube Mp electric current increase is flowed through in load current increase, the resistance of equivalent load Reduce, output limit is larger, and the electric current of the 3rd PMOS P3 samplings also increases, and the 3rd PMOS P3 drain terminal voltage increases therewith Greatly, the 5th NMOS tube Mz grid voltage rises, so the 5th NMOS tube Mz equivalent resistance reduces, zero caused by compensation circuit Point increase, and the limit approximately equal of LDO outputs；When load current reduces, that is, when flowing through power tube Mp electric current reduction, etc. Load resistance increase is imitated, output limit is smaller, and the electric current of the 3rd PMOS P3 sampling also reduces, the 3rd PMOS P3 drain terminal Voltage reduces, and the 5th NMOS tube Mz grid voltage declines, so the 5th NMOS tube Mz equivalent resistance increase, compensation circuit production Raw zero point reduces, and LDO output limit approximately equals, so as to improve the stability of LDO loops.

It should be appreciated that the application of the present invention is not limited to above-mentioned citing, for those of ordinary skills, can To be improved or converted according to the above description, all these modifications and variations should all belong to the guarantor of appended claims of the present invention Protect scope.

Claims

1. a kind of new LDO circuit for improving loop stability, it is characterised in that including reference voltage generating circuit and biased electrical Generation circuit is flowed, the reference voltage generating circuit provides reference voltage V ref, the bias current for error amplifier circuit Generation circuit provides bias current Ibias, the output end connection of the error amplifier circuit for the error amplifier circuit Secondary amplifier circuit, the secondary amplifier circuit connection auxiliary circuit, the auxiliary circuit include thermal-shutdown circuit and Short-circuit protection circuit, the output end connection power tube of the secondary amplifier circuit, the output end connection resistance of the power tube Partial pressure feedback circuit, load and external capacitor, the error amplifier circuit receive the feedback voltage of electric resistance partial pressure feedback circuit Vfb。

2. LDO circuit as claimed in claim 1, it is characterised in that wherein, the first PMOS, the grid of the second PMOS connect Bias current Ibias caused by bias current generating circuit is met, source electrode is all connected with supply voltage VIN, the drain electrode of the first PMOS Connect the drain electrode of the first NMOS tube and the second NMOS tube, base caused by the grid connection reference voltage generating circuit of the first NMOS tube Quasi- voltage Vref, source electrode connect the grid of the drain electrode of the 3rd NMOS tube, grid and the 4th NMOS tube, the grid of second NMOS tube Feedback voltage Vfb caused by pole connection electric resistance partial pressure feedback circuit, source electrode connect the drain electrode of the 4th NMOS tube, the 5th NMOS tube Drain electrode and the grid of the 6th NMOS tube；The source electrode connection supply voltage VIN of 3rd PMOS, drain electrode the 5th NMOS tube of connection The source electrode of grid and the 4th PMOS；The grounded drain of 4th PMOS, grid connect the source electrode and inside electricity of the 5th NMOS tube One end of appearance, the other end connection grid of the 3rd PMOS of internal capacitance, the drain electrode of the second PMOS, the leakage of the 6th NMOS tube Pole and the grid of power tube, the source grounding of the 3rd NMOS tube, the 4th NMOS tube and the 6th NMOS tube；The power tube Source electrode connection supply voltage VIN, drain electrode is the output end VOUT of LDO circuit, and connects the one of electric resistance partial pressure feedback circuit The other end of end and one end of external capacitor, electric resistance partial pressure feedback circuit and external capacitor is grounded, the electric resistance partial pressure feedback Circuit is made up of the first resistor and second resistance connected, and the partial pressure between two resistance is feedback voltage Vfb.