CN105138064A - Low differential pressure linear voltage regulator circuit with high bandwidth high power supply ripple inhibition ratio - Google Patents

Abstract

The invention discloses a low differential pressure linear voltage regulator circuit with high bandwidth high power supply ripple inhibition ratio; the circuit employs embedded power supply ripple feedforward technology to improve low and medium frequency PSR, employs embedded double-zero point compensation technology to introduce a pair of intermediate frequency complex poles to a PSR transmission function, thus improving low and medium frequency PSR, and realizing high PSR under a width frequency scope. The circuit is simple in structure, small in chip area, low in power consumption, and only needs 10ua static state current.

Description

A kind of low differential voltage linear voltage stabilizer circuit of high bandwidth high PSRR

Technical field

The invention belongs to power management chip design field, be specifically related to a kind of low differential voltage linear voltage stabilizer circuit of high bandwidth high PSRR.

Background technology

Low pressure difference linear voltage regulator is the class Important Circuit in power management chip, have that output ripple is little, circuit structure is simple, chip occupying area is little, low in energy consumption, be convenient to the advantages such as integrated without the need to inductance, be widely used in the field such as portable electric appts, wireless energy transfer system, as the next stage voltage stabilizer of the switching power circuits such as DC-DC, AC-DC, it can reduce output ripple to obtain more stable output voltage.As shown in Figure 1, comprise an error amplifier, a voltage buffer level, power tube, two feedback resistances and an output capacitance, it realizes the adjustment of output voltage by negative voltage feedback to traditional LDO structure.

Stable supply voltage for the mimic channel of noise-sensitive or radio circuit very important, therefore, the power supply ripple rejection ratio (PSR) of LDO is most important.Along with the fast development of integrated circuit, working frequency of chip is also more and more higher.In order to meet the more and more higher application requirement of frequency, need the LDO designing high bandwidth height PSR.

PSR for LDO improves problem, at present existing a lot of research.As far back as 2004, VishalGupta etc. proposed an impedance dividing potential drop model, and this model shows be input to the equiva lent impedance of output by increasing LDO or reduce output equivalent impedance and can improve PSR.According to this model, a lot of PSR strengthens technology and arises at the historic moment.As increased by increasing power tube storehouse the equiva lent impedance being input to output, this is actually the isolation strengthening input/output signal path, but this can increase the input and output pressure drop of LDO simultaneously, LDO conversion efficiency is greatly declined, also can increase chip area.And for example reduce output equivalent impedance by increase loop gain and loop bandwidth, but this needs the error amplifier designing high-gain high bandwidth, due to loop stability sex chromosome mosaicism, be difficult to realize high-gain and high bandwidth, and high bandwidth requirements is by increasing circuit quiescent dissipation simultaneously.In recent years, there is a kind of more effective PSR enhancing technology: power supply ripple feedovers.The core concept of this technology is that power supply ripple is fed forward to power tube grid, makes the small-signal pressure reduction between power tube grid source be ideally 0, thus suppresses input ripple to appear at LDO output terminal, reaches the object improving PSR.This method directly eliminates ripple for power supply ripple main path, structure is simple, low power dissipation design can be realized, and loop poles and zeros assignment is not affected substantially, therefore the LDO of a lot of high PSR have employed this technology, but the specific implementation of feedforward is different, and effect and the circuit overall performance of feedforward are also different.The simplest feed forward method is, with the MOSFET that diode connects, power supply ripple is fed forward to power tube grid, but this method due to the electric capacity at power tube grid place comparatively large, feedforward Bandwidth-Constrained system, so can only improve low frequency PSR.The proposition error amplifiers such as M.El-Nozahi realize feedforward path, structure as shown in Figure 2, this structure can improve medium and low frequency PSR simultaneously, the PSR of-56dB is still had under reaching 10MHz, but the feed forward method of this voltage mode needs an operational amplifier that feed-forward signal and feedback signal are added, circuit structure more complicated, consumes larger chip area, and needs the quiescent current of 50uA.

Summary of the invention

The object of the invention is to address the deficiencies of the prior art, provide the low differential voltage linear voltage stabilizer circuit of a kind of high PSR that can realize in broad frequency range, the low-power consumption high bandwidth high PSRR that low in energy consumption, area is little, the technical scheme of employing is as follows:

A low differential voltage linear voltage stabilizer circuit for high bandwidth high PSRR, comprises the load pipe M of error amplifier, diode-connected _h, filter capacitor C _h, PMOS transistor M ₁, PMOS transistor M ₂, PMOS transistor M ₃, power tube M _p, feedback resistance, PMOS transistor M _s, compensating resistance R _z, building-out capacitor C _z, output capacitance C _lwith pull-up resistor R _l, described error amplifier negative input termination reference voltage V _ref, positive input termination feedback voltage V _fb, output terminal and PMOS transistor M ₁grid electrical connection, described PMOS transistor M ₁source electrode respectively with PMOS transistor M ₂drain electrode, power tube M _pgrid and PMOS transistor M _sgrid electrical connection, described PMOS transistor M ₃drain electrode respectively with PMOS transistor M ₂grid and the load pipe M of diode-connected _hdrain electrode electrical connection, the load pipe M of described diode-connected _hsource ground, described feedback resistance, output capacitance C _lwith pull-up resistor R _lrespectively with power tube M _pdrain electrode and ground electrical connection, described compensating resistance R _zrespectively with power tube M _pdrain electrode and PMOS transistor M _sdrain electrode electrical connection, described building-out capacitor C _zrespectively with PMOS transistor M _sdrain electrode and error amplifier positive input terminal electrical connection, described PMOS transistor M ₃grid meet bias current V _bias, described PMOS transistor M _s, PMOS transistor M _p, PMOS transistor M ₂with PMOS transistor M ₃source electrode all connect input voltage, described filter capacitor C _hmeet input voltage and PMOS transistor M respectively ₂grid.

As preferably, described feedback resistance comprises the resistance R of series connection mutually _f1and R _f2.

As preferably, described transistor M ₁and M ₂size meet: when time, formula ${\mathrm{PSR}}_{ERFF}=\frac{v_{out}\left(s\right)}{v_{is}\left(s\right)}=\frac{1+g_{m,p}{r}_{ds,p}\[1-H\left(s\right)\]}{1+{\mathrm{\β}}_0{r}_{ds,p}\[A\left(s\right)g_{m,p}+\frac{1}{R_{f2}}\]+\frac{r_{ds,p}}{Z_L\left(s\right)}}$ Denominator be approximately zero, wherein g _m1for transistor M ₁mutual conductance, g _m2for transistor M ₂mutual conductance, r _{ds, p}for power tube M _pchannel resistance, g _m,pfor power tube M _pmutual conductance, for feedback factor, for power tube M _pthe small signal at grid place, C _hfor filter capacitor, g _m,hfor the load pipe M of diode-connected _hmutual conductance, the open-loop transmission function that A (s) is error amplifier, Z _ls equivalent output impedance that () is LDO, s is complex frequency.

As preferably, described transistor M _sbe of a size of M _p1/K.

As preferably, described error amplifier comprises nmos pass transistor M ₄, M ₅, M ₁₀, M ₁₁and M ₁₃, also comprise PMOS transistor M ₆, M ₇, M ₈, M ₉and M ₁₂, described transistor M ₄, M ₅, M ₁₀, M ₁₁and M ₁₃source grounding, described transistor M ₄drain electrode and M ₅grid all connect current source negative pole, described transistor M ₆, M ₇and M ₁₂source electrode and current source positive pole all meet input voltage V _in, described transistor M ₄grid and M ₅grid electrical connection, described transistor M ₅drain electrode respectively with transistor M ₆drain and gate, M ₇grid and M ₁₂grid electrical connection, described transistor M ₆grid also with M ₇grid electrical connection, described transistor M ₇drain electrode respectively with M ₈and M ₉source electrode electrical connection, described M ₈and M ₉source electrode be electrically connected mutually, described transistor M ₈grid connect reference voltage, drain electrode respectively with transistor M ₁₀drain electrode, grid and M ₁₁grid electrical connection, described M ₁₀grid also with M ₁₁grid electrical connection, described transistor M ₁₁drain electrode respectively with M ₉drain electrode and M ₁₃grid electrical connection, described transistor M ₁₃drain electrode and M ₁₂drain electrode electrical connection.

As preferably, described transistor M ₅and M ₆the long design of grid make circuit meet wherein, r _ds5for transistor M ₅channel resistance, g _m6for transistor M ₆mutual conductance.

In the present invention, mutual conductance unit is A/V, and the unit of impedance is Ω, and the unit of electric capacity is F.

Compared with prior art, beneficial effect of the present invention:

1, the present invention adopts Embedded power supply ripple feed-forward technique to improve medium and low frequency PSR, the buffer stage in Embedded power supply ripple feed forward circuit is multiplexing traditional structure, and comes to M with Hi-pass filter ₂be DC to be biased, substantially there is no additional static power consumption, also substantially do not increase chip area.

2, adopt Embedded pair of zero compensation technology, introduce a pair intermediate frequency complex pole to the transition function of PSR, improve medium-high frequency PSR.

3, the embedded power supply ripple feed-forward technique adopted does not have an impact to loop poles and zeros assignment substantially, reduces design difficulty, can be applicable in multiple LDO topological structure.

4, structure is simple, and chip area is little, low in energy consumption, only needs the quiescent current of 10uA.

Accompanying drawing explanation

Fig. 1 is traditional LDO structural representation;

Fig. 2 is the LDO structural representation that M.El-Nozahi proposes;

Fig. 3 is LDO structural representation of the present invention;

Fig. 4 is error amplifier circuit figure of the present invention;

Fig. 5 is the PSR simulation result figure of LDO of the present invention.

Embodiment

Below in conjunction with drawings and Examples, the present invention is described in further detail.

Embodiment: as shown in Figure 3, a kind of low differential voltage linear voltage stabilizer circuit of high bandwidth high PSRR, comprises the load pipe M of error amplifier, diode-connected _h, filter capacitor C _h, PMOS transistor M ₁, PMOS transistor M ₂, PMOS transistor M ₃, power tube M _p, feedback resistance, PMOS transistor M _s, compensating resistance R _z, building-out capacitor C _z, output capacitance C _lwith pull-up resistor R _l, described error amplifier negative input termination reference voltage V _ref, positive input termination feedback voltage V _fb, output terminal and PMOS transistor M ₁grid electrical connection, described PMOS transistor M ₁source electrode respectively with PMOS transistor M ₂drain electrode, power tube M _pgrid and PMOS transistor M _sgrid electrical connection, described PMOS transistor M ₃drain electrode respectively with PMOS transistor M ₂grid and the load pipe M of diode-connected _hdrain electrode electrical connection, the load pipe M of described diode-connected _hsource ground, described feedback resistance, output capacitance C _lwith pull-up resistor R _lrespectively with power tube M _pdrain electrode and ground electrical connection, described compensating resistance R _zrespectively with power tube M _pdrain electrode and PMOS transistor M _sdrain electrode electrical connection, described building-out capacitor C _zrespectively with PMOS transistor M _sdrain electrode and error amplifier positive input terminal electrical connection, described PMOS transistor M ₃grid meet bias current V _bias, described PMOS transistor M _s, PMOS transistor M _p, PMOS transistor M ₂with PMOS transistor M ₃source electrode all connect input voltage, described filter capacitor C _hmeet input voltage and PMOS transistor M respectively ₂grid.

Described feedback resistance comprises the resistance R of series connection mutually _f1and R _f2.

Leak amplifier tube M altogether ₁, altogether grid amplifier tube M ₂, offset M ₃, diode-connected load pipe M _hwith filter capacitor C _hform Embedded power supply ripple feed forward circuit, M ₁for the buffer stage of traditional LDO, for improving the driving force of error amplifier to power tube grid, and the non-dominant pole at power tube grid place is pushed away toward high frequency; M ₂for offset, be M ₁bias current is provided.

M ₁and M ₂perform the function of the feed-forward amplifier in Fig. 2: work as M simultaneously ₂grid voltage when being AC deposition, M ₂for cathode-input amplifier, power supply ripple signal is pressed certain gain feedforward to power tube grid; Due to M ₁for missing method altogether, at M ₁the equiva lent impedance at source electrode place is 1/g _m1, so be g from the low frequency small-signal gain being input to power tube grid _m2/ g _m1.

M ₁and M ₂also perform the function of the adder operational amplifier in Fig. 2: feed-forward signal and feedback signal are added at power tube grid place by current-mode simultaneously.

As can be known from Fig. 3, power supply ripple feed forward circuit is embedded in buffer stage, without the need to extra quiescent dissipation.

M ₃and M _hfor being M ₂there is provided quiescent biasing, simultaneously M ₃, M _hand C _hcomposition Hi-pass filter, makes M ₂grid voltage be AC deposition.In order to make the stop-band frequency of Hi-pass filter higher, only need very little electric capacity, saving chip area, does not significantly increase again the delay of this node.

Can obtain according to electric circuit knowledge, the transition function of whole Embedded power supply ripple feed forward circuit is:

$H\left(s\right)=\frac{v_{gp}}{v_{in}}\≈\frac{g_{m2}}{g_{m1}}\frac{1}{1+s\frac{C_h}{g_{mh}}}---\left(1\right)$

Under the condition of channel resistance considering the power tube under deep submicron process, the PSR transition function adding Embedded power supply ripple feed forward circuit is:

${\mathrm{PSR}}_{ERFF}=\frac{v_{out}\left(s\right)}{v_{in}\left(s\right)}=\frac{1+g_{m,p}{r}_{ds,p}\[1-H\left(s\right)\]}{1+{\mathrm{\β}}_0{r}_{ds,p}\[A\left(s\right)g_{m,p}+\frac{1}{R_{f2}}\]+\frac{r_{ds,p}}{Z_L\left(s\right)}}---\left(2\right)$

Wherein g _m1for transistor M ₁mutual conductance, g _m2for transistor M ₂mutual conductance, for feedback factor, the open-loop transmission function that A (s) is error amplifier, Z _ls () is equivalent output impedance.

Design transistor M ₁and M ₂size, make time, the denominator of formula (2) can be approximated to be zero, and namely low frequency PSR ideally can be infinitely small.

Known, compared with traditional structure, low frequency PSR of the present invention improves low frequency PSR after improvement is:

${\mathrm{PSR}}_{ERFF,DC}=\frac{1+g_{m,p}{r}_{ds,p}(1-\frac{g_{m2}}{g_{m1}})}{{\mathrm{\β}}_0{A}_0{g}_{m,p}{r}_{ds,p}}---\left(3\right)$

Power tube M _p, sampling pipe M _s, compensating resistance R _z, building-out capacitor C _z, feedback resistance R _f1and R _f2, output capacitance C _lform Embedded pair of zero compensation circuit.

M _pfor power tube, M _sfor sampling pipe, M _sbe used for the electric current of sampled power pipe.In the present embodiment, M _sbe of a size of M _p1/K, due to M _pand M _sgate source voltage equal, then flow through M _selectric current for flowing through M _pthe 1/K of electric current.M _ssampling obtains the electric current relevant to load current, then is injected in feedback resistive network by compensating resistance Rz and building-out capacitor Cz.R _f1and R _f2for feedback resistance, C _lfor output capacitance, C _lfor arranging main circuit limit to ensure loop stability, and high frequency ripple is coupling to ground.Known, the transition function of whole feedback network is:

$\mathrm{\β}\left(s\right)=\frac{v_{fb}}{v_{out}}\≈\frac{R_{f2}}{R_{f1}+R_{f2}}\frac{1+C_z{R}_{f1}s+\frac{C_L{C}_z{R}_{f1}{R}_z}{K}{s}^2}{1+{\mathrm{sC}}_z\frac{R_{f1}{R}_{f2}}{R_{f1}+R_{f2}}}---\left(4\right)$

From (4), feedback network introduces a pair zero point and a limit, and two zero compensation technology is embedded in feedback network.

Ignore high frequency zero pole point, the loop gain of whole circuit can be approximately:

$LG\left(s\right)\≈{\mathrm{\β}}_0{A}_0{g}_{m,p}{R}_L\frac{1+C_z{R}_{f1}s+\frac{C_L{C}_z{R}_{f1}{R}_z}{K}{s}^2}{(1+{\mathrm{sC}}_L{R}_L)(1+s\frac{C_{gp}}{g_{m1}})(1+{\mathrm{sC}}_z\frac{R_{f1}{R}_{f2}}{R_{f1}+R_{f2}})}---\left(5\right)$

The zero point that traditional structure often uses the equivalent series resistance of output capacitance (ESR) to introduce compensates, but ESR to be located at low frequency place zero point, need large ESR, this can reduce the coupling of high frequency ripple to ground on the one hand, affect high frequency PSR, transient response performance also can be made to be deteriorated on the other hand.The present embodiment does not adopt the method for ESR zero compensation to ensure loop stability, but by the output capacitance of a little ESR, compensates non-dominant pole with two zero points that feedback network is introduced.From formula (5), loop gain mainly contains two zero points and three limits, as long as design suitable K, C _z, R _ztwo zero points and two non-dominant poles are offseted, is namely equivalent to an one-pole system, enough phase margins can be obtained, ensure that loop stability, and widened loop unit gain frequency (UGF).The present embodiment embedded power supply ripple feed-forward technique used does not have an impact to loop poles and zeros assignment substantially, reduces design difficulty, can be applicable in multiple LDO topological structure.

Two zero compensation technology, indeed through the loop UGF of expansion LDO, reaches the object improving LDO medium-high frequency PSR.

The closed loop equivalent output impedance of the present embodiment is:

$Z_{out}\left(s\right)=\frac{R_L(R_{f1}+R_{f2})}{LG\left(s\right)(R_L+R_{f1}+R_{f2})}---\left(6\right)$

From formula (6), two zero points that feedback network is introduced have widened UGF, slow down the decline of medium-high frequency loop gain, also just slow down the rising of equivalent output impedance.According to impedance dividing potential drop model, less equivalent output impedance means less PSR, and traditional LDO medium-high frequency PSR variation is because equivalent output impedance increases after loop gain reduction.So two zero compensation technology can improve medium-high frequency PSR, and low frequency PSR is not affected.

The PSR transition function introducing two zero compensation technology is:

In the transition function of PSR, PSR can be made zero point to become large, and limit can make PSR reduce, and namely improves PSR.Can be seen by (7), two zero points of being introduced by feedback network create a pair complex pole in the transition function of PSR, and this makes PSR curve toward declining to complex pole.Design suitable K, C _z, R _zjust can set this position to complex pole, i.e. the flex point improved of PSR.In order to weigh PSR performance and loop stability, in the circuit of the present embodiment, the position of this complex pole is arranged on about 100kHz.

As shown in Figure 4, described error amplifier comprises nmos pass transistor M ₄, M ₅, M ₁₀, M ₁₁and M ₁₃, also comprise PMOS transistor M ₆, M ₇, M ₈, M ₉and M ₁₂, described transistor M ₄, M ₅, M ₁₀, M ₁₁and M ₁₃source grounding, described transistor M ₄drain electrode and M ₅grid all connect current source negative pole, described transistor M ₆, M ₇and M ₁₂source electrode and current source positive pole all meet input voltage V _in, described transistor M ₄grid and M ₅grid electrical connection, described transistor M ₅drain electrode respectively with transistor M ₆drain and gate, M ₇grid and M ₁₂grid electrical connection, described transistor M ₆grid also with M ₇grid electrical connection, described transistor M ₇drain electrode respectively with M ₈and M ₉source electrode electrical connection, described M ₈and M ₉source electrode be electrically connected mutually, described transistor M ₈grid connect reference voltage, drain electrode respectively with transistor M ₁₀drain electrode, grid and M ₁₁grid electrical connection, described M ₁₀grid also with M ₁₁grid electrical connection, described transistor M ₁₁drain electrode respectively with M ₉drain electrode and M ₁₃grid electrical connection, described transistor M ₁₃drain electrode and M ₁₂drain electrode electrical connection.

This error amplifier is traditional two-stage calculation amplifier structure, M ₄, M ₅, M ₆for offset, for operational amplifier provides current offset.M ₇, M ₈, M ₉, M ₁₀, M ₁₁for first stage amplifier, M ₇for tail current offset, M ₈and M ₉for first order Differential Input pipe, M ₁₀and M ₁₁for current mirror load.M ₁₂and M ₁₃for two-stage amplifier, M ₁₂for current offset tube, M ₁₃for second level common source amplifier tube.

Described transistor M ₅and M ₆the long design of grid make circuit meet wherein, r _ds5for transistor M ₅channel resistance, g _m6for transistor M ₆mutual conductance.

Claims (6)

1. a low differential voltage linear voltage stabilizer circuit for high bandwidth high PSRR, is characterized in that, comprises the load pipe M of error amplifier, diode-connected _h, filter capacitor C _h, PMOS transistor M ₁, PMOS transistor M ₂, PMOS transistor M ₃, power tube M _p, feedback resistance, PMOS transistor M _s, compensating resistance R _z, building-out capacitor C _z, output capacitance C _lwith pull-up resistor R _l, described error amplifier negative input termination reference voltage V _ref, positive input termination feedback voltage V _fb, output terminal and PMOS transistor M ₁grid electrical connection, described PMOS transistor M ₁source electrode respectively with PMOS transistor M ₂drain electrode, power tube M _pgrid and PMOS transistor M _sgrid electrical connection, described PMOS transistor M ₃drain electrode respectively with PMOS transistor M ₂grid and the load pipe M of diode-connected _hdrain electrode electrical connection, the load pipe M of described diode-connected _hsource ground, described feedback resistance, output capacitance C _lwith pull-up resistor R _lrespectively with power tube M _pdrain electrode and ground electrical connection, described compensating resistance R _zrespectively with power tube M _pdrain electrode and PMOS transistor M _sdrain electrode electrical connection, described building-out capacitor C _zrespectively with PMOS transistor M _sdrain electrode and error amplifier positive input terminal electrical connection, described PMOS transistor M ₃grid meet bias current V _bias, described PMOS transistor M _s, PMOS transistor M _p, PMOS transistor M ₂with PMOS transistor M ₃source electrode all connect input voltage, described filter capacitor C _hmeet input voltage and PMOS transistor M respectively ₂grid.

2. the low differential voltage linear voltage stabilizer circuit of a kind of high bandwidth high PSRR according to claim 1, is characterized in that, described feedback resistance comprises the resistance R of series connection mutually _f1and R _f2.

3. the low differential voltage linear voltage stabilizer circuit of a kind of high bandwidth high PSRR according to claim 1, is characterized in that, described transistor M ₁and M ₂size meet: when time, formula ${\mathrm{PSR}}_{ERFF}=\frac{v_{out}\left(s\right)}{v_{in}\left(s\right)}=\frac{1+g_{m,p}{r}_{ds,p}\[1-H\left(s\right)\]}{1+{\mathrm{\β}}_0{r}_{ds,p}\[A\left(s\right)g_{m,p}+\frac{1}{R_{f2}}\]+\frac{r_{ds,p}}{Z_L\left(s\right)}}$ Denominator be approximately zero, wherein g _m1for transistor M ₁mutual conductance, g _m2for transistor M ₂mutual conductance, r _{ds, p}for power tube M _pchannel resistance, g _m,pfor power tube M _pmutual conductance, for feedback factor, v _gpfor power tube M _pthe small signal at grid place, C _hfor filter capacitor, g _mhfor the load pipe M of diode-connected _hmutual conductance, the open-loop transmission function that A (s) is error amplifier, Z _ls equivalent output impedance that () is LDO.

4. the low differential voltage linear voltage stabilizer circuit of a kind of high bandwidth high PSRR according to claim 1, is characterized in that, described transistor M _sbe of a size of M _p1/K.

5. the low differential voltage linear voltage stabilizer circuit of a kind of high bandwidth high PSRR according to claim 1, it is characterized in that, described error amplifier comprises nmos pass transistor M ₄, M ₅, M ₁₀, M ₁₁and M ₁₃, also comprise PMOS transistor M ₆, M ₇, M ₈, M ₉and M ₁₂, described transistor M ₄, M ₅, M ₁₀, M ₁₁and M ₁₃source grounding, described transistor M ₄drain electrode and M ₅grid all connect current source negative pole, described transistor M ₆, M ₇and M ₁₂source electrode and current source positive pole all meet input voltage V _in, described transistor M ₄grid and M ₅grid electrical connection, described transistor M ₅drain electrode respectively with transistor M ₆drain and gate, M ₇grid and M ₁₂grid electrical connection, described transistor M ₆grid also with M ₇grid electrical connection, described transistor M ₇drain electrode respectively with M ₈and M ₉source electrode electrical connection, described M ₈and M ₉source electrode be electrically connected mutually, described transistor M ₈grid connect reference voltage, drain electrode respectively with transistor M ₁₀drain electrode, grid and M ₁₁grid electrical connection, described M ₁₀grid also with M ₁₁grid electrical connection, described transistor M ₁₁drain electrode respectively with M ₉drain electrode and M ₁₃grid electrical connection, described transistor M ₁₃drain electrode and M ₁₂drain electrode electrical connection.

6. the low differential voltage linear voltage stabilizer circuit of a kind of high bandwidth high PSRR according to claim 1, is characterized in that, described transistor M ₅and M ₆the long design of grid make circuit meet wherein, r _ds5for transistor M ₅channel resistance, g _m6for transistor M ₆mutual conductance.