CN105138064A - Low differential pressure linear voltage regulator circuit with high bandwidth high power supply ripple inhibition ratio - Google Patents

Abstract

The invention discloses a low-dropout linear voltage regulator circuit with high bandwidth and high power supply ripple rejection ratio. The embedded power supply ripple feedforward technology is used to improve the medium and low frequency PSR. The transfer function introduces a pair of mid-frequency complex poles to improve the mid-high frequency PSR, thereby realizing high PSR in a wide frequency range. The circuit structure of the invention is simple, the chip area is small, the power consumption is low, and only 10uA of static current is needed.

Description

A Low Dropout Linear Regulator Circuit with High Bandwidth and High Power Supply Ripple Rejection Ratio

technical field

The invention belongs to the technical field of power supply management chip design, in particular to a low-dropout linear voltage regulator circuit with high bandwidth and high power supply ripple rejection ratio.

Background technique

Low-dropout linear regulator is an important circuit in power management chips. It has the advantages of small output ripple, simple circuit structure, small chip area, low power consumption, and easy integration without inductors. It is widely used in portable electronic devices. , wireless energy transmission systems and other fields, as a next-level voltage regulator of DC-DC, AC-DC and other switching power supply circuits, it can reduce the output ripple to obtain a more stable output voltage. The traditional LDO structure is shown in Figure 1, including an error amplifier, a voltage buffer stage, a power transistor, two feedback resistors and an output capacitor, which adjust the output voltage through voltage negative feedback.

A stable power supply voltage is extremely important for noise-sensitive analog circuits or RF circuits, therefore, the power supply ripple rejection ratio (PSR) of the LDO is very important. With the rapid development of integrated circuits, the operating frequency of chips is also getting higher and higher. In order to meet the application requirements of higher and higher frequencies, it is necessary to design an LDO with high bandwidth and high PSR.

There have been many studies on the improvement of PSR of LDO. As early as 2004, VishalGupta et al. proposed an impedance divider model, which showed that PSR can be improved by increasing the equivalent impedance from LDO input to output or reducing the output equivalent impedance. According to this model, many PSR enhancement techniques came into being. For example, increasing the equivalent impedance from input to output by increasing the power tube stack, which actually strengthens the isolation of the input and output signal paths, but at the same time will increase the input and output voltage drop of the LDO, which will greatly reduce the conversion efficiency of the LDO. Will increase the chip area. Another example is to reduce the output equivalent impedance by increasing the loop gain and loop bandwidth, but this requires the design of a high-gain and high-bandwidth error amplifier. Due to loop stability issues, it is difficult to achieve high gain and high bandwidth at the same time, and high Bandwidth requirements will increase the static power consumption of the circuit. In recent years, a more effective PSR enhancement technique has emerged: power supply ripple feedforward. The core idea of this technology is to feed forward the power supply ripple to the grid of the power tube, so that the small signal voltage difference between the grid and source of the power tube is ideally 0, thereby suppressing the input ripple from appearing at the output of the LDO and improving Purpose of PSRs. This method directly targets the main path of the power supply ripple to eliminate the ripple. It has a simple structure, can realize low power consumption design, and basically has no effect on the distribution of poles and zeros of the loop. Therefore, many high-PSR LDOs use this technology, but The specific implementation of feedforward is different, and the effect of feedforward and the overall performance of the circuit are also different. The simplest feed-forward method is to use a diode-connected MOSFET to feed the power supply ripple to the gate of the power tube, but this method can only improve the low frequency due to the large capacitance at the gate of the power tube and the limited feed-forward bandwidth. PSR. M.El-Nozahi proposed to use the error amplifier to realize the feed-forward path. The structure is shown in Figure 2. This structure can improve the PSR at the middle and low frequencies at the same time, and can still achieve a PSR of -56dB at 10MHz. However, the front of this voltage mode The feed-forward method requires an operational amplifier that adds the feed-forward signal and the feedback signal. The circuit structure is relatively complex, consumes a large chip area, and requires a quiescent current of 50uA.

Contents of the invention

The purpose of the present invention is to solve the defects of the prior art, to provide a low dropout linear regulator capable of realizing high PSR in a wide frequency band, low power consumption, small area, low power consumption, high bandwidth and high power supply ripple rejection ratio The circuit adopts the following technical scheme:

A low-dropout linear voltage regulator circuit with high bandwidth and high power supply ripple rejection ratio, including an error amplifier, a diode-connected load transistor M _h , a filter capacitor C _h , a PMOS transistor M ₁ , a PMOS transistor M ₂ , and a PMOS transistor M _3. Power tube M _P , feedback resistor, PMOS transistor M _s , compensation resistor R _z , compensation capacitor C _z , output capacitor C _L and load resistor R _L , the negative input terminal of the error amplifier is connected to the reference voltage V _ref , and the positive input The terminal is connected to the feedback voltage V _fb , the output terminal is electrically connected to the gate _of the PMOS transistor M1, and the source _of the PMOS transistor M1 is respectively connected to the drain of the PMOS transistor _M2 , the gate of the power transistor MP and the _PMOS transistor M The gate of _s is electrically connected, and the drain of the PMOS transistor M3 is electrically connected with the gate of the PMOS transistor _M2 and the drain _of the diode-connected load tube M _h respectively, and the diode-connected load tube M _h The source of the power transistor is grounded, the feedback resistor, the output capacitor C _L and the load resistor R _L are electrically connected to the drain of the power transistor _MP and ground respectively, and the compensation resistor R _z is connected to the drain of the power transistor MP and the _PMOS respectively. The drain of the transistor M _s is electrically connected, the compensation capacitor C _z is electrically connected to the drain of the PMOS transistor M _s and the positive input terminal of the error amplifier respectively, the gate of the PMOS transistor M ₃ is connected to the bias current V _bias , The sources of the PMOS transistor M _s , the _PMOS transistor MP , the PMOS transistor M ₂ and the PMOS transistor M ₃ are all connected to the input voltage, and the filter capacitor C _h is respectively connected to the input voltage and the gate of the PMOS transistor M ₂ .

Preferably, the feedback resistor includes resistors R _f1 and R _f2 connected in series.

Preferably, the size _of the transistors M1 and _M2 satisfies: when When, formula ${\mathrm{PSR}}_{\mathrm{E.}Rff}=\frac{v_{out}\left(\mathrm{the\; s}\right)}{v_{i\mathrm{the\; s}}\left(\mathrm{the\; s}\right)}=\frac{1+g_{m,p}{r}_{d\mathrm{the\; s},p}\[1-h\left(\mathrm{the\; s}\right)\]}{1+{\mathrm{\β}}_0{r}_{d\mathrm{the\; s},p}\[A\left(\mathrm{the\; s}\right)g_{m,p}+\frac{1}{R_{f2}}\]+\frac{r_{d\mathrm{the\; s},p}}{Z_L\left(\mathrm{the\; s}\right)}}$ The denominator of is approximately zero, where g _m1 is the transconductance of transistor M ₁ , g _m2 is the transconductance of transistor M ₂ , _rds,p is the channel resistance of power transistor M _p , and g _m,p is the power transistor M _p the transconductance, is the feedback coefficient, is the small signal voltage at the gate of the power transistor M _p , C _h is the filter capacitor, g _m,h is the transconductance of the diode-connected load tube M _h , A(s) is the open-loop transfer function of the error amplifier, Z _L (s) is the equivalent output impedance of the LDO, and s is the complex frequency.

Preferably, the size of the transistor M _s is 1/ _K of MP.

Preferably, the error amplifier includes NMOS transistors M ₄ , M ₅ , M ₁₀ , M ₁₁ and M ₁₃ , and also includes PMOS transistors M ₆ , M ₇ , M ₈ , M ₉ and M ₁₂ , and the transistors M ₄ , The sources of M ₅ , M ₁₀ , M ₁₁ and M ₁₃ are all grounded, the drains of the transistor M ₄ and the gate of M ₅ are connected to the negative pole of the current source, and the sources of the transistors M ₆ , M ₇ and M ₁₂ Pole and the positive pole of the current source are both connected to the input voltage _Vin , the gate of the transistor M4 is electrically connected to the gate of the _M5 , and the drain of the transistor _M5 is respectively connected to the drain and the _gate of the transistor _M6 , M ₇ gate is electrically connected to the gate of M12, the gate _of the transistor _M6 is also electrically connected to the gate of _M7 , and the drain of the transistor _M7 is electrically connected to the source electrodes of _M8 and _M9 respectively connected, the sources of the _M8 and _M9 are electrically connected to each other, the gate of the transistor _M8 is connected to the reference voltage, and the drain is electrically connected to the drain and the gate of the transistor _M10 and the gate of the _M11 respectively, The gate of the M ₁₀ is also electrically connected to the gate of the M ₁₁ , the drain of the transistor M ₁₁ is respectively electrically connected to the drain of the M ₉ and the gate of the M 13, and the drain of the transistor M ₁₃ is electrically connected to the gate of the M _{13 The} drain of M12 is electrically connected.

As a preference, the gate lengths of the transistors _M5 and _M6 are designed so that the circuit satisfies Among them, _rds5 is the channel resistance of transistor M5, and _gm6 is the _{transconductance} of transistor _M6 .

In the present invention, the unit of transconductance is A/V, the unit of impedance is Ω, and the unit of capacitance is F.

Compared with prior art, the beneficial effect of the present invention:

1. The present invention adopts the embedded power supply ripple feedforward technology to improve the medium and low frequency PSR. The embedded power supply ripple feedforward circuit reuses the buffer stage in the traditional structure, and uses a high-pass filter to do DC for _M2 Bias, basically no additional static power consumption, and basically no increase in chip area.

2. Using embedded double zero point compensation technology, a pair of intermediate frequency complex poles are introduced into the PSR transfer function, which improves the medium and high frequency PSR.

3. The embedded power supply ripple feed-forward technology basically does not affect the zero-pole distribution of the loop, which reduces the difficulty of design and can be applied to various LDO topologies.

4. The structure is simple, the chip area is small, the power consumption is low, and only quiescent current of 10uA is required.

Description of drawings

Figure 1 is a schematic diagram of a traditional LDO structure;

Figure 2 is a schematic diagram of the LDO structure proposed by M.El-Nozahi;

Fig. 3 is the structural representation of LDO of the present invention;

Fig. 4 is error amplifier circuit diagram of the present invention;

Fig. 5 is a graph of the PSR simulation result of the LDO of the present invention.

Detailed ways

The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments.

Embodiment: As shown in FIG. 3 , a low-dropout linear voltage regulator circuit with high bandwidth and high power supply ripple rejection ratio includes an error amplifier, a diode-connected load transistor M _h , a filter capacitor C _h , and a PMOS transistor M ₁ , PMOS transistor M ₂ , PMOS transistor M ₃ , power transistor M _P , feedback resistor, PMOS transistor M _s , compensation resistor R _z , compensation capacitor C _z , output capacitor C _L and load resistor R _L , the negative input of the error amplifier The terminal is connected to the reference voltage V _ref , the positive input terminal is connected to the feedback voltage V _fb , the output terminal is electrically connected to the gate of the PMOS transistor M ₁ , the source of the PMOS transistor M ₁ is respectively connected to the drain of the PMOS transistor M ₂ and the power transistor The gate of MP is electrically connected to the gate of the _PMOS transistor M _s , and the drain of the PMOS transistor M ₃ is electrically connected to the gate of the PMOS transistor M ₂ and the drain of the diode-connected load transistor M _h respectively, so The source of the load tube M _h in the diode connection method is grounded, the feedback resistor, the output capacitor C _L and the load resistor R _L are electrically connected to the drain of the power tube _MP and the ground respectively, and the compensation resistor R _z is connected to the ground respectively. The drain of the power transistor M _P is electrically connected to the drain of the PMOS transistor M _s , the compensation capacitor C _z is electrically connected to the drain of the PMOS transistor M _s and the positive input terminal of the error amplifier, respectively, and the PMOS transistor M ₃ The gate is connected to the bias current V _bias , the sources of the PMOS transistor M _s , the _PMOS transistor MP , the PMOS transistor M ₂ and the PMOS transistor M ₃ are all connected to the input voltage, and the filter capacitor C _h is connected to the input voltage and the PMOS transistor respectively. Gate of transistor _M2 .

The feedback resistors include resistors R _f1 and R _f2 connected in series.

Common drain amplifier tube M ₁ , common grid amplifier tube M ₂ , bias tube M ₃ , diode-connected load tube M _h and filter capacitor C _h form an embedded power supply ripple feedforward circuit, and M ₁ is the traditional LDO The buffer stage is used to improve the driving ability of the error amplifier to the gate of the power tube, and push the non-dominant pole at the gate of the power tube to high frequency; _M2 is _a bias tube, which provides bias current for M1.

M ₁ and M ₂ perform the function of the feedforward amplifier in Figure 2 at the same time: when the gate voltage of M ₂ is AC ground, M ₂ is a common grid amplifier, which feeds the power supply ripple signal to the power tube with a certain gain Gate: Since M ₁ is common-drain connection, the equivalent impedance at the source of M ₁ is 1/g _m1 , so the low-frequency small signal gain from input to power tube gate is g _m2 /g _m1 .

M ₁ and M ₂ also perform the function of the adding operational amplifier in Figure 2 at the same time: the feedforward signal and the feedback signal are summed at the gate of the power tube through the current mode.

It can be seen from Figure 3 that the power supply ripple feedforward circuit is embedded in the buffer stage without additional static power consumption.

M ₃ and M _h are used to provide static bias for M ₂ , while M ₃ , M _h and C _h form a high-pass filter, so that the gate voltage of M ₂ is AC ground. In order to make the stopband frequency of the high-pass filter higher, only a small capacitor is needed, saving chip area without significantly increasing the delay of this node.

According to circuit knowledge, the transfer function of the entire embedded power supply ripple feedforward circuit is:

$\mathrm{<span\; class="notranslate">\; h</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; p</span>}}}{{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}}}<span\; class="notranslate">\; \&ap;</span>\frac{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; h</span>}}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; h</span>}}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

Under the condition of considering the channel resistance of the power tube in the deep submicron process, the PSR transfer function of the embedded power supply ripple feedforward circuit is:

${\mathrm{<span\; class="notranslate">\; PSR</span>}}_{\mathrm{<span\; class="notranslate">\; E.</span>}\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; f</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; t</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; p</span>}}{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; p</span>}}<span\; class="notranslate">\; \&lsqb;</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; h</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&rsqb;</span>}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; p</span>}}<span\; class="notranslate">\; \&lsqb;</span>\mathrm{<span\; class="notranslate">\; A</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; p</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; \&rsqb;</span><span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; p</span>}}}{{\mathrm{<span\; class="notranslate">\; Z</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

where _gm1 is the transconductance _of transistor M1, _gm2 is the transconductance of transistor _M2 , is the feedback coefficient, A(s) is the open-loop transfer function of the error amplifier, and Z _L (s) is the equivalent output impedance.

Design the dimensions _of transistors M1 and _M2 such that , the denominator of formula (2) can be approximately zero, that is, the low-frequency PSR can be infinitely small under ideal conditions.

As can be seen, compared with the traditional structure, the low-frequency PSR of the present invention has improved The improved low frequency PSR is:

${\mathrm{<span\; class="notranslate">\; PSR</span>}}_{\mathrm{<span\; class="notranslate">\; E.</span>}\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; D.</span>}\mathrm{<span\; class="notranslate">\; C</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; p</span>}}{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; p</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; p</span>}}{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; p</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

Power tube M _P , sampling tube M _S , compensation resistor R _Z , compensation capacitor C _Z , feedback resistors R _f1 and R _f2 , and output capacitor C _L form an embedded double zero point compensation circuit.

M _P is the power tube, _{MS is the sampling tube, and M S is} used to sample the current of the power tube. In this embodiment, the size of _MS is 1/ _K of _MP , and since the gate-source voltages of _MP and MS are equal, the current flowing through _MS is 1/ _K of the current flowing through MP. M _S samples the current related to the load current, and then injects it into the feedback resistor network through the compensation resistor Rz and the compensation capacitor Cz. R _f1 and R _f2 are the feedback resistors, _CL is the output capacitor, and _CL is used to set the main pole of the circuit to ensure the stability of the loop and couple the high-frequency ripple to the ground. It can be seen that the transfer function of the entire feedback network is:

$\mathrm{<span\; class="notranslate">\; \&beta;</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; b</span>}}}{{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; t</span>}}}<span\; class="notranslate">\; \&ap;</span>\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}\frac{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; z</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; z</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; z</span>}}}{\mathrm{<span\; class="notranslate">\; K</span>}}{\mathrm{<span\; class="notranslate">\; the\; s</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; sC</span>}}_{\mathrm{<span\; class="notranslate">\; z</span>}}\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

From (4) we can see that the feedback network introduces a pair of zeros and a pole, and the double zero compensation technology is embedded in the feedback network.

Ignoring the high-frequency pole-zero, the loop gain of the entire circuit can be approximated as:

$\mathrm{<span\; class="notranslate">\; L</span>}\mathrm{<span\; class="notranslate">\; G</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&ap;</span>{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; p</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}\frac{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; z</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; z</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; z</span>}}}{\mathrm{<span\; class="notranslate">\; K</span>}}{\mathrm{<span\; class="notranslate">\; the\; s</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; sC</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; p</span>}}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; sC</span>}}_{\mathrm{<span\; class="notranslate">\; z</span>}}\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; )</span>$

The traditional structure often uses the zero point introduced by the equivalent series resistance (ESR) of the output capacitor as compensation, but to set the ESR zero point at low frequency, a large ESR is required, which will reduce the coupling of high frequency ripple to ground. Affecting high-frequency PSR, on the other hand, will also make transient response performance worse. In this embodiment, the method of ESR zero point compensation is not used to ensure the stability of the loop, but an output capacitor with a small ESR is used to compensate the non-dominant poles with the double zero points introduced by the feedback network. It can be seen from formula (5) that the loop gain mainly has two zeros and three poles, as long as K, C _Z , R _Z are designed properly so that the two zeros and two non-dominant poles cancel each other out, it is equivalent to a single pole system, sufficient phase margin can be obtained, the loop is stable, and the loop unity gain frequency (UGF) is widened. The embedded power supply ripple feed-forward technology used in this embodiment basically does not affect the zero-pole distribution of the loop, which reduces the design difficulty and can be applied to various LDO topologies.

The double zero point compensation technology actually achieves the purpose of improving the medium and high frequency PSR of the LDO by expanding the loop UGF of the LDO.

The closed-loop equivalent output impedance of this embodiment is:

${\mathrm{<span\; class="notranslate">\; Z</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; t</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; L</span>}\mathrm{<span\; class="notranslate">\; G</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; )</span>$

It can be seen from formula (6) that the double zero points introduced by the feedback network widen the UGF, slow down the decline of the mid-high frequency loop gain, and slow down the rise of the equivalent output impedance. According to the impedance divider model, the smaller the equivalent output impedance means the smaller the PSR, and the deterioration of the high-frequency PSR in the traditional LDO is because the equivalent output impedance increases after the loop gain is reduced. Therefore, the double zero point compensation technology can improve the medium and high frequency PSR, and has no effect on the low frequency PSR.

The PSR transfer function of introducing double zero point compensation technology is:

In the transfer function of PSR, the zero point will make the PSR larger, and the pole will make the PSR smaller, that is, improve the PSR. It can be seen from (7) that the double zeros introduced by the feedback network produce a pair of complex poles in the transfer function of the PSR, and this pair of complex poles makes the PSR curve descend. Designing appropriate K, C _Z , and R _Z can set the position of the pair of complex poles, that is, the inflection point of PSR improvement. In order to balance PSR performance and loop stability, the position of the complex pole in the circuit of this embodiment is set at about 100 kHz.

As shown in FIG. 4 , the error amplifier includes NMOS transistors M ₄ , M ₅ , M ₁₀ , M ₁₁ and M ₁₃ , and also includes PMOS transistors M ₆ , M ₇ , M ₈ , M ₉ and M ₁₂ , and the transistors The sources of M ₄ , M ₅ , M ₁₀ , M ₁₁ and M ₁₃ are all grounded, the drains of the transistor M ₄ and the gates of M ₅ are connected to the negative pole of the current source, and the transistors M ₆ , M ₇ and M _The source electrode of I2 and the positive electrode of the current source are both connected to the input voltage V _in , the gate of the transistor _M4 is electrically connected to the gate of the _M5 , and the drain of the transistor _M5 is connected to the drain and gate of the transistor _M6 respectively. pole, the gate _{of M7} and the gate of M12 are electrically connected, the gate of the transistor _M6 is also electrically connected with the gate of _M7 , and the drain of the transistor _M7 is respectively connected with the gates of _M8 and _M9 The sources are electrically connected, the sources of the _M8 and _M9 are electrically connected to each other, the gate of the transistor _M8 is connected to the reference voltage, and the drain is respectively connected to the drain and the gate of the transistor _M10 and the gate of the _{M11 The} gate of the M10 is also electrically connected to the gate of the _M11 , the drain of the transistor _M11 is respectively electrically connected to the drain of the _M9 and the gate of the _M13 , and the gate of the transistor _M13 The drain is electrically connected to the drain of M ₁₂ .

The error amplifier is a traditional two-stage operational amplifier structure, and M ₄ , M ₅ , and M ₆ are bias tubes that provide current bias for the operational amplifier. M ₇ , M ₈ , M ₉ , M ₁₀ , and M ₁₁ are first-stage amplifiers, M ₇ is a tail current bias tube, M ₈ and M ₉ are first-stage differential input tubes, and M ₁₀ and M ₁₁ are current mirror loads . M ₁₂ and M ₁₃ are two-stage amplifiers, M ₁₂ is a current bias tube, and M ₁₃ is a second-stage common-source amplifier tube.

The gate length design of the transistors _M5 and _M6 makes the circuit satisfy Among them, _rds5 is the channel resistance of transistor M5, and _gm6 is the _{transconductance} of transistor _M6 .

Claims (6)

1. a low differential voltage linear voltage stabilizer circuit for high bandwidth high PSRR, is characterized in that, comprises the load pipe M of error amplifier, diode-connected _h, filter capacitor C _h, PMOS transistor M ₁, PMOS transistor M ₂, PMOS transistor M ₃, power tube M _p, feedback resistance, PMOS transistor M _s, compensating resistance R _z, building-out capacitor C _z, output capacitance C _lwith pull-up resistor R _l, described error amplifier negative input termination reference voltage V _ref, positive input termination feedback voltage V _fb, output terminal and PMOS transistor M ₁grid electrical connection, described PMOS transistor M ₁source electrode respectively with PMOS transistor M ₂drain electrode, power tube M _pgrid and PMOS transistor M _sgrid electrical connection, described PMOS transistor M ₃drain electrode respectively with PMOS transistor M ₂grid and the load pipe M of diode-connected _hdrain electrode electrical connection, the load pipe M of described diode-connected _hsource ground, described feedback resistance, output capacitance C _lwith pull-up resistor R _lrespectively with power tube M _pdrain electrode and ground electrical connection, described compensating resistance R _zrespectively with power tube M _pdrain electrode and PMOS transistor M _sdrain electrode electrical connection, described building-out capacitor C _zrespectively with PMOS transistor M _sdrain electrode and error amplifier positive input terminal electrical connection, described PMOS transistor M ₃grid meet bias current V _bias, described PMOS transistor M _s, PMOS transistor M _p, PMOS transistor M ₂with PMOS transistor M ₃source electrode all connect input voltage, described filter capacitor C _hmeet input voltage and PMOS transistor M respectively ₂grid.

2. the low differential voltage linear voltage stabilizer circuit of a kind of high bandwidth high PSRR according to claim 1, is characterized in that, described feedback resistance comprises the resistance R of series connection mutually _f1and R _f2.

3. the low differential voltage linear voltage stabilizer circuit of a kind of high bandwidth high PSRR according to claim 1, is characterized in that, described transistor M ₁and M ₂size meet: when time, formula ${\mathrm{PSR}}_{ERFF}=\frac{v_{out}\left(s\right)}{v_{in}\left(s\right)}=\frac{1+g_{m,p}{r}_{ds,p}\&lsqb;1-H\left(s\right)\&rsqb;}{1+{\mathrm{\&beta;}}_0{r}_{ds,p}\&lsqb;A\left(s\right)g_{m,p}+\frac{1}{R_{f2}}\&rsqb;+\frac{r_{ds,p}}{Z_L\left(s\right)}}$ Denominator be approximately zero, wherein g _m1for transistor M ₁mutual conductance, g _m2for transistor M ₂mutual conductance, r _{ds, p}for power tube M _pchannel resistance, g _m,pfor power tube M _pmutual conductance, for feedback factor, v _gpfor power tube M _pthe small signal at grid place, C _hfor filter capacitor, g _mhfor the load pipe M of diode-connected _hmutual conductance, the open-loop transmission function that A (s) is error amplifier, Z _ls equivalent output impedance that () is LDO.

4. the low differential voltage linear voltage stabilizer circuit of a kind of high bandwidth high PSRR according to claim 1, is characterized in that, described transistor M _sbe of a size of M _p1/K.

5. the low differential voltage linear voltage stabilizer circuit of a kind of high bandwidth high PSRR according to claim 1, it is characterized in that, described error amplifier comprises nmos pass transistor M ₄, M ₅, M ₁₀, M ₁₁and M ₁₃, also comprise PMOS transistor M ₆, M ₇, M ₈, M ₉and M ₁₂, described transistor M ₄, M ₅, M ₁₀, M ₁₁and M ₁₃source grounding, described transistor M ₄drain electrode and M ₅grid all connect current source negative pole, described transistor M ₆, M ₇and M ₁₂source electrode and current source positive pole all meet input voltage V _in, described transistor M ₄grid and M ₅grid electrical connection, described transistor M ₅drain electrode respectively with transistor M ₆drain and gate, M ₇grid and M ₁₂grid electrical connection, described transistor M ₆grid also with M ₇grid electrical connection, described transistor M ₇drain electrode respectively with M ₈and M ₉source electrode electrical connection, described M ₈and M ₉source electrode be electrically connected mutually, described transistor M ₈grid connect reference voltage, drain electrode respectively with transistor M ₁₀drain electrode, grid and M ₁₁grid electrical connection, described M ₁₀grid also with M ₁₁grid electrical connection, described transistor M ₁₁drain electrode respectively with M ₉drain electrode and M ₁₃grid electrical connection, described transistor M ₁₃drain electrode and M ₁₂drain electrode electrical connection.

6. the low differential voltage linear voltage stabilizer circuit of a kind of high bandwidth high PSRR according to claim 1, is characterized in that, described transistor M ₅and M ₆the long design of grid make circuit meet wherein, r _ds5for transistor M ₅channel resistance, g _m6for transistor M ₆mutual conductance.