CN102591393B - Low-dropout linear regulator - Google Patents

Abstract

The invention discloses a low-dropout linear regulator. The low-dropout linear regulator comprises a first PMOS (p-channel metal oxide semiconductor) transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS (n-channel metal oxide semiconductor) transistor, a first resistance unit, a second resistance unit, a third resistance unit, a fourth resistance unit, a fifth resistance unit, a first capacitor, a second capacitor, a first amplifier and a second amplifier. The low-dropout linear regulator adopts feed-forward noise cancellation technology, and can enable the gate voltageof a power tube to have noise identical to the noise of power supply voltage in magnitude and phase by coupling, so that the gate voltage difference of the power tube does no contain the noise of power supply voltage and that the drain current is immune to the noise of power supply voltage. Accordingly, the output voltage of the regulator under high-frequency conditions is immune to the power voltage noise, thereby greatly improving power supply rejection ratio of the linear regulator under high-frequency conditions.

Description

A kind of low pressure difference linear voltage regulator

Technical field

The invention belongs to the power management techniques field, be specifically related to a kind of low pressure difference linear voltage regulator (Low Dropout Regulator, design LDO).

Background technology

Low pressure difference linear voltage regulator has that output noise is little, circuit structure is simple, chip occupying area is little and advantage such as voltage ripple is little, has become the important circuit of a class in the power management chip.Low pressure difference linear voltage regulator can provide the power supply of output ripple and low for noise-sensitive circuit such as mimic channel and radio circuits, and because structure is simple relatively, peripheral component is few, thereby is widely used in the on-chip system chip.

LDO is the nucleus module in the power management, is mainly mimic channel and radio circuit provides low noise power supply, so Power Supply Rejection Ratio is one of key parameter of LDO.But the fast development along with integrated circuit, working frequency of chip is improving constantly, the Power Supply Rejection Ratio of LDO also decreases, thereby power supply noise will influence the performance of total system by LDO, therefore can not satisfy the application requirements of high-frequency work environment, improve the important research direction that Power Supply Rejection Ratio under the high frequency situations has become LDO.At present, most commercial high Power Supply Rejection Ratio LDO chips adopt the method for LDO cascade, this kind scheme directly causes the reduction of LDO efficient, some solutions have been proposed in some documents, but mostly to increase chip area, the reduction load capacity is cost, such as using in the document " Mohamed El-Nozahi; Ahmed Amer; Joselyn Torres; Kamran Entesari; Edgar S á nchez-Sinencio; High PSR Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique, 565-577 " feed-forward technique to improve the Power Supply Rejection Ratio of LDO, not only big the but also Power Supply Rejection Ratio of chip area neither be too high.

Summary of the invention

The objective of the invention is to have proposed a kind of low pressure difference linear voltage regulator in order to solve the lower problem of Power Supply Rejection Ratio under the existing low pressure difference linear voltage regulator high frequency situations.

Technical scheme of the present invention is: a kind of low pressure difference linear voltage regulator, comprise: PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, NMOS pipe and first resistance unit, second resistance unit, the 3rd resistance unit, the 4th resistance unit, the 5th resistance unit, first electric capacity, second electric capacity and first amplifier, second amplifier, concrete annexation is:

One end of first resistance unit connects reference voltage, and the other end connects an end of first electric capacity and the in-phase input end of first amplifier, and the other end of first electric capacity connects outer power voltage; The reverse input end of first amplifier connects an end of the 3rd resistance unit and the source electrode of a NMOS pipe, and output terminal connects the grid of a NMOS pipe, and the 3rd resistance unit other end connects earth potential; The drain electrode of the one NMOS pipe connects an end of second resistance unit and the grid of the 2nd PMOS pipe, and the other end of second resistance unit connects outer power voltage; The source electrode of the 2nd PMOS pipe connects outer power voltage, and drain electrode connects the grid of a PMOS pipe and the source electrode of the 3rd PMOS pipe; The source electrode of the one PMOS pipe connects outer power voltage, and the drain electrode of the 3rd PMOS pipe connects earth potential, and grid connects the output terminal of second amplifier; The in-phase input end of second amplifier connects reference voltage, one end of one end of the 4th resistance unit, an end of the 5th resistance unit and second electric capacity links together and links to each other with the second amplifier reverse input end, and the other end of the 5th resistance unit is connected to earth potential; The other end of the other end of the 4th resistance and second electric capacity links together and links to each other as described low pressure difference linear voltage regulator with the drain electrode of a PMOS pipe is output terminal.

Beneficial effect of the present invention: low pressure difference linear voltage regulator of the present invention, compare with existing LDO, under the low frequency situation, not too big variation of Power Supply Rejection Ratio, but when this voltage stabilizer is operated in the high frequency situation, owing to adopt the feed-forward noise cancellation techniques, this technology is to make the grid voltage as a PMOS pipe of power tube contain and supply voltage noise equal and opposite in direction by outer power voltage coupling, the noise that phase place is identical, therefore the gate source voltage difference of power tube does not contain the supply voltage noise, drain current is not subjected to the supply voltage The noise, thereby make the output voltage of voltage stabilizer under the high frequency situations also not be subjected to the supply voltage The noise, improved the Power Supply Rejection Ratio of high frequency situations lower linear voltage stabilizer greatly.Circuit structure proposed by the invention keeps LDO high-level efficiency, low noise, simple while of circuit structure, has improved the Power Supply Rejection Ratio under the high frequency situations.

Description of drawings

Fig. 1 is low differential voltage linear voltage stabilizer circuit structural representation of the present invention.

Fig. 2 is the Power Supply Rejection Ratio emulation contrast synoptic diagram that has the feed-forward noise cancellation techniques and do not have feed-forward noise cancellation techniques low pressure difference linear voltage regulator of the present invention.

Embodiment

The invention will be further elaborated below in conjunction with accompanying drawing and specific embodiment.

At low this problem of existing LDO Power Supply Rejection Ratio under high frequency situations, the present invention proposes a kind of low pressure difference linear voltage regulator of high Power Supply Rejection Ratio, particular circuit configurations as shown in Figure 1, comprise PMOS pipe M0, M2, M3 and NMOS pipe M1 and resistance unit R1, R2, R3, R4, R5 and capacitor C 1, C2, the first amplifier OP, the second operational amplifier OTA.R among Fig. 1 _LAnd C _LLoad unit as low pressure difference linear voltage regulator.Concrete annexation is as follows:

The end of resistance unit R1 connects reference voltage V _Ref, the other end connects the end of C1 and the in-phase input end of amplifier OP, and the other end of C1 connects outer power voltage V _INThe reverse input end of amplifier OP connects the end of R3 and the source electrode of NMOS pipe M1, and output terminal connects the grid of NMOS pipe M1, and the R3 other end connects ground VSS; The drain electrode of NMOS pipe M1 connects the end of R2 and the grid of PMOS pipe M2, and the other end of R2 connects outer power voltage V _INThe source electrode of PMOS pipe M2 connects outer power voltage V _IN, drain electrode connects the grid of PMOS pipe M0 and the source electrode of PMOS pipe M3; The drain electrode of PMOS pipe M3 connects earth potential VSS, the output terminal of grid concatenation operation amplifier OTA; The in-phase input end of operational amplifier OTA connects reference voltage V _Ref, reverse input end connects the end that R4 is connected with R5 and C2, and the other end of R5 is connected to earth potential VSS; The other end of R4 links to each other with the other end of C2, is connected to R _LAnd C _LAn end and the drain electrode of PMOS pipe M0, be output terminal V as low pressure difference linear voltage regulator _OUT, the source electrode of PMOS pipe M0 connects outer power voltage V _IN, R _LThe other end and C _LThe other end all be connected to earth potential VSS.

Here, resistance unit R1 and capacitor C 1 are formed Hi-pass filter, the supply voltage noise are coupled to the in-phase input end of operational amplifier OP under high frequency situations.Resistance unit R1 and capacitor C 1 all will be tried one's best greatly in the design of this Hi-pass filter, so just can provide better coupling effect, but the increase of resistance unit and electric capacity can increase chip area, thus resistance unit R1 and capacitor C 1 choose the consideration of will compromising; Amplifier OP mainly plays clamped effect in circuit, the in-phase input end voltage clamping to reverse input end, is changed forming currents thereby pass through resistance R 3.In order under high frequency situations, fast the supply voltage noise to be coupled to the grid of power tube, as a kind of more excellent scheme, amplifier OP should select high speed operation amplifier, and for better feed-forward noise signal, the bandwidth of amplifier must be enough big, the bandwidth of this amplifier is greater than the C point bandwidth, thereby can not influence the feedforward speed of LDO; Resistance unit R4, R5 are feedback resistance, form feedback network, can regulate the size of output voltage by the ratio of regulating resistance unit R4, R5 resistance; The resistance of resistance unit R2, R3 is identical, can make like this that the B point voltage is not subjected to the supply voltage The noise among Fig. 1; In order to make PMOS pipe M2 have identical mutual conductance g with M3 _mSo the parameter of M2 and M3 is identical.

LDO of the present invention is owing to adopt the feed-forward noise cancellation techniques, this technology is to contain and supply voltage noise equal and opposite in direction by the grid voltage of outer power voltage coupling with power tube, the noise that phase place is identical, therefore the gate source voltage difference of power tube does not contain the supply voltage noise, drain current is not subjected to the supply voltage The noise, thereby make the output voltage of voltage stabilizer under the high frequency situations also not be subjected to the supply voltage The noise, improved the Power Supply Rejection Ratio of high frequency situations lower linear voltage stabilizer greatly.

Can realize that to LDO of the present invention the principle of high PSRR is specifically described under high frequency situations below:

The Hi-pass filter that resistance R 1 and capacitor C 1 are formed is with supply voltage V _INNoise V _IN(f) be coupled to the in-phase input end of OP amplifier, clamped by the OP amplifier, then the reverse input end of amplifier (being A point among Fig. 1) voltage is

V _A=V _ref+V _IN(f)

Thereby obtain R3 and go up electric current:

I _R3=[V _ref+V _IN(f)]/R3

So B point voltage:

V _B=V _IN+V _IN(f)-[V _ref+V _IN(f)]=V _IN-V _ref

The gate source voltage of PMOS pipe M2:

Vgs _M2=V _IN+V _IN(f)-V _B=V _IN(f)+V _ref

Parameter owing to PMOS pipe M2, M3 is identical again, and drain current is identical, so PMOS pipe M2, M3 have identical mutual conductance g _m, C point voltage then:

V _C=g _m*Vgs _M2*1/g _m=V _ref+V _IN(f)

For containing V _IN(f) so voltage and value are the V of power tube M0 _GsThe noise that does not contain supply voltage, the drain current of power tube and independent of power voltage, thereby the raising of Power Supply Rejection Ratio under the realization high frequency situations.

The second amplifier OTA is as trsanscondutance amplifier, its purposes be voltage clamping with input end in the same way to reverse input end, and for the grid of PMOS pipe M3 provides suitable operating voltage, thereby realize the stable of output voltage under the low frequency situation.Since the end ground connection of R5, other end magnitude of voltage by clamped in reference voltage V _RefOn, and R5 goes up electric current and goes up electric current with R4 and equate, then the LDO output voltage V _OUTFor:

$V_{\mathrm{out}}=(1+\frac{R_4}{R5})*V_{\mathrm{ref}}$

Capacitor C 2 is introduced as next zero point and a limit for system in this LDO circuit:

Zero frequency: ${\mathrm{\ω}}_z=\frac{1}{C2*R4}$

Pole frequency: ${\mathrm{\ω}}_p=\frac{1}{C2*(R4//R5)}$

Be inferior limit that produces among the LDO in order to offset the zero point that produces, and to compare R4 less owing to resistance unit R5, thus produce high pole frequency, thus increased the bandwidth of system, improved system stability.

Derivation can be seen, removes capacitor C 1 in the ifs circuit, and then the grid of power tube does not just have the supply voltage noise, can not had the LDO of feed-forward noise technology like this.

Fig. 2 is not for having LDO and the PSRR simulation waveform comparison diagram that has the LDO of feed-forward noise cancellation techniques of the present invention of feed-forward noise cancellation techniques, wherein, last figure is that the LDO pull-up resistor that do not have a feed-forward noise cancellation techniques is respectively 200K, 2K, 80 ohm PSRR oscillogram, and figure below is that the LDO pull-up resistor that has a feed-forward noise cancellation techniques is respectively 200K, 2K, 80 ohm PSRR oscillogram.The load capacitance size is 4uF, and the simulation waveform curve is as shown in table 1:

Table 1

Can see that frequency 1K is following have feed-forward noise technology LDO and do not have feed-forward noise technology LDO Power Supply Rejection Ratio do not have to change substantially; More than the frequency 10K, have the LDO of feed-forward noise cancellation techniques than more than the big 10db of PSRR that does not have feed-forward noise cancellation techniques LDO, compare with existing LDO, the high frequency PSRR that the present invention has feed-forward noise technology LDO also has bigger advantage.

Those of ordinary skill in the art will appreciate that embodiment described here is in order to help reader understanding's principle of the present invention, should to be understood that protection scope of the present invention is not limited to such special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combinations that do not break away from essence of the present invention according to these technology enlightenments disclosed by the invention, and these distortion and combination are still in protection scope of the present invention.

Claims (2)

1. low pressure difference linear voltage regulator, it is characterized in that, comprise: PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, NMOS pipe and first resistance unit, second resistance unit, the 3rd resistance unit, the 4th resistance unit, the 5th resistance unit, first electric capacity, second electric capacity and first amplifier, second amplifier, concrete annexation is:

One end of first resistance unit connects reference voltage, and the other end connects an end of first electric capacity and the in-phase input end of first amplifier, and the other end of first electric capacity connects outer power voltage; The reverse input end of first amplifier connects an end of the 3rd resistance unit and the source electrode of a NMOS pipe, and output terminal connects the grid of a NMOS pipe, and the 3rd resistance unit other end connects earth potential; The drain electrode of the one NMOS pipe connects an end of second resistance unit and the grid of the 2nd PMOS pipe, and the other end of second resistance unit connects outer power voltage; The source electrode of the 2nd PMOS pipe connects outer power voltage, and drain electrode connects the grid of a PMOS pipe and the source electrode of the 3rd PMOS pipe; The source electrode of the one PMOS pipe connects outer power voltage, and the drain electrode of the 3rd PMOS pipe connects earth potential, and grid connects the output terminal of second amplifier; The in-phase input end of second amplifier connects reference voltage, one end of one end of the 4th resistance unit, an end of the 5th resistance unit and second electric capacity links together and links to each other with the second amplifier reverse input end, and the other end of the 5th resistance unit is connected to earth potential; The other end of the other end of the 4th resistance and second electric capacity links together and links to each other as described low pressure difference linear voltage regulator with the drain electrode of a PMOS pipe is output terminal.

2. low pressure difference linear voltage regulator according to claim 1 is characterized in that, described second resistance unit is identical with the resistance of the 3rd resistance unit.

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