CN104460802B - The low pressure difference linear voltage regulator of one self-adaptive current multiple circuit and this circuit integrated - Google Patents

Abstract

The invention discloses the low pressure difference linear voltage regulator of a kind of self-adaptive current multiple circuit and this circuit integrated, first by constant bias voltage generative circuit for generating the constant bias voltage of NMOS tube and PMOS, sluggish current comparator gathers fraction load current again, compare with steady current, when load underloading, sluggish current comparator turns off self-adaptive current multiplication generative circuit, self-adaptive current multiplier electrode VBPA is for raising, low pressure difference linear voltage regulator operational amplifier bias current reduces, thus ensures stablize and reduce quiescent dissipation; When load by be downloaded to heavy duty time, self-adaptive current multiplication generative circuit opened by sluggish current comparator, self-adaptive current multiplier electrode VBPA reduces, operational amplifier bias current is increased to specific factor during underloading, the gain bandwidth product of low pressure difference linear voltage regulator increases, and transient response performance strengthens.

Description

The low pressure difference linear voltage regulator of one self-adaptive current multiple circuit and this circuit integrated

Technical field

The invention belongs to technical field of power management, more specifically say, relate to the low pressure difference linear voltage regulator of a kind of self-adaptive current multiple circuit and this circuit integrated.

Background technology

Low pressure difference linear voltage regulator is the important component part of power-supply management system, has that transient response speed is fast, quiescent current is low, advantages of simple structure and simple, is the circuit of some noise-sensitive, as medical electronics circuit etc., provides clean, the stable energy.

Conventional low voltage difference linear constant voltage regulator needs a capacitance to be the outer filter capacitor of sheet of 0.1 ~ 10 μ F at output terminal, this electric capacity makes the dominant pole of low pressure difference linear voltage regulator be positioned at output terminal, guarantee low pressure difference linear voltage regulator is stablized, and also can absorb output voltage overshoot and the undershoot of transient state transition period simultaneously.But existing technique cannot the filter capacitor of integrated large capacitance, can only be connected to board-level circuit, realized by additional electric capacity by pad and bonding wire.But additional electric capacity not only increases cost, too increase low pressure difference linear voltage regulator volume, in the application of some implantable medical devices, system bulk is strictly limited, and industry member needs the low pressure difference linear voltage regulator without additional electric capacity simultaneously.

Therefore, be suggested without the outer electric capacity low pressure difference linear voltage regulator of sheet, the outer filter capacitor of sheet can be eliminated completely.Be completely integrated in chip internal without the outer electric capacity low pressure difference linear voltage regulator of sheet, take silicon area little, be therefore extensively employed in medical electronics field.But without the outer electric capacity low pressure difference linear voltage regulator of sheet due to the upper punch of the output voltage that do not have filter capacitor to absorb and undershoot, mapping is very crucial.

The bias current adding operational amplifier optimizes the typical method without the outer electric capacity low pressure difference linear voltage regulator of sheet, but the energy is the resource be of great value in the application of low-power consumption medical electronics, in order to extend the stand-by time of system, when usually wishing underloading, bias current is minimized, simultaneously similar with based on miller-compensated operational amplifier without the outer electric capacity low pressure difference linear voltage regulator dominant pole position of sheet, be positioned at the grid of Correctional tube MP, secondary limit is positioned at low pressure difference linear voltage regulator and exports.High bias currents can increase the low pressure difference linear voltage regulator first order, the namely mutual conductance of operational amplifier, the gain bandwidth product of low pressure difference linear voltage regulator is widened, the secondary limit of low pressure difference linear voltage regulator is determined by the mutual conductance of Correctional tube MP, when low pressure difference linear voltage regulator load current is lower, secondary pole frequency is usually lower, increasing the biased electrical of the operational amplifier gain bandwidth product widening low pressure difference linear voltage regulator that fails to be convened for lack of a quorum causes the phase margin of low pressure difference linear voltage regulator to reduce, causes low pressure difference linear voltage regulator instability when underloading.Therefore, only have and introduce extra miller capacitance, reduce the gain bandwidth product of voltage stabilizer.This not only adds the area of voltage stabilizer, miller capacitance also can reduce the switching rate of operational amplifier simultaneously, reduces the transient response speed of voltage stabilizer.

Document " Output-capacitor-freeadaptivelybiasedlowdropoutregulator forsystem-on-chips " (IEEETrans.CircuitsSyst.I, 2010,57 (5): 1017 – 1028) propose a kind of low pressure difference linear voltage regulator, have employed adaptive bias technology, when underloading, operational amplifier bias current is low, ensure that low pressure difference linear voltage regulator is stablized; During heavy duty, by PMOS coupling Correctional tube MP grid voltage, gather the quiescent current that fraction load current increases operational amplifier, expanded low pressure difference linear voltage regulator bandwidth, improve operational amplifier switching rate, enhance the transient response performance of low pressure difference linear voltage regulator.But, adaptive bias technology is only effective when low pressure difference linear voltage regulator heavy duty, in carry time, add bias current very little, low pressure difference linear voltage regulator performance is not almost improved, meanwhile, the method being increased bias current by coupling Correctional tube MP grid voltage is affected obviously by flow-route and temperature, reduces the robustness of low pressure difference linear voltage regulator.

Summary of the invention

The object of the invention is to overcome the deficiencies in the prior art, the low pressure difference linear voltage regulator of a kind of self-adaptive current multiple circuit and this circuit integrated is provided, is improved frequency characteristic and the transient response performance of integrated low-voltage difference linear constant voltage regulator on sheet by adaptive bias technology.

For achieving the above object, the present invention one self-adaptive current multiple circuit, is characterized in that, comprising:

One constant bias voltage generative circuit, comprises PMOS MP4, PMOS MP5 and NMOS tube MN1;

The source electrode of PMOS MP4 and PMOS MP5 meets supply voltage VDD, and the grid of the drain electrode of PMOS MP4, the grid of PMOS MP4, PMOS MP5 is connected and is linked into outside constant-current bias source IB, for generating the constant bias voltage VBP of PMOS;

The drain electrode of PMOS MP5, the grid of NMOS tube MN1, drain electrode are connected with the grid of the NMOS tube MN2 in sluggish current comparator, are linked into the constant bias voltage VBN of NMOS tube;

The source ground of NMOS tube MN1;

One sluggish current comparator, comprises PMOS MP1, PMOS MP2 and NMOS tube MN2;

The source electrode of PMOS MP1, PMOS MP2 meets supply voltage VDD, the grid of PMOS MP1 meets voltage VG, and the grid of the NMOS tube MN4 that the drain electrode of the drain electrode of PMOS MP1, the drain electrode of PMOS MP2, NMOS tube MN2 and self-adaptive current double in generative circuit is all connected;

Grid and the self-adaptive current of PMOS MP2 double the grid of the PMOS MP3 in generative circuit, drain electrode, NMOS tube MN4 drain electrode be all connected, be linked into the self-adaptive current multiplier electrode VBPA of PMOS;

The source ground of NMOS tube MN2, the grid of NMOS tube MN2 is linked into NMOS tube constant bias voltage VBN;

One self-adaptive current multiplication generative circuit, comprises PMOS MP3 and NMOS tube MN3, NMOS tube MN4;

The source electrode of PMOS MP3 meets supply voltage VDD, and the drain electrode of the grid of PMOS MP3, the drain electrode of PMOS MP3, NMOS tube MN4 is all connected, is linked into the self-adaptive current multiplier electrode VBPA of PMOS;

The source ground of NMOS tube MN3, the drain electrode of NMOS tube MN3 connects the source electrode of NMOS tube MN4;

The grid of NMOS tube MN4 is all connected with the drain electrode of the PMOS MP1 in sluggish current comparator, the drain electrode of PMOS MP2, the drain electrode of NMOS tube MN2.

Self-adaptive current multiple circuit comprises constant bias voltage generative circuit, sluggish current comparator and self-adaptive current multiplication generative circuit; Constant bias voltage generative circuit is for generating the constant bias voltage of NMOS tube and PMOS; Sluggish current comparator first gathers fraction load current by PMOS MP1, the steady current formed with NMOS tube MN2 again compares, when load underloading, the grid voltage of NMOS tube MN4 is ground voltage, sluggish current comparator turns off self-adaptive current multiplication generative circuit by NMOS tube MN4, self-adaptive current multiplier electrode VBPA is for raising, and low pressure difference linear voltage regulator operational amplifier bias current reduces, thus ensures stablize and reduce quiescent dissipation; When load by be downloaded to heavy duty time, increased by the electric current of PMOS MP1, the grid voltage of NMOS tube MN4 is supply voltage VDD, the complete conducting of NMOS tube MN4, sluggish current comparator opens self-adaptive current multiplication generative circuit by NMOS tube MN4, is increased by the electric current of PMOS MP3, self-adaptive current multiplier electrode VBPA reduces, operational amplifier bias current is increased to specific factor during underloading, and the gain bandwidth product of low pressure difference linear voltage regulator increases, and transient response performance strengthens; Wherein, PMOS MP2 is for generation of sluggishness.

The low pressure difference linear voltage regulator of integrated described self-adaptive current multiple circuit, is characterized in that, comprising: operational amplifier, Correctional tube and potential-divider network;

Operational amplifier, Correctional tube and potential-divider network constitute degeneration factor jointly, for the output voltage VO UT of stabilizing low voltage difference linear stabilizer; Wherein, the reverse input end of operational amplifier connects external reference voltages VREF, and in-phase input end connects low pressure difference linear voltage regulator feedback voltage V FB, and output terminal connects the grid of Correctional tube MP; Resistor voltage divider network input end is that low pressure difference linear voltage regulator exports VOUT, and output terminal is low pressure difference linear voltage regulator feedback voltage V FB; The source electrode of Correctional tube MP connects outer power voltage VDD, and the drain electrode of Correctional tube MP exports VOUT as low pressure difference linear voltage regulator.

Wherein, described operational amplifier, comprising: PMOS MP6, PMOS MP7, PMOS MP8, PMOS MP9, PMOS MP10, PMOS MP11, PMOS MP12, PMOS MP13 and NMOS tube MN6, NMOS tube MN7, NMOS tube MN8, NMOS tube MN9, NMOS tube MN10, NMOS tube MN11, NMOS tube MN12, NMOS tube MN13;

The source electrode of PMOS MP6, PMOS MP7, PMOS MP8, PMOS MP9, PMOS MP10, PMOS MP11, PMOS MP12, PMOS MP13 is all connected to supply voltage VDD;

The drain electrode of PMOS MP6, the drain electrode of PMOS MP8, the drain electrode of NMOS tube MN6, the grid of NMOS tube MN10 are all connected;

The grid of PMOS MP6 and PMOS MP7 is connected respectively to the constant bias voltage VBP of PMOS;

The drain electrode of PMOS MP7, the drain electrode of PMOS MP9, the drain electrode of NMOS tube MN7, the grid of NMOS tube MN11 are all connected;

The grid of PMOS MP8 and PMOS MP9 is linked into the self-adaptive current multiplier electrode VBPA of PMOS respectively;

The drain electrode of PMOS MP10, the grid of PMOS MP10, the grid of PMOS MP12, the drain electrode of NMOS tube MN8 are all connected;

The drain electrode of PMOS MP11, the grid of PMOS MP11, the grid of PMOS MP13, the drain electrode of NMOS tube MN9 are all connected;

The drain electrode of PMOS MP12, the drain electrode of NMOS tube MN12, the grid of NMOS tube MN12, the grid of NMOS tube MN13 are all connected;

The grid of the drain electrode of PMOS MP13, the drain electrode of NMOS tube MN13, Correctional tube MP is all connected, meets voltage VG;

The grid of NMOS tube MN6, NMOS tube MN8 all meets external reference voltages VREF, and the drain electrode of the source electrode of NMOS tube MN6, the source electrode of NMOS tube MN9 and NMOS tube MN10 is all connected;

The grid of NMOS tube MN7, NMOS tube MN9 all connects low pressure difference linear voltage regulator feedback voltage V FB, and the drain electrode of the source electrode of NMOS tube MN7, the source electrode of NMOS tube MN8, NMOS tube MN11 is all connected;

The source electrode ground connection respectively of NMOS tube MN10, NMOS tube MN11, NMOS tube MN12, NMOS tube MN13.

Described potential-divider network, comprising: the first divider resistance RFB1 and the second divider resistance RFB2;

One end of first divider resistance RFB1 is connected to low pressure difference linear voltage regulator and exports VOUT, and one end is connected to low pressure difference linear voltage regulator feedback voltage V FB in addition; One end of second divider resistance RFB2 is connected to low pressure difference linear voltage regulator feedback voltage V FB, and the other end is connected to ground.

Goal of the invention of the present invention is achieved in that

Self-adaptive current multiple circuit of the present invention comprises constant bias voltage generative circuit, sluggish current comparator and self-adaptive current multiplication generative circuit.Constant bias voltage generative circuit is for generating the constant bias voltage of NMOS tube and PMOS; First sluggish current comparator gathers fraction load current, then compare with steady current, during underloading, sluggish current comparator turns off self-adaptive current multiplication generative circuit, self-adaptive current multiplier electrode VBPA is for raising, low pressure difference linear voltage regulator operational amplifier bias current reduces, thus ensures stablize and reduce quiescent dissipation; In when being downloaded to heavy duty, self-adaptive current multiplication generative circuit opened by sluggish current comparator, and self-adaptive current multiplier electrode VBPA reduces, and operational amplifier bias current is increased to specific factor during underloading, the gain bandwidth product of low pressure difference linear voltage regulator increases, and transient response performance strengthens.

Meanwhile, the low pressure difference linear voltage regulator of self-adaptive current multiple circuit of the present invention and this circuit integrated also has following beneficial effect:

(1), the present invention one self-adaptive current multiple circuit, by voltage stabilizer in carry and heavy duty time quiescent current rise to underloading time specific factor, therefore voltage stabilizer in carry and heavy duty time quiescent current can not be subject to the impact of loading condition, temperature and technique, stability and robustness are obviously better than traditional adaptive bias technology.

(2), low, the fast response time of the quiescent current of the low pressure difference linear voltage regulator of integrated adaptive current multiplication circuit, be suitable for medical electronics application.

Accompanying drawing explanation

Fig. 1 is the low pressure difference linear voltage regulator theory diagram of self-adaptive current multiple circuit of the present invention and this circuit integrated;

Fig. 2 is a kind of implementing circuit figure of self-adaptive current multiple circuit of the present invention;

Fig. 3 is a kind of implementing circuit figure of the low pressure difference linear voltage regulator of integrated adaptive current multiplication circuit;

Fig. 4 is the low dropout linear regulator structure figure of integrated underloading transient state intensifier circuit;

Fig. 5 is the frequency response the result figure of the low pressure difference linear voltage regulator of integrated adaptive current multiplication circuit;

Fig. 6 is the outer electric capacity of low pressure difference linear voltage regulator sheet of integrated adaptive current multiplication circuit when being 0, by underloading to heavily loaded load transient response the result figure;

Fig. 7 is the outer electric capacity of low pressure difference linear voltage regulator sheet of integrated adaptive current multiplication circuit when being 100pF, by underloading to heavily loaded load transient response the result figure;

Fig. 8 is the outer electric capacity of low pressure difference linear voltage regulator sheet of integrated adaptive current multiplication circuit when being 100pF, by be downloaded to the load transient response the result figure of heavy duty;

Embodiment

Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described, so that those skilled in the art understands the present invention better.Requiring particular attention is that, in the following description, when perhaps the detailed description of known function and design can desalinate main contents of the present invention, these are described in and will be left in the basket here.

Embodiment

Fig. 1 is the present invention one self-adaptive current multiple circuit and the integrated low pressure difference linear voltage regulator theory diagram be somebody's turn to do.

In the present embodiment, as shown in Figure 1, the present invention mainly comprises the low pressure difference linear voltage regulator 2 of self-adaptive current multiple circuit 1 and this circuit integrated.Wherein, self-adaptive current multiple circuit 1 comprises and comprises: constant bias voltage generative circuit 3, sluggish current comparator 4 and self-adaptive current multiplication generative circuit 5; Low pressure difference linear voltage regulator 2 comprises again operational amplifier 6, Correctional tube 7 and resistance pressure-dividing network 8.

Constant bias voltage generative circuit 3 is for generating the constant bias voltage of NMOS tube and PMOS, sluggish current comparator 4 first first gathers fraction load current by PMOS MP1, the steady current formed with NMOS tube MN2 again compares, when load underloading, the grid voltage of NMOS tube MN4 is ground voltage, sluggish current comparator 4 turns off self-adaptive current multiplication generative circuit 1 by NMOS tube MN4, self-adaptive current multiplier electrode VBPA raises, the bias current of the operational amplifier 6 in low pressure difference linear voltage regulator 2 reduces, thus ensure stablize and reduce quiescent dissipation, when load by be downloaded to heavy duty time, increased by the electric current of PMOS MP1, the grid voltage of NMOS tube MN4 is supply voltage VDD, the complete conducting of NMOS tube MN4, sluggish current comparator 4 opens self-adaptive current multiplication generative circuit 1 by NMOS tube MN4, increased by the electric current of PMOS MP3, self-adaptive current multiplier electrode VBPA reduces, the bias current of operational amplifier 6 is increased to specific factor during underloading, the gain bandwidth product of low pressure difference linear voltage regulator 2 increases, transient response performance strengthens, wherein, PMOS MP2 is for generation of sluggishness, promote the robustness of circuit, self-adaptive current multiple circuit is used for the bias current of control algorithm amplifier 6.

Operational amplifier 6, Correctional tube 7 and potential-divider network 8 constitute degeneration factor jointly, for the output voltage VO UT of stabilizing low voltage difference linear stabilizer 2; The reverse input end of operational amplifier 6 connects external reference voltages VREF, and in-phase input end connects low pressure difference linear voltage regulator 2 feedback voltage V FB, and output terminal connects the grid of Correctional tube 7; Resistor voltage divider network 8 input end is that low pressure difference linear voltage regulator 2 exports VOUT, and output terminal is low pressure difference linear voltage regulator 2 feedback voltage V FB; The source electrode of Correctional tube 7 connects outer power voltage VDD, and the drain electrode of Correctional tube 7 exports VOUT as described low pressure difference linear voltage regulator 2.

Fig. 2 is a kind of implementing circuit figure of self-adaptive current multiple circuit of the present invention.

As shown in Figure 2, in the present embodiment, self-adaptive current multiple circuit comprises: constant bias voltage generative circuit, sluggish current comparator and self-adaptive current multiplication generative circuit.

Constant bias voltage generative circuit, comprises PMOS MP4, PMOS MP5 and NMOS tube MN1;

The source electrode of PMOS MP4 and PMOS MP5 meets supply voltage VDD, and the grid of the drain electrode of PMOS MP4, the grid of PMOS MP4, PMOS MP5 is connected and is linked into outside constant-current bias source IB, for generating the constant bias voltage VBP of PMOS;

The drain electrode of PMOS MP5, the grid of NMOS tube MN1, drain electrode are connected with the grid of the NMOS tube MN2 in sluggish current comparator, are linked into the constant bias voltage VBN of NMOS tube;

The source ground of NMOS tube MN1;

Sluggish current comparator, comprises PMOS MP1, PMOS MP2 and NMOS tube MN2;

The source electrode of PMOS MP1, PMOS MP2 meets supply voltage VDD, the grid of PMOS MP1 meets voltage VG, and the grid of the NMOS tube MN4 that the drain electrode of the drain electrode of PMOS MP1, the drain electrode of PMOS MP2, NMOS tube MN2 and self-adaptive current double in generative circuit is all connected;

Grid and the self-adaptive current of PMOS MP2 double the grid of the PMOS MP3 in generative circuit, drain electrode, NMOS tube MN4 drain electrode be all connected, be linked into the self-adaptive current multiplier electrode VBPA of PMOS;

The source ground of NMOS tube MN2, the grid of NMOS tube MN2 is linked into NMOS tube constant bias voltage VBN;

Self-adaptive current multiplication generative circuit, comprises PMOS MP3 and NMOS tube MN3, NMOS tube MN4;

The source electrode of PMOS MP3 meets supply voltage VDD, and the drain electrode of the grid of PMOS MP3, the drain electrode of PMOS MP3, NMOS tube MN4 is all connected, is linked into the self-adaptive current multiplier electrode VBPA of PMOS;

The source ground of NMOS tube MN3, the drain electrode of NMOS tube MN3 connects the source electrode of NMOS tube MN4;

The grid of NMOS tube MN4 is all connected with the drain electrode of the PMOS MP1 in sluggish current comparator, the drain electrode of PMOS MP2, the drain electrode of NMOS tube MN2.

Fig. 3 is a kind of implementing circuit figure of the low pressure difference linear voltage regulator of integrated adaptive current multiplication circuit.

In the present embodiment, as shown in Figure 3, low pressure difference linear voltage regulator, comprising: operational amplifier, Correctional tube and potential-divider network.

Operational amplifier, comprising: PMOS MP6, PMOS MP7, PMOS MP8, PMOS MP9, PMOS MP10, PMOS MP11, PMOS MP12, PMOS MP13 and NMOS tube MN6, NMOS tube MN7, NMOS tube MN8, NMOS tube MN9, NMOS tube MN10, NMOS tube MN11, NMOS tube MN12, NMOS tube MN13;

The source electrode of PMOS MP6, PMOS MP7, PMOS MP8, PMOS MP9, PMOS MP10, PMOS MP11, PMOS MP12, PMOS MP13 is all connected to supply voltage VDD;

The drain electrode of PMOS MP6, the drain electrode of PMOS MP8, the drain electrode of NMOS tube MN6, the grid of NMOS tube MN10 are all connected;

The grid of PMOS MP6 and PMOS MP7 is connected respectively to the constant bias voltage VBP of PMOS;

The drain electrode of PMOS MP7, the drain electrode of PMOS MP9, the drain electrode of NMOS tube MN7, the grid of NMOS tube MN11 are all connected;

The grid of PMOS MP8 and PMOS MP9 is linked into the self-adaptive current multiplier electrode VBPA of PMOS respectively;

The drain electrode of PMOS MP10, the grid of PMOS MP10, the grid of PMOS MP12, the drain electrode of NMOS tube MN8 are all connected;

The drain electrode of PMOS MP11, the grid of PMOS MP11, the grid of PMOS MP13, the drain electrode of NMOS tube MN9 are all connected;

The drain electrode of PMOS MP12, the drain electrode of NMOS tube MN12, the grid of NMOS tube MN12, the grid of NMOS tube MN13 are all connected;

The grid of the drain electrode of PMOS MP13, the drain electrode of NMOS tube MN13, Correctional tube MP is all connected, meets voltage VG;

The grid of NMOS tube MN6, NMOS tube MN8 all meets external reference voltages VREF, and the drain electrode of the source electrode of NMOS tube MN6, the source electrode of NMOS tube MN9 and NMOS tube MN10 is all connected;

The grid of NMOS tube MN7, NMOS tube MN9 all connects low pressure difference linear voltage regulator feedback voltage V FB, and the drain electrode of the source electrode of NMOS tube MN7, the source electrode of NMOS tube MN8, NMOS tube MN11 is all connected;

The source electrode ground connection respectively of NMOS tube MN10, NMOS tube MN11, NMOS tube MN12, NMOS tube MN13.

Potential-divider network, comprising: the first divider resistance RFB1 and the second divider resistance RFB2;

One end of first divider resistance RFB1 is connected to low pressure difference linear voltage regulator and exports VOUT, and one end is connected to low pressure difference linear voltage regulator feedback voltage V FB in addition; One end of second divider resistance RFB2 is connected to low pressure difference linear voltage regulator feedback voltage V FB, and the other end is connected to ground.

Fig. 4 is the low dropout linear regulator structure figure of integrated underloading transient state intensifier circuit.

In the present embodiment, as shown in Figure 4, the low pressure difference linear voltage regulator of integrated adaptive current multiplication circuit passes through the gate leakage capacitance C of Correctional tube MP _gdpthe miller capacitance formed realizes limit and is separated, and its transport function can be expressed as:

$A_{v\left(s\right)}=\frac{g_{m1}{R}_{o1}(g_{\mathrm{mp}}-s{C}_{\mathrm{gdp}})R_{\mathrm{out}}}{1+{\mathrm{sR}}_{o1}(C_{\mathrm{gsp}}+C_{\mathrm{gdp}}+g_{\mathrm{mp}}{R}_{\mathrm{out}}{C}_{\mathrm{gdp}})+s^2{C}_L(C_{\mathrm{gsp}}+C_{\mathrm{gdp}})R_{\mathrm{out}}{R}_{o1}}---\left(1\right)$

Wherein g _m1it is the mutual conductance of operational amplifier.R _o1it is the output resistance of operational amplifier.G _mpthe mutual conductance of Correctional tube MP, C _gspand C _gdpgrid source electric capacity and the gate leakage capacitance of Correctional tube MP respectively.C _lbe the output capacitance of a 100pF, it is used for simulating the maximum output capacitance of power division on sheet and the stray capacitance on some metal wires.R _outit is the overall output resistance of low pressure difference linear voltage regulator.

The dominant pole of low pressure difference linear voltage regulator and gain bandwidth product GBW distribution are expressed as:

P _-3dB＝1/[R _o1(C _gsp+C _gdp+g _mpR _outC _gdp)](2)

$\mathrm{GBW}=\frac{g_{m1}}{C_{\mathrm{gdp}}+\frac{C_{\mathrm{gsp}}+C_{\mathrm{gdp}}}{g_{\mathrm{mp}}{R}_{\mathrm{out}}}}---\left(3\right)$

The Z at zero point of low pressure difference linear voltage regulator RHP ₁can be expressed as:

Z ₁＝g _mp/C _gdp(4)

Due to Z ₁be far beyond gain bandwidth product, can't affect stable, in order to simple analysis, its effect is left in the basket.

The secondary limit P of low pressure difference linear voltage regulator RHP ₂can be expressed as:

$P_2=\frac{g_{\mathrm{mp}}}{C_{\mathrm{LOAD}}}\frac{C_{\mathrm{gsp}}+C_{\mathrm{gdp}}+g_{\mathrm{mp}}{R}_{\mathrm{out}}{C}_{\mathrm{gdp}}}{g_{\mathrm{mp}}{R}_{\mathrm{out}}(C_{\mathrm{gsp}}+C_{\mathrm{gdp}})}\≈\frac{g_{\mathrm{mp}}}{C_{\mathrm{LOAD}}}\frac{C_{\mathrm{gdp}}}{C_{\mathrm{gsp}}+C_{\mathrm{gdp}}}---\left(5\right)$

From dominant pole P _-3dBformula (2) can be found out, the equivalent capacity of operational amplifier output terminal is C _gsp+ C _gdp+ g _mpr _outc _gdp.Correctional tube MP grid source electric capacity C _gspwith Correctional tube MP grid leak C _gdpbe directly connected to the output of operational amplifier, g _mpr _outc _gdpbecause the Miller effect produces.During underloading, the gain of Correctional tube power level is very large, g _mpr _outc _gdp>>C _gsp+ C _gdp, gain bandwidth product GBW equals g _m1/ C _gdp.Secondary limit P2 is directly proportional in Correctional tube MP mutual conductance g _mp, reduce along with load current IL and reduce.Therefore, the poorest phase margin occur in load current IL minimum time.Appropriate design operational amplifier mutual conductance g can be passed through _m1obtain the gain bandwidth product needed for LDO, thus obtain the phase margin of expectation at minimum load current IL.When load current IL increases, secondary limit P ₂frequency raised, then, the gain bandwidth product of LDO there is no need still to remain on lower value.Therefore, in carry and heavy duty time, self-adaptive current multiple circuit is unlocked, and increases operational amplifier quiescent current, widens LDO gain bandwidth product.During heavy duty, in order to more effectively utilize chip area, Correctional tube MP is designed in linear zone, and the gain of Correctional tube power level can be lowered.The gain reduction of power level can cause the Miller effect to reduce, as shown in formula (3), gain bandwidth product GBW can reduce when heavy duty, therefore expands the gain bandwidth product GBW of voltage stabilizer by introducing self-adaptive current multiple circuit, promotes transient response performance.

In addition, introduce the output current that self-adaptive current multiple circuit also can increase operational amplifier, at steady state, be 5 times of PMOS MP11 and NMOS tube MN12 by the distribution of current of PMOS MP13 and NMOS tube MN13, therefore operational amplifier output current expression formula is as follows:

I _oa＝5K[(V _OV+ΔV _OUT) ²-(V _OV-ΔVOUT) ²]＝20KV _OVΔV _OUT(6)

Wherein K is the mutual conductance of NMOS tube MN8 and MN9, V _oVthe overdrive voltage of operational amplifier input to pipe NMOS tube MN8 and MN9, Δ V _oUTbeing output voltage difference, in order to suppress output voltage upper punch and undershoot, needing to increase Ioa and Δ V _oUTscale-up factor, one of them method increases operational amplifier output-parallel number, and then this method can increase operational amplifier mutual conductance g _m1, reduce phase margin, another one method is exactly increase the overdrive voltage V of operational amplifier input to pipe _oV, can in be downloaded to heavy duty time introduce self-adaptive current multiple circuit and realize.

Therefore, self-adaptive current multiple circuit not only increases in voltage stabilizer gain bandwidth product when being downloaded to heavy duty, also can increase operational amplifier driving force, stability during underloading can not be affected simultaneously, introduce the transient response performance that self-adaptive current multiple circuit significantly can increase voltage stabilizer.

Simulating, verifying is carried out to the low pressure difference linear voltage regulator of the present invention's a kind of self-adaptive current multiple circuit and this circuit integrated below, the process environments of its checking is: verify under a kind of standard 0.13 μm of CMOS technology, the threshold voltage of NMOS tube and PMOS is 0.3V.

Under different load conditions, the result of frequency response as shown in Figure 5 for a kind of low pressure difference linear voltage regulator of integrated adaptive current multiplication circuit.Wherein RFB1 is that 0, RFB2 removes, and voltage stabilizer exports VOUT and is directly connected to feedback end VFB, and external reference voltages is 0.6V, and supply voltage VDD is 0.8V.When load current IL is 100 μ A, self-adaptive current multiple circuit cuts out, and voltage stabilizer DC current gain is 62dB, and gain bandwidth product is 800kHz, and phase margin is 62 °.When load current IL is 2mA, self-adaptive current multiple circuit is opened, DC current gain is 66dB, gain bandwidth product is increased to 7.3MHz, and phase margin is 60 °, when load current IL is increased to 100mA, because Correctional tube enters linear zone, DC current gain is reduced to 50dB, and gain bandwidth product is 3.4MHz, and phase margin is 81 °.

The low pressure difference linear voltage regulator of integrated adaptive current multiplication circuit load capacitance CL be 0 and 100pF a time, by underloading to heavy duty load transient response as shown in Figure 6 and Figure 7, wherein RFB1 is that 0, RFB2 removes.Supply voltage VDD is 0.8V, output voltage VO UT is 0.6V, and load current IL scope is 100 μ A to 100mA.Under underloading, the quiescent current of low pressure difference linear voltage regulator is only 1.5 μ A, and owing to introducing self-adaptive current multiple circuit, full load, low pressure difference linear voltage regulator quiescent current is increased to 14 μ A.When load current switches between 100 μ A and 100mA, output voltage undershoot is 100mV, and output voltage overshoot is 50mV, and Time Created is 1 μ s.

The low pressure difference linear voltage regulator of integrated adaptive current multiplication circuit when load capacitance CL is 100pF, by be downloaded to heavy duty load transient response as shown in Figure 8, wherein RFB1 is that 0, RFB2 removes.Supply voltage VDD is 0.8V, output voltage VO UT is 0.6V.In when being downloaded to heavy duty, self-adaptive current multiple circuit is in opening always, and low pressure difference linear voltage regulator quiescent current is 14 μ A.When load current switches between 2mA and 100mA, output voltage undershoot is 40mV, output voltage overshoot is 45mV, Time Created is 1 μ s, self-adaptive current multiple circuit is in opening always, in be downloaded to heavy duty output voltage undershoot obviously reduce, transient response performance, especially carry response performance obviously promote.

Although be described the illustrative embodiment of the present invention above; so that those skilled in the art understand the present invention; but should be clear; the invention is not restricted to the scope of embodiment; to those skilled in the art; as long as various change to limit and in the spirit and scope of the present invention determined, these changes are apparent, and all innovation and creation utilizing the present invention to conceive are all at the row of protection in appended claim.

Claims (4)

1. a self-adaptive current multiple circuit, is characterized in that, comprising:

One constant bias voltage generative circuit, comprises PMOS MP4, PMOS MP5 and NMOS tube MN1;

The source electrode of PMOS MP4 and PMOS MP5 meets supply voltage VDD, and the grid of the drain electrode of PMOS MP4, the grid of PMOS MP4, PMOS MP5 is connected and is linked into outside constant-current bias source IB, for generating the constant bias voltage VBP of PMOS;

The drain electrode of PMOS MP5, the grid of NMOS tube MN1, drain electrode are connected with the grid of the NMOS tube MN2 in sluggish current comparator, are linked into the constant bias voltage VBN of NMOS tube;

The source ground of NMOS tube MN1;

One sluggish current comparator, comprises PMOS MP1, PMOS MP2 and NMOS tube MN2;

The source electrode of PMOS MP1, PMOS MP2 meets supply voltage VDD, the grid of PMOS MP1 meets voltage VG, and the grid of the NMOS tube MN4 that the drain electrode of the drain electrode of PMOS MP1, the drain electrode of PMOS MP2, NMOS tube MN2 and self-adaptive current double in generative circuit is all connected;

Grid and the self-adaptive current of PMOS MP2 double the grid of the PMOS MP3 in generative circuit, drain electrode, NMOS tube MN4 drain electrode be all connected, be linked into the self-adaptive current multiplier electrode VBPA of PMOS;

The source ground of NMOS tube MN2, the grid of NMOS tube MN2 is linked into NMOS tube constant bias voltage VBN;

One self-adaptive current multiplication generative circuit, comprises PMOS MP3 and NMOS tube MN3, NMOS tube MN4;

The source electrode of PMOS MP3 meets supply voltage VDD, and the drain electrode of the grid of PMOS MP3, the drain electrode of PMOS MP3, NMOS tube MN4 is all connected, is linked into the self-adaptive current multiplier electrode VBPA of PMOS;

The source ground of NMOS tube MN3, the drain electrode of NMOS tube MN3 connects the source electrode of NMOS tube MN4;

The grid of NMOS tube MN4 is all connected with the drain electrode of the PMOS MP1 in sluggish current comparator, the drain electrode of PMOS MP2, the drain electrode of NMOS tube MN2;

Self-adaptive current multiple circuit comprises constant bias voltage generative circuit, sluggish current comparator and self-adaptive current multiplication generative circuit; Constant bias voltage generative circuit is for generating the constant bias voltage of NMOS tube and PMOS; Sluggish current comparator first gathers fraction load current by PMOS MP1, the steady current formed with NMOS tube MN2 again compares, when load underloading, the grid voltage of NMOS tube MN4 is ground voltage, sluggish current comparator turns off self-adaptive current multiplication generative circuit by NMOS tube MN4, the self-adaptive current multiplier electrode VBPA of PMOS is raised, and operational amplifier bias current reduces, thus ensures stablize and reduce quiescent dissipation; When load by be downloaded to heavy duty time, increased by the electric current of PMOS MP1, the grid voltage of NMOS tube MN4 is supply voltage VDD, the complete conducting of NMOS tube MN4, sluggish current comparator opens self-adaptive current multiplication generative circuit by NMOS tube MN4, increased by the electric current of PMOS MP3, the self-adaptive current multiplier electrode VBPA of PMOS is reduced, operational amplifier bias current is increased to specific factor during underloading, the gain bandwidth product of low pressure difference linear voltage regulator increases, and transient response performance strengthens; Wherein, PMOS MP2 is for generation of sluggishness.

2. be integrated with a low pressure difference linear voltage regulator for self-adaptive current multiple circuit according to claim 1, it is characterized in that, comprising: operational amplifier, Correctional tube and potential-divider network;

Operational amplifier, Correctional tube and potential-divider network constitute degeneration factor jointly, for the output voltage VO UT of stabilizing low voltage difference linear stabilizer; Wherein, the inverting input of operational amplifier connects external reference voltages VREF, and in-phase input end connects low pressure difference linear voltage regulator feedback voltage V FB, and output terminal connects the grid of Correctional tube MP; Potential-divider network input end is that low pressure difference linear voltage regulator exports VOUT, and output terminal is low pressure difference linear voltage regulator feedback voltage V FB; The source electrode of Correctional tube MP connects outer power voltage VDD, and the drain electrode of Correctional tube MP is as the output terminal VOUT of low pressure difference linear voltage regulator.

3. a kind of low pressure difference linear voltage regulator being integrated with self-adaptive current multiple circuit according to claim 1 according to claim 2, it is characterized in that, described operational amplifier, comprising: PMOS MP6, PMOS MP7, PMOS MP8, PMOS MP9, PMOS MP10, PMOS MP11, PMOS MP12, PMOS MP13 and NMOS tube MN6, NMOS tube MN7, NMOS tube MN8, NMOS tube MN9, NMOS tube MN10, NMOS tube MN11, NMOS tube MN12, NMOS tube MN13;

The source electrode of PMOS MP6, PMOS MP7, PMOS MP8, PMOS MP9, PMOS MP10, PMOS MP11, PMOS MP12, PMOS MP13 is all connected to supply voltage VDD;

The drain electrode of PMOS MP6, the drain electrode of PMOS MP8, the drain electrode of NMOS tube MN6, the grid of NMOS tube MN10 are all connected;

The grid of PMOS MP6 and PMOS MP7 is connected respectively to the constant bias voltage VBP of PMOS;

The drain electrode of PMOS MP7, the drain electrode of PMOS MP9, the drain electrode of NMOS tube MN7, the grid of NMOS tube MN11 are all connected;

The grid of PMOS MP8 and PMOS MP9 is linked into the self-adaptive current multiplier electrode VBPA of PMOS respectively;

The drain electrode of PMOS MP10, the grid of PMOS MP10, the grid of PMOS MP12, the drain electrode of NMOS tube MN8 are all connected;

The drain electrode of PMOS MP11, the grid of PMOS MP11, the grid of PMOS MP13, the drain electrode of NMOS tube MN9 are all connected;

The drain electrode of PMOS MP12, the drain electrode of NMOS tube MN12, the grid of NMOS tube MN12, the grid of NMOS tube MN13 are all connected;

The grid of the drain electrode of PMOS MP13, the drain electrode of NMOS tube MN13, Correctional tube MP is all connected, meets voltage VG;

The grid of NMOS tube MN6, NMOS tube MN8 all meets external reference voltages VREF, and the drain electrode of the source electrode of NMOS tube MN6, the source electrode of NMOS tube MN9 and NMOS tube MN10 is all connected;

The grid of NMOS tube MN7, NMOS tube MN9 all connects low pressure difference linear voltage regulator feedback voltage V FB, and the drain electrode of the source electrode of NMOS tube MN7, the source electrode of NMOS tube MN8, NMOS tube MN11 is all connected;

The source electrode ground connection respectively of NMOS tube MN10, NMOS tube MN11, NMOS tube MN12, NMOS tube MN13.

4. a kind of low pressure difference linear voltage regulator being integrated with self-adaptive current multiple circuit according to claim 1 according to claim 2, it is characterized in that, described potential-divider network, comprising: the first divider resistance RFB1 and the second divider resistance RFB2;

One end of first divider resistance RFB1 is connected to low pressure difference linear voltage regulator and exports VOUT, and one end is connected to low pressure difference linear voltage regulator feedback voltage V FB in addition; One end of second divider resistance RFB2 is connected to low pressure difference linear voltage regulator feedback voltage V FB, and the other end is connected to ground.