CN116430945B - Low dropout linear voltage stabilizing circuit and power supply equipment - Google Patents

Low dropout linear voltage stabilizing circuit and power supply equipment Download PDF

Info

Publication number
CN116430945B
CN116430945B CN202310689794.6A CN202310689794A CN116430945B CN 116430945 B CN116430945 B CN 116430945B CN 202310689794 A CN202310689794 A CN 202310689794A CN 116430945 B CN116430945 B CN 116430945B
Authority
CN
China
Prior art keywords
current
nmos
tube
circuit
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202310689794.6A
Other languages
Chinese (zh)
Other versions
CN116430945A (en
Inventor
徐永志
梁源超
刘小妮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhuhai Zhirong Technology Co ltd
Original Assignee
Zhuhai Zhirong Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhuhai Zhirong Technology Co ltd filed Critical Zhuhai Zhirong Technology Co ltd
Priority to CN202310689794.6A priority Critical patent/CN116430945B/en
Publication of CN116430945A publication Critical patent/CN116430945A/en
Application granted granted Critical
Publication of CN116430945B publication Critical patent/CN116430945B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses a low-dropout linear voltage stabilizing circuit and power supply equipment, and belongs to the technical field of electronics. The low dropout linear voltage regulator circuit includes: an NMOS adjusting tube; the bias circuit is electrically connected with the NMOS adjusting tube and is configured to provide a first bias current according to the load current of the NMOS adjusting tube, and the first bias current is inversely related to the load current; and the feedback control circuit is respectively and electrically connected with the NMOS adjusting tube and the bias circuit, and is configured to generate a control signal according to an output feedback signal of the NMOS adjusting tube, a reference signal and a first bias current, and adjust the grid voltage of the NMOS adjusting tube by utilizing the control signal. By positively correlating the zero point of the transfer function of the output feedback signal to the grid electrode of the NMOS adjusting tube with the load current, the tracking of the zero point to the output pole is realized, the bandwidth is widened, the loop stability and the response speed are improved, and the ripple wave of the output voltage is reduced.

Description

Low dropout linear voltage stabilizing circuit and power supply equipment
Technical Field
The invention belongs to the technical field of electronics, and particularly relates to a low-dropout linear voltage stabilizing circuit and power supply equipment.
Background
Low dropout linear voltage regulator (low dropout regulator, ldo) has been widely used in integrated circuit design because of its low power consumption, low ripple, low noise, and other advantages. ldo circuits are generally classified as either off-chip capacitors or off-chip capacitors. The ldo circuit output end of the off-chip capacitor is often reserved with a pin plug-in compensation capacitor, and the plug-in compensation capacitor is used for improving loop stability and reducing ripple voltage of a load end during light load, but the plug-in compensation capacitor often reaches uF level and is difficult to integrate.
With the development of consumer portable products, in order to provide longer endurance time, the space occupied by the battery is larger and larger, and the space reserved for the plate electrode is reduced; in addition, with the advent of increasingly miniaturized packages, pin space resources are limited. In particular in SOC designs, ldo often only powers the digital circuitry inside the chip, and the external pins and external capacitors can severely waste packaging and board space. Low dropout linear regulators (capless ldo) without off-chip capacitors are increasingly used, but loop stability and load side ripple voltage of such low dropout linear regulators are difficult to guarantee.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art. Therefore, the invention provides the low-dropout linear voltage stabilizing circuit and the power supply device, which improve the loop stability, can effectively expand the bandwidth of the loop and improve the response speed of the loop; and when the load jumps, the ripple wave of the output voltage can be effectively reduced.
In a first aspect, the present invention provides a low dropout linear voltage regulator circuit, comprising: an NMOS adjusting tube; the bias circuit is electrically connected with the NMOS adjusting tube and is configured to provide a first bias current according to the load current of the NMOS adjusting tube, and the first bias current is inversely related to the load current; and the feedback control circuit is respectively and electrically connected with the NMOS adjusting tube and the bias circuit, and is configured to generate a control signal according to an output feedback signal of the NMOS adjusting tube, a reference signal and a first bias current and adjust the grid voltage of the NMOS adjusting tube by utilizing the control signal, wherein a zero point of a transfer function from the output feedback signal to the control signal in the feedback control circuit is inversely related to the first bias current.
According to the low-dropout linear voltage stabilizing circuit, the bias circuit and the feedback control circuit are designed, so that the zero point of the transfer function from the output feedback signal to the control signal in the feedback control circuit is positively correlated with the load current of the NMOS adjusting tube in a certain range, the tracking of the zero point to the output pole is realized, the loop stability is improved, the bandwidth of the loop can be effectively expanded, and the response speed of the loop is improved; and when the load jumps, the ripple wave of the output voltage can be effectively reduced.
According to one embodiment of the present invention, a feedback control circuit includes: the feedback circuit is electrically connected with the NMOS adjusting tube and is configured to generate an output feedback signal according to the output voltage of the NMOS adjusting tube; the first operational amplifier circuit is electrically connected with the feedback circuit and is configured to generate a first amplified signal according to a difference value between an output feedback signal and a reference signal; the second operational amplifier circuit is respectively and electrically connected with the first operational amplifier circuit and the NMOS adjusting tube and is configured to amplify the first amplified signal to generate a second amplified signal; the feedforward circuit is respectively and electrically connected with the feedback circuit, the bias circuit and the NMOS adjusting tube, and is configured to generate a feedforward signal according to the difference value between the output feedback signal and the reference signal under the adjustment of the first bias current, the transconductance of the feedforward circuit is larger than that of the first operational amplifier circuit, and the transconductance of the feedforward circuit and the first bias current are in positive correlation; the second amplified signal and the feedforward signal are combined and used for controlling the NMOS adjusting tube.
According to an embodiment of the present invention, a first operational amplifier circuit includes: the first differential pair transistor is configured to be connected with a second bias current and generate a corresponding first current and a second current under the control of a reference signal and an output feedback signal respectively; the first current mirror unit is electrically connected with the first differential pair tube and is configured to be connected with a first current and provide a corresponding first mirror current; the second current mirror unit is electrically connected with the first differential pair tube and is configured to be connected with a second current and provide a corresponding second mirror current; the output end of the first current mirror unit is electrically connected with the output end of the second current mirror unit, and the output end of the first current mirror unit and the output end of the second current mirror unit are used for providing a first amplified signal.
According to an embodiment of the present invention, the second operational amplifier circuit includes: the third current mirror unit is electrically connected with the first differential pair tube and is configured to be connected with the second current and provide a corresponding third mirror current; the drain electrode of the NMOS tube is respectively and electrically connected with the output end of the third current mirror unit and the grid electrode of the NMOS adjusting tube, the grid electrode of the NMOS tube is used for accessing the first amplified signal, and the source electrode of the NMOS tube is grounded.
According to one embodiment of the invention, the second operational circuit is connected in parallel with a miller compensation capacitor.
According to one embodiment of the present invention, a feed forward circuit includes: the source electrode of the PMOS tube is used for being connected with input voltage, and the grid electrode of the PMOS tube is biased by voltage formed by the first bias current; the second differential pair transistor is electrically connected with the drain electrode of the PMOS transistor and is configured to generate corresponding third current and fourth current under the control of a reference signal and an output feedback signal respectively based on third bias current provided by the PMOS transistor; the fourth current mirror unit is electrically connected with the second differential pair transistor, is configured to be connected with a third current and provides a fourth mirror current; a fifth current mirror unit electrically connected to the second differential pair of transistors and configured to access a fourth current and provide a fifth mirror current; the output end of the fourth current mirror unit and the output end of the fifth current mirror unit are electrically connected with the grid electrode of the NMOS adjusting tube, and the output end of the fourth current mirror unit and the output end of the fifth current mirror unit are used for providing feedforward signals.
According to one embodiment of the present invention, a bias circuit includes: the grid electrode and the source electrode of the NMOS mirror image tube are electrically connected with the grid electrode and the source electrode of the NMOS adjusting tube and are used for copying the load current of the NMOS adjusting tube in proportion; a sixth current mirror unit electrically connected with the NMOS mirror tube and configured to access a current flowing through the NMOS mirror tube and provide a sixth mirror current; a seventh current mirror unit configured to switch in a reference current and to provide a seventh mirror current; the output end of the sixth current mirror unit is electrically connected with the output end of the seventh current mirror unit, and the output end of the sixth current mirror unit and the output end of the seventh current mirror unit are used for providing a first bias current, wherein the first bias current is the difference between the seventh mirror current and the sixth mirror current.
According to one embodiment of the present invention, the reference current includes a first reference current and a second reference current, and the seventh current mirror unit includes: a cascode configured to access the first reference current and provide a seventh mirror current; and the drain electrode and the grid electrode of the NMOS bias tube are electrically connected and connected with a second reference current for providing bias voltage for the cascode tube.
According to one embodiment of the present invention, the low dropout linear voltage regulator circuit further includes: and the eighth current mirror unit is configured to switch in a reference current and provide a first reference current and a second reference current, and the ratio among the reference current, the first reference current and the second reference current is 1:1:1.
In a second aspect, the present invention provides a power supply apparatus comprising a low dropout linear regulator circuit according to the foregoing.
According to the power supply equipment, the low-dropout linear voltage stabilizing circuit with high stability, high bandwidth, high response speed and low output ripple voltage is adopted, so that the provided power supply is more reliable, and the power consumption requirement of the back-end circuit is ensured.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
FIG. 1 is a block diagram of a low dropout linear voltage regulator circuit according to an embodiment of the present invention;
FIG. 2 is a second block diagram of a low dropout linear voltage regulator circuit according to an embodiment of the present invention;
FIG. 3 is an equivalent schematic diagram of a low dropout linear voltage regulator circuit according to an embodiment of the present invention;
FIG. 4 is a schematic circuit diagram of a main feedback circuit provided by an embodiment of the present invention;
FIG. 5 is a schematic circuit diagram of a feedforward circuit provided by an embodiment of the present invention;
fig. 6 is a schematic circuit diagram of a bias circuit according to an embodiment of the present invention.
Reference numerals:
the device comprises an NMOS adjusting tube 100, a biasing circuit 200, a feedback control circuit 300, a feedback circuit 310, a first operational amplifier circuit 320, a second operational amplifier circuit 330 and a feedforward circuit 340.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
Referring to fig. 1, one embodiment of the present invention provides a low dropout linear voltage regulator circuit.
In this embodiment, the low dropout linear regulator circuit includes an NMOS regulator 100, a bias circuit 200, and a feedback control circuit 300, where the bias circuit 200 is electrically connected to the NMOS regulator 100 and configured to provide a first bias current according to a load current of the NMOS regulator 100, the first bias current being inversely related to the load current; the feedback control circuit 300 is electrically connected to the NMOS regulator 100 and the bias circuit 200, respectively, and is configured to generate a control signal according to the output feedback signal, the reference signal, and the first bias current of the NMOS regulator 100, and adjust the gate voltage of the NMOS regulator 100 by using the control signal, where a zero point of a transfer function from the output feedback signal to the control signal in the feedback control circuit 300 is inversely related to the first bias current.
In this embodiment, an NMOS (N-Metal-Oxide-Semiconductor) transistor is used as the adjustment tube. The drain electrode of the NMOS adjusting tube 100 is used for being connected with an input power supply, the source electrode of the NMOS adjusting tube 100 is used for providing an output power supply, and the grid electrode of the NMOS adjusting tube 100 is connected with the feedback control circuit 300.
The NMOS regulator 100 is in a saturation region under the control of the feedback control circuit 300, and its output voltage is controlled by the gate voltage. The feedback control circuit 300 adjusts the gate voltage of the NMOS regulator 100 by using the control signal to stabilize the output voltage. The output impedance of the NMOS tuning tube 100 decreases with increasing load current, i.e., the output pole moves toward low frequency with decreasing load current.
It should be noted that, the output feedback signal is used to represent the actual output voltage of the NMOS regulator 100, and the reference signal is used to represent the desired output voltage of the NMOS regulator 100. The output feedback signal and the reference signal may be voltage signals. The feedback control circuit 300 controls the NMOS regulator 100 in a negative feedback manner, and adjusts the NMOS regulator 100 according to a difference between the output feedback signal and the reference signal, so that the actual output voltage of the NMOS regulator 100 is stabilized at the desired output voltage.
In the present embodiment, the output feedback signal is an input signal of the feedback control circuit 300, the control signal is an output signal of the feedback control circuit 300, and the control signal is applied to the gate of the NMOS regulator 100 to control the on state of the NMOS regulator 100. The output feedback signal and the control signal satisfy formula (1):
（1）
wherein V is g Representing control signals, V fb Representing the output feedback signal, f (x) is the transfer function.
The bias circuit 200 is designed to provide a bias current inversely related to the load current. Meanwhile, the feedback control circuit 300 is designed such that the zero point of the transfer function from the output feedback signal to the control signal is inversely related to the first bias current. Thus, the zero point of the transfer function is positively correlated with the load current.
When the load current of the NMOS adjusting tube 100 increases, the output pole gradually moves towards high frequency, and at the same time, the zero point of the transfer function also moves towards high frequency; when the load current of the NMOS regulator 100 decreases, the output pole gradually moves toward the low frequency, and at the same time, the zero point of the transfer function also moves toward the low frequency. Whereby the zero frequency can track the output pole variation of the NMOS trim pipe 100.
According to the low-dropout linear voltage stabilizing circuit, the bias circuit 200 and the feedback control circuit 300 are designed, so that the zero point of the transfer function from the output feedback signal to the control signal in the feedback control circuit 300 is positively correlated with the load current of the NMOS regulating tube 100, the tracking of the zero point to the output pole is realized, the loop stability is improved, the bandwidth of the loop can be effectively expanded, and the response speed of the loop is improved; and when the load jumps, the ripple wave of the output voltage can be effectively reduced.
Referring to fig. 2, the present invention proposes a design scheme of a feedback control circuit 300.
In some embodiments, the feedback control circuit 300 includes a feedback circuit 310, a first operational amplifier circuit 320, a second operational amplifier circuit 330, and a feed-forward circuit 340, the feedback circuit 310 being electrically connected to the NMOS trim pipe 100 and configured to generate an output feedback signal from an output voltage of the NMOS trim pipe 100; the first operational amplifier circuit 320 is electrically connected to the feedback circuit 310 and configured to generate a first amplified signal according to a difference between the output feedback signal and a reference signal; the second operational amplifier circuit 330 is electrically connected to the first operational amplifier circuit 320 and the NMOS regulator 100, respectively, and is configured to amplify the first amplified signal to generate a second amplified signal; the feedforward circuit 340 is electrically connected to the feedback circuit 310, the bias circuit 200 and the NMOS regulator 100, respectively, and is configured to generate a feedforward signal according to a difference between the output feedback signal and the reference signal under the adjustment of the first bias current, wherein the transconductance of the feedforward circuit 340 is greater than the transconductance of the first operational amplifier circuit 320, and the transconductance of the feedforward circuit 340 is in positive correlation with the first bias current; the second amplified signal and the feedforward signal are combined to control the NMOS trim pipe 100.
In this embodiment, the first operational amplifier 320 and the second operational amplifier 330 form a main feedback circuit, and the output of the main feedback loop and the output of the feedforward circuit 340 jointly control the NMOS regulator 100. The feedforward circuit 340 generates a feedforward signal under the influence of the first bias current, the feedforward signal being used to assist the second amplified signal. The feedback control principle is a mature technology, and this embodiment is not described in detail here.
Referring to fig. 3, fig. 3 shows an equivalent circuit diagram of a low dropout linear voltage regulator circuit. To facilitate small signal analysis, the feedback loop is disconnected. The first resistor R1 and the second resistor R2 form a feedback circuit 310 for providing an output feedback signal V by using the voltage division principle fb 。A v1 Is a first operational amplifier, which corresponds to the first operational amplifier circuit 320; a is that v2 Is a second operational amplifier corresponding to the second operational amplifier circuit 330; r is (r) o1 Representing a first operational amplifier A v1 Output impedance of (a); g m1 And g m2 Respectively denoted as first operational amplifier A v1 And a second operational amplifier A v2 Is a transconductance of (2); a is that vf1 Representing a feed forward circuit 340; r is (r) o2 Representing a second operational amplifier A v2 And the output impedance of feed forward circuit 340; g mf1 A transconductance represented as feed forward circuit 340; APBC (antiphase bias circuit) the bias circuit 200; a is that v3 An NMOS tuning tube 100; g m3 A transconductance represented as NMOS trim tube 100; c (C) g Representation A v2 And A vf1 The sum of the output capacitance and the input capacitance of the NMOS trim transistor 100. Since the NMOS tuning tube 100 is much larger in size than the output tubes of the second operational amplifier circuit 330 and the feedforward circuit 340, C is g The capacitance is mainly occupied by the gate capacitance of the NMOS adjusting tube 100, C m Compensating the capacitance for miller. Based on kirchhoff's voltage and current law, V is given by the following formula (2) fb To V g Is a small signal transfer function of (2):
（2）
wherein S is a Laplace parameter. As can be seen from equation (2), the transfer function will appear to be a zero point under the combined action of the main feedback circuit and the feedforward circuit 340, and if g mf1 Greater than g m1 When the zero lies in the left half plane, equation (3) gives the zero frequency position:
（3）
g m1 g m2 r o1 gain g, denoted as first stage of the main feedback circuit m1 *r o1 And transconductance g of the second stage m2 Product, in the circuit design process, is generally g m1 r o1 Far greater than 1 and g m2 And g mf1 The order of magnitude is equivalent, so g m1 g m2 r o1 And g is equal to mf1 The sum is mainly composed of g m1 g m2 r o1 Occupied, the zero point can be further simplified to equation (4):
（4）
as can be seen from (4), the zero point generated by the feedforward circuit 340 and the main feedback circuit and g of the feedforward circuit 340 mf1 Are inversely related to g mf1 Is positively correlated with the bias current of the feed-forward circuit 340 and, therefore, the zero is inversely correlated with the bias current of the feed-forward circuit 340.
In one placeIn some embodiments, the second operational amplifier 330 is connected in parallel with a miller compensation capacitor C m 。
V fb To V g The Q value of the transfer function is given by equation (5),
（5）
（6）
（7）
in the circuit design process, the miller compensation circuit C m >C g As can be seen from equation (5), the Q value is easily less than 0.5 (the circuit gain level is typically greater than 10, i.e., g m2 *r o1 >10，g m2 *r o2 >10 And therefore V fb To V g The transfer function of (2) has two poles separated by the left half plane, the pole positions are shown in equations (6) and (7), and P n As dominant pole, P nd Is a non-dominant pole. For small and medium scale digital circuit design, the current provided by ldo is not excessive, C g The capacitance is typically of the order of pF, by providing a Miller compensation capacitance C m Non-principal pole point P nd Pushing to a position outside the loop bandwidth, and ensuring the loop stability.
In some embodiments, the first operational amplifier 320 includes a first differential pair of transistors configured to be connected to a second bias current and generate corresponding first and second currents under control of a reference signal and an output feedback signal, respectively; the first current mirror unit is electrically connected with the first differential pair tube and is configured to be connected with a first current and provide a corresponding first mirror current; the second current mirror unit is electrically connected with the first differential pair tube and is configured to be connected with a second current and provide a corresponding second mirror current; the output end of the first current mirror unit is electrically connected with the output end of the second current mirror unit, and the output end of the first current mirror unit and the output end of the second current mirror unit are used for providing a first amplified signal.
In this embodiment, the reference signal and the output feedback signal are respectively supplied to two transistors in the first differential pair transistor to control the second bias current, and generate the first current and the second current. The first current and the second current are combined into a first amplified signal after at least one mirror copy, the first amplified signal being used to characterize the difference between the reference signal and the output feedback signal.
Referring to fig. 4, in some embodiments, the first differential pair of tubes includes a first PMOS tube PM1 and a second PMOS tube PM2. Grid access reference signal V of first PMOS tube PM1 ref The grid electrode of the second PMOS tube PM2 is connected with an output feedback signal V fb . The source electrode of the first PMOS tube PM1 is connected with the source electrode of the second PMOS tube PM2 and is used for accessing a second bias current, the drain electrode of the first PMOS tube PM1 provides a first current, and the drain electrode of the second PMOS tube PM2 provides a second current.
The first current mirror unit comprises a first NMOS tube NM1, a third NMOS tube NM3, a third PMOS tube PM3 and a fourth PMOS tube PM4, wherein the drain electrode and the grid electrode of the first NMOS tube NM1 are connected with the drain electrode of the first PMOS tube PM1, the grid electrode of the third NMOS tube NM3 is connected with the grid electrode of the first NMOS tube NM1, the source electrode of the first NMOS tube NM1 and the source electrode of the third NMOS tube NM3 are grounded, the grid electrode of the third PMOS tube PM3 is respectively connected with the drain electrode of the third PMOS tube PM3, the drain electrode of the third NMOS tube NM3 and the grid electrode of the fourth PMOS tube PM4, and the source electrode of the third PMOS tube PM3 and the source electrode of the fourth PMOS tube PM4 are connected with input voltage.
The first NMOS tube NM1 and the third NMOS tube NM3 form a current mirror, the third PMOS tube PM3 and the fourth PMOS tube PM4 form a current mirror, the first current forms a first mirror current after mirror image replication twice, and the drain electrode of the fourth PMOS tube PM4 provides the first mirror current.
The second current mirror unit comprises a second NMOS tube NM2 and a fourth NMOS tube NM4, wherein the drain electrode and the grid electrode of the second NMOS tube NM2 are connected with the drain electrode of the second PMOS tube PM2, the grid electrode of the fourth NMOS tube NM4 is connected with the grid electrode of the second NMOS tube NM2, and the source electrode of the second NMOS tube NM2 and the source electrode of the fourth NMOS tube NM4 are grounded.
The second NMOS transistor NM2 and the fourth NMOS transistor NM4 form a current mirror, the second current forms a second mirror current after one mirror copy, and the drain of the fourth NMOS transistor NM4 provides the second mirror current.
In this embodiment, the NMOS regulator 100 is a seventh NMOS transistor NM7, the feedback circuit 310 includes a first resistor R1 and a second resistor R2 connected in series, a first end of the first resistor R1 is connected to the source of the seventh NMOS transistor NM7, a second end of the first resistor R1 is connected to a first end of the second resistor R2, and a second end of the second resistor R2 is grounded. The junction of the first resistor R1 and the second resistor R2 is used for providing an output feedback signal V fb 。
In some embodiments, the second operational amplifier 330 includes a third current mirror unit and a sixth NMOS transistor NM6, the third current mirror unit being electrically connected to the first differential pair of transistors and configured to source the second current and provide a corresponding third mirrored current; the drain electrode of the sixth NMOS transistor NM6 is electrically connected to the output end of the third current mirror unit and the gate electrode of the NMOS regulator 100, respectively, and the gate electrode of the sixth NMOS transistor NM6 is used for accessing the first amplified signal, and the source electrode of the sixth NMOS transistor NM6 is grounded.
In some embodiments, the third current mirror unit includes a fifth NMOS transistor NM5, a fifth PMOS transistor PM5, and a sixth PMOS transistor PM6. The gate of the fifth NMOS tube NM5 is connected with the gate of the second NMOS tube NM2, and the source electrode of the fifth NMOS tube NM5 is grounded. The grid electrode of the fifth PMOS tube PM5 is respectively connected with the drain electrode of the fifth PMOS tube PM5, the drain electrode of the fifth NMOS tube NM5 and the grid electrode of the sixth PMOS tube PM6, and the source electrode of the fifth PMOS tube PM5 and the source electrode of the sixth PMOS tube PM6 are connected with input voltages.
The fifth NMOS tube NM5 and the second NMOS tube NM2 form a current mirror, the fifth PMOS tube PM5 and the sixth PMOS tube PM6 form a current mirror, the second current forms a third mirror current after mirror image replication twice, and the drain electrode of the sixth PMOS tube PM6 provides the third mirror current.
The drain electrode of the sixth NMOS transistor NM6 is electrically connected to the drain electrode of the sixth PMOS transistor PM6 and the gate electrode of the seventh NMOS transistor NM7, respectively, and the gate electrode of the sixth NMOS transistor NM6 is connected to the drain electrode of the fourth PMOS transistor PM 4.
In some embodiments, the feed-forward circuit 340 includes a PMOS transistor, a second differential pair transistor, a fourth current mirror unit, and a fifth current mirror unit, where a source of the PMOS transistor is used for accessing an input voltage, and a gate of the PMOS transistor is biased by a voltage formed by the first bias current; the second differential pair transistor is electrically connected with the drain electrode of the PMOS transistor and is configured to generate corresponding third current and fourth current under the control of a reference signal and an output feedback signal respectively based on third bias current provided by the PMOS transistor; the fourth current mirror unit is electrically connected with the second differential pair tube and is configured to be connected with a third current and provide a fourth mirror current; the fifth current mirror unit is electrically connected with the second differential pair tube and is configured to access a fourth current and provide a fifth mirror current; the output end of the fourth current mirror unit and the output end of the fifth current mirror unit are electrically connected with the grid electrode of the NMOS adjusting tube 100, and the output end of the fourth current mirror unit and the output end of the fifth current mirror unit are used for providing feedforward signals.
In this embodiment, the reference signal and the output feedback signal are respectively supplied to two transistors in the second differential pair transistor to control the third bias current, and generate a third current and a fourth current. The third current and the fourth current are combined into a feedforward signal after at least one mirror image copy, and the feedforward signal is used for representing the difference value between the reference signal and the output feedback signal.
In some embodiments, the feed-forward circuit 340 and the first operational amplifier 320 may be in the same circuit configuration, differing in that the feedback signal V is output fb And reference signal V ref Is opposite to the access location of (a). Thus, the phase of the feed forward signal and the first amplified signal are opposite.
Referring to fig. 5, in some embodiments, the PMOS transistor is a fifteenth PMOS transistor PM15, a source of the fifteenth PMOS transistor PM15 is used to access an input voltage, and a gate of the fifteenth PMOS transistor PM15 is biased by a voltage formed by the first bias current. The first bias current provided by the bias circuit 200 is used for driving the fifteenth PMOS transistor PM15 and adjusting the current flowing through the fifteenth PMOS transistor PM15 to provide a third bias current.
The second differential pair pipe comprises an eleventh PMOS pipe PM11 and a twelfth PMOS pipe PM12. The grid of the eleventh PMOS tube PM11 is connected with an output feedback signal V fb Grid access reference signal V of twelfth PMOS tube PM12 ref . The source electrode of the eleventh PMOS tube PM11 is connected with the source electrode of the twelfth PMOS tube PM12 and is used for accessing a third bias current, the drain electrode of the eleventh PMOS tube PM11 provides a third current, and the drain electrode of the twelfth PMOS tube PM12 provides a fourth current.
The fourth current mirror unit comprises an eleventh NMOS tube NM11, a thirteenth NMOS tube NM13, a thirteenth PMOS tube PM13 and a fourteenth PMOS tube PM14, wherein the drain electrode and the grid electrode of the eleventh NMOS tube NM11 are connected with the drain electrode of the eleventh PMOS tube PM11, the grid electrode of the thirteenth NMOS tube NM13 is connected with the grid electrode of the eleventh NMOS tube NM11, the source electrode of the eleventh NMOS tube NM11 and the source electrode of the thirteenth NMOS tube NM13 are grounded, the grid electrode of the thirteenth PMOS tube PM13 is respectively connected with the drain electrode of the thirteenth PMOS tube PM13, the drain electrode of the thirteenth NMOS tube NM13 and the grid electrode of the fourteenth PMOS tube PM14, and the source electrode of the thirteenth PMOS tube PM13 and the source electrode of the fourteenth PMOS tube PM14 are connected with input voltages.
The eleventh NMOS transistor NM11 and the thirteenth NMOS transistor NM13 form a current mirror, the thirteenth PMOS transistor PM13 and the fourteenth PMOS transistor PM14 form a current mirror, the third current forms a fourth mirror current after mirror image replication twice, and the drain of the fourteenth PMOS transistor PM14 provides the fourth mirror current.
The fifth current mirror unit includes a twelfth NMOS transistor NM12 and a fourteenth NMOS transistor NM14, wherein the drain and the gate of the twelfth NMOS transistor NM12 are both connected to the drain of the twelfth PMOS transistor PM12, the gate of the fourteenth NMOS transistor NM14 is connected to the gate of the twelfth NMOS transistor NM12, and the source of the twelfth NMOS transistor NM12 and the source of the fourteenth NMOS transistor NM14 are grounded.
The twelfth NMOS transistor NM12 and the fourteenth NMOS transistor NM14 form a current mirror, the fourth current forms a fifth mirror current after one mirror copy, and the drain of the fourteenth NMOS transistor NM14 provides the fifth mirror current. The copy proportion of each current mirror can be set according to the requirement.
In some embodiments, the bias circuit 200 includes an NMOS mirror, a sixth current mirror, and a seventh current mirror, where the gate and the source of the NMOS mirror are electrically connected to the gate and the source of the NMOS trim transistor 100, for scaling the load current of the NMOS trim transistor 100; the sixth current mirror unit is electrically connected with the NMOS mirror tube and is configured to access the current flowing through the NMOS mirror tube and provide a sixth mirror current; a seventh current mirror unit configured to switch in a reference current and to provide a seventh mirror current; the output end of the sixth current mirror unit is electrically connected with the output end of the seventh current mirror unit, and the output end of the sixth current mirror unit and the output end of the seventh current mirror unit are used for providing a first bias current, wherein the first bias current is the difference between the seventh mirror current and the sixth mirror current.
In this embodiment, the present invention is not limited to this embodiment. First bias current = seventh mirror current-sixth mirror current, the difference between the seventh mirror current and the sixth mirror current being used to form the first bias current. Since the NMOS mirror is used to replicate the load current, the sixth mirror current is positively correlated with the load current, and the first bias current is inversely correlated with the sixth mirror current, whereby the first bias current is inversely correlated with the load current.
Referring to fig. 6, in some embodiments, the NMOS mirror is a twenty-ninth NMOS transistor NM29, the gate of the twenty-ninth NMOS transistor NM29 is connected to the gate of the seventh NMOS transistor NM7, and the source of the twenty-ninth NMOS transistor NM29 is connected to the source of the seventh NMOS transistor NM 7.
In the present embodiment, the first bias current flows through the twenty-sixth PMOS transistor PM26 in a diode-connected manner to provide the gate bias of the fifteenth PMOS transistor PM 15.
The sixth current mirror unit comprises a twenty-seventh PMOS tube PM27 and a twenty-eighth PMOS tube PM28, wherein the grid electrode of the twenty-eighth PMOS tube PM28 is respectively connected with the drain electrode of the twenty-eighth PMOS tube PM28, the drain electrode of the twenty-ninth NMOS tube NM29 and the grid electrode of the twenty-seventh PMOS tube PM27, and the source electrode of the twenty-seventh PMOS tube PM27 and the source electrode of the twenty-eighth PMOS tube PM28 are connected with input voltages.
The twenty-ninth NMOS transistor NM29 is configured to copy the load current of the seventh NMOS transistor NM7 in proportion, where the twenty-seventh PMOS transistor PM27 and the twenty-eighth PMOS transistor PM28 form a current mirror, and the load current forms a sixth mirror current through two mirrors.
In some embodiments, the reference current includes a first reference current Ib1 and a second reference current Ib2, the seventh current mirror employs a cascode configured to tap the first reference current Ib1 and provide a seventh mirrored current; the drain electrode and the grid electrode of the NMOS bias tube are electrically connected and connected with a second reference current Ib2 for providing bias voltage for the cascode tube.
With continued reference to fig. 6, in the present embodiment, the NMOS bias tube is a twenty-second NMOS tube NM22, and the cascode current mirror includes a twenty-third NMOS tube NM23, a twenty-fourth NMOS tube NM24, a twenty-fifth NMOS tube NM25, and a twenty-sixth NMOS tube NM26. The gate and the drain of the twenty-second NMOS transistor NM22 are connected to access the second reference current Ib2, and the drain of the twenty-fourth NMOS transistor NM24 is connected to access the first reference current Ib1. The grid electrode of the twenty-fourth NMOS tube NM24 is respectively connected with the grid electrode of the twenty-fifth NMOS tube NM25 and the drain electrode of the twenty-second NMOS tube NM22, the source electrode of the twenty-fourth NMOS tube NM24 is connected with the drain electrode of the twenty-third NMOS tube NM23, the grid electrode of the twenty-third NMOS tube NM23 is respectively connected with the grid electrode of the twenty-sixth NMOS tube NM26 and the drain electrode of the twenty-fourth NMOS tube NM24, the source electrode of the twenty-fifth NMOS tube NM25 is connected with the drain electrode of the twenty-sixth NMOS tube NM26, and the source electrodes of the twenty-second NMOS tube NM22, the twenty-third NMOS tube NM23 and the twenty-sixth NMOS tube NM26 are all grounded.
In this embodiment, the gate of the twenty-sixth PMOS transistor PM26 is connected to the drain of the twenty-sixth PMOS transistor PM26 and the gate of the fifteenth PMOS transistor PM15, respectively, and the twenty-sixth PMOS transistor PM26 and the fifteenth PMOS transistor PM15 form a current mirror. The current flowing through the source and drain of the twenty-sixth PMOS transistor PM26 is a first bias current equal to the difference between the current of NM25/NM26 and the current of PM27, which provides the gate voltage pgate of the fifteenth PMOS transistor PM15 of fig. 5 through PM 26.
As an example, the copy ratio between the twenty-ninth NMOS transistor NM29 and the seventh NMOS transistor NM7 may be 1: n1. If the load current of the low dropout linear regulator circuit is Iout, the currents flowing through the twenty-ninth NMOS transistor NM29 and the twenty-eighth PMOS transistor PM28 are approximately Iout/N1, and the twenty-seventh PMOS transistor PM27 and the twenty-eighth PMOS transistor PM28 are according to 1: n2 mirror image of the relationship, flow throughThe twenty-seventh PMOS transistor PM27 has a current Iout/(N1×n2). Ib1 and Ib2 are reference currents, assuming that they are Ibias, the twenty-second NMOS transistor NM22 provides gate voltages of the twenty-fourth NMOS transistor NM24 and the twenty-fifth NMOS transistor NM25, and assuming that the twenty-fifth NMOS transistor NM25 and the twenty-sixth NMOS transistor NM26 are mirror images of the twenty-fourth NMOS transistor NM24 and the twenty-third NMOS transistor NM23 according to N3:1, currents flowing through the twenty-fifth NMOS transistor NM25 and the twenty-sixth NMOS transistor NM26 are N3 x Ibias. Therefore, the current flowing through the twenty-sixth PMOS PM26 is N3×ibias-Iout/(N1×n2), and the twenty-sixth PMOS PM26 and the fifteenth PMOS PM15 may have the same size, so that the mirror ratio of the two is 1:1. Therefore, the current flowing through the fifteenth PMOS PM15 is also N3×ibias-Iout/(N1×n2). N1, N2, and N3 take a certain value to ensure transconductance g of feed-forward circuit 340 mf1 Is greater than the first operational amplifier A v1 Transconductance g of (2) m1 The zero generated by the feed-forward circuit is thus located in the left half plane, inversely related to the current N3 x Ibias-Iout/(N1 x N2).
In some embodiments, the low dropout linear regulator circuit further comprises: an eighth current mirror unit is configured to switch in the reference current Ibias and provide the first reference current Ib1 and the second reference current Ib2, and the ratio among the reference current Ibias, the first reference current Ib1 and the second reference current Ib2 is 1:1:1.
With continued reference to fig. 4, in this embodiment, the eighth current mirror unit may include a thirty-first PMOS pipe PM31, a thirty-second PMOS pipe PM32, a thirty-third PMOS pipe PM33, and a thirty-fourth PMOS pipe PM34. The grid electrode of the thirty-first PMOS tube PM31 is respectively connected with the drain electrode of the thirty-first PMOS tube PM31, the grid electrode of the thirty-second PMOS tube PM32, the grid electrode of the thirty-third PMOS tube PM33 and the grid electrode of the thirty-fourth PMOS tube PM34, the source electrode of the thirty-first PMOS tube PM31, the source electrode of the thirty-second PMOS tube PM32, the source electrode of the thirty-third PMOS tube PM33 and the source electrode of the thirty-fourth PMOS tube PM34 are connected with input voltages, and the drain electrode of the thirty-fourth PMOS tube PM34 is respectively electrically connected with the source electrode of the first PMOS tube PM1 and the source electrode of the second PMOS tube PM2. The drain of the thirty-second PMOS transistor PM32 provides a first reference current, the drain of the thirty-third PMOS transistor PM33 provides a second reference current, and the drain of the thirty-fourth PMOS transistor PM34 provides a second bias current.
The mirror image ratio of the thirty-first PMOS tube PM31, the thirty-second PMOS tube PM32 and the thirty-third PMOS tube PM33 is 1:1:1. Thus, ibias: ib1: ib2=1:1:1. The mirror ratio of the thirty-fourth PMOS PM34 to the thirty-first PMOS PM31 can be set according to the requirements.
The invention also provides power supply equipment which comprises the low-dropout linear voltage stabilizing circuit.
In some embodiments, the low dropout linear regulator circuit may be integrated in a power chip that is used to power an electrical device, which may be a chip or the like. Of course, the low dropout linear voltage regulator circuit can also be applied to other devices, and the specific structure of the low dropout linear voltage regulator circuit can refer to the foregoing embodiments, and this embodiment is not repeated here.
According to the power supply equipment, the low-dropout linear voltage stabilizing circuit with high stability, high bandwidth, high response speed and low output ripple voltage is adopted, so that the provided power supply is more reliable, and the power consumption requirement of the back-end circuit is ensured. Of course, the low dropout linear voltage regulator circuit may also adopt the technical solutions in the above embodiments, which also have corresponding technical effects.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present invention may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the invention, the scope of which is defined by the claims and their equivalents.

Claims (8)

1. A low dropout linear voltage regulator circuit, comprising:
an NMOS adjusting tube;
a bias circuit electrically connected to the NMOS trim tube and configured to provide a first bias current according to a load current of the NMOS trim tube, the first bias current inversely related to the load current;
the feedback control circuit is respectively and electrically connected with the NMOS adjusting tube and the bias circuit, and is configured to generate a control signal according to an output feedback signal of the NMOS adjusting tube, a reference signal and the first bias current, and adjust the grid voltage of the NMOS adjusting tube by utilizing the control signal, wherein a zero point of a transfer function from the output feedback signal to the control signal in the feedback control circuit is inversely related to the first bias current;
the feedback control circuit includes:
the feedback circuit is electrically connected with the NMOS adjusting tube and is configured to generate an output feedback signal according to the output voltage of the NMOS adjusting tube;
the first operational amplifier circuit is electrically connected with the feedback circuit and is configured to generate a first amplified signal according to the difference value between the output feedback signal and a reference signal;
the second operational amplifier circuit is respectively and electrically connected with the first operational amplifier circuit and the NMOS adjusting tube and is configured to amplify the first amplified signal to generate a second amplified signal;
the feedforward circuit is respectively and electrically connected with the feedback circuit, the bias circuit and the NMOS adjusting tube, and is configured to generate a feedforward signal according to the difference value between the output feedback signal and the reference signal under the adjustment of the first bias current, the transconductance of the feedforward circuit is larger than that of the first operational amplifier circuit, and the transconductance of the feedforward circuit and the first bias current form positive correlation;
the second amplified signal and the feedforward signal are combined and then used for controlling the NMOS adjusting tube;
the bias circuit includes:
the grid electrode and the source electrode of the NMOS mirror image tube are electrically connected with the grid electrode and the source electrode of the NMOS adjusting tube and are used for copying the load current of the NMOS adjusting tube in proportion;
a sixth current mirror unit electrically connected to the NMOS mirror and configured to access a current flowing through the NMOS mirror and provide a sixth mirror current;
a seventh current mirror unit configured to switch in a reference current and to provide a seventh mirror current;
the output end of the sixth current mirror unit is electrically connected with the output end of the seventh current mirror unit, and the output end of the sixth current mirror unit and the output end of the seventh current mirror unit are used for providing the first bias current, wherein the first bias current is the difference between the seventh mirror current and the sixth mirror current.
2. The low dropout linear regulator circuit according to claim 1, wherein said first operational amplifier circuit comprises:
the first differential pair transistor is configured to be connected with a second bias current and generate a corresponding first current and a second current under the control of the reference signal and the output feedback signal respectively;
the first current mirror unit is electrically connected with the first differential pair tube and is configured to access the first current and provide a corresponding first mirror current;
a second current mirror unit electrically connected to the first differential pair of tubes and configured to access the second current and provide a corresponding second mirrored current;
the output end of the first current mirror unit is electrically connected with the output end of the second current mirror unit, and the output end of the first current mirror unit and the output end of the second current mirror unit are used for providing the first amplified signal.
3. The low dropout linear regulator circuit according to claim 2, wherein said second operational amplifier circuit comprises:
a third current mirror unit electrically connected to the first differential pair of tubes and configured to access the second current and provide a corresponding third mirror current;
the drain electrode of the NMOS tube is respectively and electrically connected with the output end of the third current mirror unit and the grid electrode of the NMOS adjusting tube, the grid electrode of the NMOS tube is used for being connected with the first amplified signal, and the source electrode of the NMOS tube is grounded.
4. The low dropout linear regulator circuit according to claim 1, wherein said second operational amplifier circuit is connected in parallel with a miller compensation capacitor.
5. The low dropout linear regulator circuit according to claim 1, wherein said feed forward circuit comprises:
the source electrode of the PMOS tube is used for being connected with input voltage, and the grid electrode of the PMOS tube is biased by the voltage formed by the first bias current;
the second differential pair transistor is electrically connected with the drain electrode of the PMOS transistor and is configured to generate corresponding third current and fourth current under the control of the reference signal and the output feedback signal respectively based on third bias current provided by the PMOS transistor;
a fourth current mirror unit electrically connected to the second differential pair of tubes and configured to access the third current and provide a fourth mirrored current;
a fifth current mirror unit electrically connected to the second differential pair of tubes and configured to access the fourth current and provide a fifth mirrored current;
the output end of the fourth current mirror unit and the output end of the fifth current mirror unit are electrically connected with the grid electrode of the NMOS adjusting tube, and the output end of the fourth current mirror unit and the output end of the fifth current mirror unit are used for providing the feedforward signal.
6. The low dropout linear regulator circuit according to claim 1, wherein the reference current includes a first reference current and a second reference current, and the seventh current mirror unit includes:
a cascode configured to access the first reference current and provide the seventh mirrored current;
and the drain electrode and the grid electrode of the NMOS bias tube are electrically connected, and the second reference current is accessed to provide bias voltage for the cascode tube.
7. The low dropout linear regulator circuit according to claim 6, further comprising:
and an eighth current mirror unit configured to switch in a reference current and provide the first reference current and the second reference current, wherein the ratio among the reference current, the first reference current and the second reference current is 1:1:1.
8. A power supply apparatus characterized in that it comprises the low dropout linear regulator circuit according to any one of claims 1 to 7.
CN202310689794.6A 2023-06-12 2023-06-12 Low dropout linear voltage stabilizing circuit and power supply equipment Active CN116430945B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310689794.6A CN116430945B (en) 2023-06-12 2023-06-12 Low dropout linear voltage stabilizing circuit and power supply equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310689794.6A CN116430945B (en) 2023-06-12 2023-06-12 Low dropout linear voltage stabilizing circuit and power supply equipment

Publications (2)

Publication Number Publication Date
CN116430945A CN116430945A (en) 2023-07-14
CN116430945B true CN116430945B (en) 2023-09-01

Family

ID=87091107

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310689794.6A Active CN116430945B (en) 2023-06-12 2023-06-12 Low dropout linear voltage stabilizing circuit and power supply equipment

Country Status (1)

Country Link
CN (1) CN116430945B (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101853040A (en) * 2010-07-05 2010-10-06 复旦大学 High mains rejection ratio low dropout voltage linear voltage regulator with feedforward transconductance
CN103838287A (en) * 2013-12-10 2014-06-04 珠海全志科技股份有限公司 Linear voltage regulator for compensation zero point dynamic adjustment
CN104460802A (en) * 2014-11-27 2015-03-25 电子科技大学 Self-adapting current multiplication circuit and low-dropout-voltage linear voltage regulator integrating same
KR101592500B1 (en) * 2015-06-19 2016-02-11 중앙대학교 산학협력단 Low drop out regulator
CN113268102A (en) * 2021-02-21 2021-08-17 中山大学 Low-dropout linear regulator circuit with ultra-low power consumption and rapid transient response
CN113867465A (en) * 2021-10-13 2021-12-31 辽宁大学 LDO (low dropout regulator) module for in-chip adjustable bandwidth
CN115016594A (en) * 2022-07-22 2022-09-06 湖南芯力特电子科技有限公司 Low dropout linear regulator

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6661683B2 (en) * 2002-03-18 2003-12-09 Texas Instruments Incorporated Charge pump having very low voltage ripple
US8089261B2 (en) * 2009-05-13 2012-01-03 Lsi Corporation Low dropout regulator compensation circuit using a load current tracking zero circuit
US9122293B2 (en) * 2012-10-31 2015-09-01 Qualcomm Incorporated Method and apparatus for LDO and distributed LDO transient response accelerator

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101853040A (en) * 2010-07-05 2010-10-06 复旦大学 High mains rejection ratio low dropout voltage linear voltage regulator with feedforward transconductance
CN103838287A (en) * 2013-12-10 2014-06-04 珠海全志科技股份有限公司 Linear voltage regulator for compensation zero point dynamic adjustment
CN104460802A (en) * 2014-11-27 2015-03-25 电子科技大学 Self-adapting current multiplication circuit and low-dropout-voltage linear voltage regulator integrating same
KR101592500B1 (en) * 2015-06-19 2016-02-11 중앙대학교 산학협력단 Low drop out regulator
CN113268102A (en) * 2021-02-21 2021-08-17 中山大学 Low-dropout linear regulator circuit with ultra-low power consumption and rapid transient response
CN113867465A (en) * 2021-10-13 2021-12-31 辽宁大学 LDO (low dropout regulator) module for in-chip adjustable bandwidth
CN115016594A (en) * 2022-07-22 2022-09-06 湖南芯力特电子科技有限公司 Low dropout linear regulator

Also Published As

Publication number Publication date
CN116430945A (en) 2023-07-14

Similar Documents

Publication Publication Date Title
US7719241B2 (en) AC-coupled equivalent series resistance
WO2018129967A1 (en) Low drop-out linear voltage regulator
US20140091780A1 (en) Reference voltage generator
CN110174918B (en) Overshoot elimination circuit, undershoot elimination circuit and chip of low dropout linear voltage regulator
US20170371365A1 (en) Voltage regulator
US9256233B2 (en) Generating a root of an open-loop freqency response that tracks an opposite root of the frequency response
CN110945453B (en) LDO, MCU, fingerprint module and terminal equipment
CN109358689B (en) Self-bias peak detection circuit and low dropout linear regulator
US10996700B1 (en) Fast response linear regulator with bias current control and overshoot and undershoot suppression
CN110488908B (en) Low dropout regulator for improving transient response
CN114265460B (en) In-chip integrated frequency compensation adjustable low dropout regulator
CN103163926B (en) High-accuracy low drop-out voltage regulator
CN110825157B (en) Low dropout regulator based on heavy load compensation
CN110989756B (en) Low dropout regulator based on constant power protection
CN116430945B (en) Low dropout linear voltage stabilizing circuit and power supply equipment
CN110389614B (en) High-efficiency low dropout regulator
CN116027838A (en) Low dropout linear voltage regulator, voltage stabilizing system and dynamic compensation method of pole of voltage stabilizing system
CN111367342A (en) Low dropout linear voltage stabilizing circuit
CN115756057A (en) Transient response enhancement type LDO linear voltage regulator
CN115840483A (en) Low dropout regulator with transient enhancement characteristic
US20210226531A1 (en) Switching converter with adaptive compensation
US9541934B2 (en) Linear regulator circuit
CN114421897A (en) Circuit for reducing noise of integrated circuit amplifier and noise reduction method thereof
CN114115415B (en) Low dropout linear voltage stabilizing circuit
CN117826926B (en) Low-power consumption LDO circuit with double loop control

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant