CN110389614B - High-efficiency low dropout regulator - Google Patents

High-efficiency low dropout regulator Download PDF

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CN110389614B
CN110389614B CN201910644601.9A CN201910644601A CN110389614B CN 110389614 B CN110389614 B CN 110389614B CN 201910644601 A CN201910644601 A CN 201910644601A CN 110389614 B CN110389614 B CN 110389614B
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current mirror
circuit
current
nmos transistor
transistor
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CN110389614A (en
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肖知明
胡伟波
和雨
王宇
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Shenzhen Research Institute Of Nankai University
Nankai University
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Shenzhen Research Institute Of Nankai University
Nankai University
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

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Abstract

The invention provides a high-efficiency low dropout regulator, which comprises an output voltage regulating circuit, a voltage follower circuit, a voltage regulating circuit and a voltage regulating circuit, wherein the voltage follower circuit is used for regulating output voltage to be equal to input reference voltage; a positive feedback loop with stability independent of load capacitance and load current and loop gain below 1 and a gain attenuation circuit ensuring that the loop gain is less than 1; a minimum load current providing circuit for providing a load current at zero load; the output load current limiting circuit is used for overcurrent protection, and when the output load current exceeds a set threshold value, the circuit is turned off in time; the input current eliminating circuit is used for providing a voltage stabilizing structure with infinite input impedance; meanwhile, the bias current of the circuit is self-adaptive to the output load current, and the energy efficiency of the circuit is improved.

Description

High-efficiency low dropout regulator
Technical Field
The invention relates to the technical field of voltage regulators, in particular to a high-efficiency low dropout voltage regulator.
Background
With the advance of the process and the popularization of the very large scale integrated circuit, a low dropout regulator is required in various analog integrated circuits and digital-analog hybrid integrated circuit systems. This is because the voltage supplied directly from the external power supply to the circuit is not only unstable but also weak in the load carrying capability of the external power supply, and the low dropout regulator can supply a stable output voltage while having a strong load carrying capability. Most of the existing linear voltage regulators form a negative feedback loop with high low-frequency loop gain through an amplifier and a source follower, and the purpose of regulating output voltage by using target reference voltage is achieved. The closed regulation loop reduces the effective output impedance and helps maintain a stable output voltage over a wide range of load currents and supply voltages.
Most of the existing linear voltage regulators are based on a negative feedback loop, and the stability of the loop depends on output load capacitance. Furthermore, the load current of the low dropout regulator determines the output impedance and the location of the dominant pole, and thus in a system with dynamic current consumption it is difficult to maintain high loop gain and energy efficiency over a wide load current range. In a mixed signal system, the digital circuit portion is turned on and off irregularly, resulting in the load current of the low dropout regulator varying irregularly over time. Therefore, in order to maintain loop stability under the worst condition or at the highest possible load current, some indicators of gain and power consumption are sacrificed, thereby affecting other performances of the low dropout regulator, such as dc line/load regulation and transient response. Also, some applications may not provide off-chip capacitance due to pin limitations or solution size limitations, and the variation in load capacitance of low dropout regulators may make design difficult to optimize.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a low dropout voltage regulator circuit based on a positive feedback loop, in which a bias current can adaptively change with an output load current, so as to improve a plurality of technical indexes such as energy efficiency, a bearable load current range, and loop stability, and solve the problem of compromising the technical indexes and area in the original structure.
In order to achieve the purpose, the scheme of the application is as follows:
a high-efficiency low dropout regulator comprises an output voltage regulating circuit, a positive feedback loop and a gain attenuation circuit, wherein the voltage follower circuit is used for regulating an output voltage to be equal to an input reference voltage, the positive feedback loop is independent of a load capacitor and a load current, and the loop gain is lower than 1;
the output load current limiting circuit is used for overcurrent protection, and when the output load current exceeds a set threshold value, the circuit is turned off in time. A minimum load current providing circuit for providing a load current at zero load; the input current cancellation circuit is used for providing a voltage stabilization mode with infinite input impedance; meanwhile, the bias current of the circuit is self-adaptive to the output load current, and the energy efficiency of the circuit is improved.
Preferably, the output voltage regulating circuit comprises a first current mirror, a second current mirror and an NMOS transistor MN0；
The output current end of the slave current mirror branch A of the first current mirror and MN8AThe drain electrodes of the MOS tubes of the main current mirror branch circuits are communicated, and the grid electrodes of the MOS tubes of the main current mirror branch circuits are connected with an NMOS tube MN0A gate electrode of (1);
the grids of the MOS transistors of the main current mirror branch and the auxiliary current mirror branch of the second current mirror are connected with an NMOS transistor MN0Grid, input reference voltage is connected with current mirror MOS tube MN in main current mirror branch circuit1AThe output voltage end of the source electrode is positioned in a current mirror MOS tube MN in a slave current mirror branch circuit1BOf the substrate.
Preferably, the gain attenuation circuit is connected in series with the input reference voltage and the NMOS transistor MN0Resistance R between gates0And a capacitor Cc and an NMOS transistor MN1ASubstrate access resistance R0And a capacitor Cc.
Preferably, the minimum load current supply circuit includes a resistor R connected in series between the output voltage terminal and the negative power supply voltage VSS2。
Preferably, the input current cancellation circuit comprises a third current mirror, a fourth current mirror and a fifth current mirror,
the grid electrode of the current mirror MOS tube of the current mirror branch of the third current mirror is connected with the current mirror MOS tube MN of one slave current mirror branch of the fifth current mirror6CThe drain electrode of the third current mirror is connected with the current mirror branch cascode MOS tube MP3BIs connected to the input reference voltage; a current mirror MOS transistor MN of another current mirror branch of the fifth current mirror6BThe drain electrode of the second current mirror is connected with the grid electrode of the second current mirror;
the grid electrode of the MOS tube of the fourth current mirror is connected with the MP of the first slave current mirror branch C4CThe drain electrode of the fourth current mirror, and a cascode MOS (metal oxide semiconductor) transistor MN of a slave current mirror branch circuit of the fourth current mirror5AThe drain of which is connected to an input reference voltage.
Preferably, the first and second current mirrors, the third current mirror and the fourth current mirror are cascode current mirrors.
Preferably, the load current threshold generating circuit comprises an NMOS transistor MN having a gate and a fifth current mirror6BNMOS transistor MN with connected grid6AThe grid of the NMOS tube MN is connected with6AResistance R between and a negative supply voltage Vss1The NMOS tube MN6AAnd the gate and the drain of the first current mirror are connected to the input of the current mirror branch D of the first current mirror.
The embodiment of the invention has the following beneficial effects:
the invention establishes a voltage stabilization mode with loop stability independent of load capacitance and load current, simultaneously the bias current of the voltage stabilization mode is self-adaptive to the output load current, the energy efficiency of the circuit is improved, the internal self-carrying load current generating circuit can still normally work under the condition of zero external load, and the bearable range of the output load current is widened.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention as set forth above.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic structural diagram provided in an embodiment of the present invention;
FIG. 2 is a schematic diagram of a circuit connection according to an embodiment of the present invention;
fig. 3 is a simplified schematic diagram of the present invention.
Fig. 4 is an equivalent schematic diagram of a positive feedback loop.
FIG. 5 is an analysis chart.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
The invention relates to a high-efficiency low dropout regulator, which comprises,
an output voltage adjusting circuit including a voltage follower circuit for adjusting an output voltage to be equal to an input reference voltage, a positive feedback loop having a stability independent of a load capacitance and a load current and a loop gain lower than 1, and a gain attenuation circuit for ensuring the loop gain smaller than 1;
the output load current limiting circuit is used for overcurrent protection, and when the output load current exceeds a set threshold value, the circuit is turned off in time. A minimum load current providing circuit for providing a load current at zero load; the input current cancellation circuit is used for providing a voltage stabilization mode with infinite input impedance; meanwhile, the bias current of the circuit is self-adaptive to the output load current, and the energy efficiency of the circuit is improved. Wherein the lowest load current supply circuit comprises a resistor R connected in series between an output voltage terminal and a negative power supply voltage VSS2While the resistance R is2Is connected with a capacitor C in parallel1To act as a load capacitor.
The output voltage regulating circuit comprises a first current mirror, a second current mirror and an NMOS (N-channel metal oxide semiconductor) transistor MN0；
The output current end of the slave current mirror branch A of the first current mirror and the NMOS tube MN8AThe drain electrode of the first current mirror is communicated, the output current end of the secondary current mirror branch A of the first current mirror is communicated with the NMOS tube MN8AThe drain electrode of the first current mirror is communicated with the PMOS tube MP2AElectricity, electricityCurrent mirror PMOS tube MP2B、PMOS pipe MP4AAnd PMOS transistor MP4BGrid electrode of the PMOS transistor MP4BA drain electrode of (1); the output load current is loaded in the NMOS transistor MN0Source electrode of (1), PMOS tube MP2APMOS transistor MP with current mirror2B,Source electrode and NMOS transistor MN0The drain electrode of the transistor is connected with a power supply voltage; the grids of the MOS transistors of the main current mirror branch and the auxiliary current mirror branch of the second current mirror are connected with an NMOS transistor MN0Grid, input reference voltage is connected with current mirror MOS tube MN in main current mirror branch circuit1AThe output voltage end of the source electrode is positioned in a current mirror MOS tube MN in a slave current mirror branch circuit1BOf the substrate.
The gain attenuation circuit is connected in series with an input reference voltage and an NMOS (N-channel metal oxide semiconductor) transistor MN0Resistance R between gates0And a capacitance Cc.
Specifically, the first current mirror comprises a current mirror PMOS transistor MP2AAnd current mirror PMOS transistor MP2BAnd a cascode PMOS transistor MP with source electrode correspondingly connected to the drain electrode4AAnd cascode PMOS transistor MP4BPMOS tube MP2BAnd PMOS transistor MP4BIs a branch of a main current mirror, a PMOS tube MP2AAnd PMOS transistor MP4AFor the slave current mirror branch A, the PMOS tube MP of the master current mirror branch of the first current mirror4BDrain electrode of and NMOS transistor MN8BIs connected. Similarly, the second current mirror comprises a cascode NMOS transistor MN8AAnd NMOS transistor MN8BAnd a current mirror NMOS transistor MN correspondingly connected to the source electrode1AAnd a current mirror NMOS transistor MN1BNMOS transistor MN8AAnd NMOS transistor MN1AForm a main current mirror branch, an NMOS tube MN8BAnd NMOS transistor MN1BA slave current mirror branch is formed. Current mirror NMOS transistor MN1BDrain electrode of the NMOS transistor MN0Drain electrode of (1), NMOS tube MN8AAnd NMOS transistor MN8BThe source electrodes of the NMOS transistors are respectively connected with the NMOS transistor MN1AAnd NMOS transistor MN1BA drain electrode of (1); cascode NMOS transistor MN1AAnd NMOS transistor MN8ANMOS transistor MN with cascode1BAnd NMOS transistor MN8BHave a common gate voltage and connected in parallel with an NMOS transistor MN0A gate electrode of (1).
The specific structure is similar to that of the prior art, and is not repeated herein.
MOS transistor MN for current mirror of slave branch of second current mirror1BThe source of the NMOS transistor is used as a voltage output end mainly because of the NMOS transistor MN1BThe source voltage of the NMOS transistor is consistent with the input reference voltage due to the NMOS transistor MN1AAnd NMOS transistor MN8AThe pair of cascode MOS transistor and NMOS transistor MN1BAnd NMOS transistor MN8BThe pair of cascode MOS transistors have a common gate voltage, while having the same size, and the same current, and thus the same source voltage, NMOS transistor MN1AIs connected with a reference voltage, and an NMOS transistor MN1BThe source of (1) is locked at the reference voltage, and the input reference voltage and the output voltage are kept consistent. The purpose of adding a positive feedback loop is to ensure that when the output voltage changes, it can be quickly adjusted so that the output voltage and the input reference voltage are consistent again.
The positive feedback loop is an NMOS transistor MN in FIG. 10And NMOS transistor MN8ANMOS transistor MN8BAnd NMOS transistor MN1ANMOS tube MN1BThe gain attenuation module is mainly realized by R0And Cc. NMOS tube MN8ANMOS transistor MN8BNMOS transistor MN1ANMOS transistor MN1BPMOS tube MP1APMOS tube MP1BPMOS tube MP2APMOS tube MP2BAnd NMOS transistor MN0The formed current mirror structure is used as a voltage following circuit, and V is ensuredoutFollowing VrefAnd (4) changing. First, the regulation mechanism of positive feedback can be equated with fig. 4. RAAnd RBNMOS transistor MN corresponding to the second current mirror in FIG. 21AAnd NMOS transistor MN1BThe equivalent impedance of (2). Let T be0Representing the loop gain, the load equivalent impedance is ZloadWhen outputting the load current ioA change of Δ will cause the voltage of the left current-controlled voltage source to change by one RAΔ, at the same time, will result in RBChange in pressure drop by one RBΔ, change of output voltage by one ZloadΔ. For the left loop, Vref＝RA*io+V1And V isrefIs a fixed voltage, so that V is caused1By varying one R in opposite directionsAΔ. The output voltage will change (R)B*Δ+Zload*Δ-RAΔ), thus forming a positive feedback loop, but in order to ensure that the output voltage can be reduced, it is necessary to ensure RAΔ changes more, i.e. RA/(RB+Zload) Is less than one. Otherwise, io becomes large, the output voltage becomes large, and the system is uncontrollable. RA/(RB+Zload) Is the loop gain T0. Rout represents the equivalent output impedance looking into the output when the input signal is 0. When io changes by one Δ, the pressure drop over RB changes by RBΔ, the left current-controlled voltage source changes RA Δ, thus V1 changes-RAΔ, so the output voltage changes (R)B-RA) Δ, therefore, the equivalent output impedance Rout ═ RB-RA。
RA and RB correspond to NMOS transistor MN, respectively, in FIG. 21BReverse transconductance (1/GM) ofMN1B) And NMOS transistor MN1AReverse transconductance (1/GM) ofMN1A). In the circuit, an NMOS transistor MN1AAnd NMOS transistor MN1BAre equal in size, and PMOS transistors MP2AAnd PMOS transistor MP2BThe current mirror ratio between is set to 1: 1, so as to flow through the NMOS transistor MN1AAnd NMOS transistor MN1BAre equal. The Current Control Current Source (CCVS) corresponds to the NMOS transistor MN1AAnd NMOS transistor MN1BIs connected to the follower. The transconductance stage refers to the sensed output current from the PMOS transistor MP2BMirror image to PMOS tube MP2AAnd then further fed into a diode-connected NMOS transistor MN1AIn (1). For simplicity, the resistor R is temporarily ignored0And capacitors CC, GDSMN1BIs MN1BIs the inverse of the output impedance due to channel length modulation, also known as the output impedance of the MOSFET. MN (Mobile node)1BOutput impedance of cascode device MN8BIs lifted, so that MN1BThe overall effective transconductance of the stage is GM'MN1B＝GMMN1B-GDSMN1B·GDSMN8B/GMMN8BAlways less than GMMN1B. From the foregoing, the loop gain can be expressed as
Figure GDA0002482146340000061
Due to MN1AAnd MN1BIs equal in size of GM'MN1BIs always less than GMMN1ATherefore, even at output short circuit (Z)load0) is the worst case, loop gain T0Is always less than 1 and meets the stability requirements.
But is compatible with GMMN1ACompared with GM'MN1B＝GMMN1B-GDSMN1B·GDSMN8B/GMMN8BIs much smaller, so under practical conditions due to mismatch, GM'MN1BMay have a value higher than that of the GMMN1A。
Figure GDA0002482146340000062
As frequency increases above ZloadAngular frequency of (d), output impedance ZloadInitially decreasing towards zero and the loop gain increasing towards 1, which leads to potential instability and oscillation problems. Oscillation will occur under non-ideal conditions due to the loop formation with positive feedback.
Thus, C as shown in 2CAnd R0For creating a pole to attenuate the peak loop gain so that its loop gain never exceeds 1, regardless of the non-ideal conditions that occur. The worst case occurs at low temperatures and zero load current and the largest possible load capacitance, which results in the loop gain peaking at the lowest frequency and therefore being the most difficult to attenuate. And is selected from R0And CCA pole is created to allow sufficient attenuation of the peak loop gain. FIG. 5 shows that when the loop gain exceeds 1 in the non-ideal case of mismatch, the loop gain is at ZloadAfter the angular frequency of (c), the highest gain does not exceed 1.
The gain attenuation module mainly utilizes the body effect of the MOS device by using the MN of the NMOS tube1ASubstrate introduction R0Cc, let the equivalent GMMNlAAs a function of frequency, once a frequency point exceeds R0And Cc, the gain will be attenuated.
The output voltage regulating circuit comprises a positive feedback loop, a voltage follower circuit, a gain attenuation circuit and other output voltage regulating circuits which are responsible for regulating the output voltage so that the output voltage is equal to the input reference voltage. Wherein the loop gain of the positive feedback loop is lower than 1 to achieve the purpose of stabilizing the output voltage. In order to ensure that the loop gain is lower than 1, a gain attenuation module is added, so that the loop gain is always lower than 1 at 5 process angles, the temperature is-45-125 ℃, the power supply voltage is between 2.5V and 3.3V.
The current of the output voltage regulating circuit mainly comes from the external load current and the lowest load current generation circuit, which can ensure that the circuit can still work normally when no load current exists. The load current threshold value generation circuit mainly determines a maximum load current value, and once the maximum load current value is exceeded, the voltage follower circuit is immediately turned off, so that the overcurrent protection effect is achieved. Without the limitation of minimum load capacitance, a loop stable structure is ensured by a positive feedback loop and a loop gain lower than 1. And provides a self-limiting current function to protect the low dropout regulator from overheating caused by an output short-circuit fault. The stable new structure of the loop is ensured by a positive feedback loop and a loop gain lower than 1 under the condition of no limit of the minimum load capacitance.
The bias current self-adapting to the output load current is also through the NMOS transistor MN0And NMOS transistor MN8ANMOS transistor MN8BAnd NMOS transistor MN1ANMOS tube MN1BRealized by a current mirror, and the output load current is loaded on an NMOS transistor MN0By means of current mirror proportional mirroring, this current is mirrored proportionally to the NMOS transistor MN1ANMOS tube MN1BNMOS tube MN8AAnd NMOS transistor MN8BThereby providing a bias current to the circuit. In order to ensure that the normal operation of the circuit is not affected under the condition of 0 load current, a minimum load current providing circuit is provided, and a fixed current exists on R2 corresponding to R2 in FIG. 2, wherein the current and the output are negativeCurrent-carrying common NMOS transistor MN0The ratio (400: 1) is mirrored into the circuit. The sum of the lowest load current generating circuit and the external load current in the output load current limiting circuit of fig. 1 is mirrored proportionally to the bias current. Specifically, the sum of the load current and the current of the lowest current generation circuit is the NMOS transistor MN0And NMOS transistor MN1BSetting NMOS tube MN0And NMOS transistor MN1ASetting NMOS transistor MN with the same gate-source voltage0Size of NMOS transistor MN1A400 times of that of the NMOS transistor MN0The divided current is an NMOS tube MN1A400 times, current ratio of 400: 1, and further realizes the proportional mirroring.
The principle of bias current adaptation is shown in fig. 3, and the output load current is mirrored to the voltage follower circuit through an ultra-large NMOS (N-Metal-Oxide-Semiconductor) to provide a bias current for the voltage follower circuit, so that the bias current is adaptive to the output load current, and the energy efficiency of the circuit is improved. Since the output load current is generally large, about milliampere, the NMOS transistor MN0Is an oversized MOS tube.
In order to achieve high input impedance so that the low dropout regulator can drive a bandgap reference circuit, a digital-to-analog conversion circuit, a resistor divider, and the like, the current drawn from the input reference voltage node should be reduced as much as possible. The input current eliminating circuit ensures zero input current, thereby achieving the purpose of high input impedance.
As a specific embodiment, the input current cancellation circuit of the present invention comprises a third current mirror, a fourth current mirror and a fifth current mirror,
the grid electrode of the current mirror MOS tube of the current mirror branch of the third current mirror is connected with the current mirror MOS tube MN of one slave current mirror branch of the fifth current mirror6CThe drain electrode of the third current mirror is connected with the current mirror branch cascode MOS tube MP3BIs connected to the input reference voltage; a current mirror MOS transistor MN of another current mirror branch of the fifth current mirror6BThe drain electrode of the second current mirror is connected with the grid electrode of the second current mirror;
the grid electrode of the MOS tube of the fourth current mirror is connected with the MP of the first slave current mirror branch C4CThe drain electrode of the fourth current mirror, and a cascode MOS (metal oxide semiconductor) transistor MN of a slave current mirror branch circuit of the fourth current mirror5AThe drain of which is connected to an input reference voltage.
Specifically, the third current mirror comprises a PMOS transistor MP of a cascode1AAnd PMOS transistor MP1BAnd a PMOS transistor MP correspondingly connected to the drain thereof3AAnd PMOS transistor MP3BPMOS tube MP1AAnd PMOS transistor MP3AForm a current mirror branch, a PMOS transistor MP1AAnd PMOS transistor MP1BA current mirror branch is formed.
The first slave current mirror branch C comprises a PMOS transistor MP connected with the master current mirror branch of the first current mirror2BCascode PMOS transistor MP2CAnd PMOS transistor MP2CPMOS tube MP connected with drain electrode4C。
The fourth current mirror comprises an NMOS tube MN with the drain electrode connected with the reference voltage5AGrid electrode and NMOS tube MN5ANMOS transistor MN connected with grid electrode5BDrain electrode and NMOS transistor MN5ANMOS transistor MN connected with source electrode4ADrain electrode and NMOS transistor MN5BNMOS transistor MN connected with source electrode4BThe NMOS tube MN5ANMOS transistor MN5BNMOS transistor MN4AAnd NMOS transistor MN4BThe grid electrodes of the NMOS transistors are connected to the NMOS transistor MN in common5BDrain electrode of (1), NMOS tube MN5AAnd NMOS transistor MN4AAnd NMOS transistor MN5BAnd NMOS transistor MN4BRespectively forming current mirror branches.
The fifth current mirror comprises an NMOS tube MN6CAnd NMOS transistor MN6BNMOS transistor MN6CDrain electrode of the PMOS transistor MP3ADrain electrode, source electrode connected to VSS, NMOS transistor MN6BDrain electrode of the NMOS transistor MN0Grid, source connected to VSS, NMOS transistor MN6CAnd NMOS transistor MN6BIs connected in parallel with the PMOS transistor MP mentioned below4DOf the substrate.
Input current cancellation principle, as shown in FIG. 2, when a reference voltage V is inputrefSuppose from VrefThe current flowing in is Iin according toKirchhoff's current law: iin ═ I3B+I1A-I5A。
Through the matching of the cascode current mirror, the PMOS transistor MP is enabled1AAnd PMOS transistor MP1BMixing the raw materials in a ratio of 1: 1 size matching, NMOS transistor MN6CAnd NMOS transistor MN6BMixing the raw materials in a ratio of 1: size of 1 matches 1: 1, then: i is3B＝I3A＝I6B. Wherein at an intermediate node VDRVAccording to kirchhoff's current law, the following can be known: i is4A-I6B＝I1AThus Iin ═ I4A-I5A. Through ensuring the current mirror PMOS tube MP2AAnd PMOS transistor MP2BAnd NMOS transistor MN1AAnd NMOS transistor MN8AIs matched with, I4A＝I5A. The input current is therefore zero.
The load current threshold value generating circuit comprises an NMOS transistor MN of a grid electrode and a fifth current mirror6BNMOS transistor MN with connected grid6AConnected with an NMOS tube MN6AResistance R between and a negative supply voltage Vss1The NMOS tube MN6AAnd into the input branch D of the first current mirror.
The branch D of the first current mirror comprises a PMOS transistor MP connected with the main current mirror branch of the first current mirror2BA PMOS transistor MP2D of cascode, and a PMOS transistor MP connected with the drain electrode of the PMOS transistor MP2D4DThe source and the gate of the PMOS transistor MP2D are the output current terminals of the current mirror branch D, and the PMOS transistor MP4DThe drain of which is the input current terminal of the current mirror branch D,
once R is present1When the current of the NMOS transistor exceeds a certain value, the NMOS transistor MN is connected6AGate voltage of the MOS transistor MN is increased6AThe transistor is conducted to further conduct the NMOS transistor MN6BIs pulled low, VDRVThe circuit is cut off, a load current sensing module is added, in order to prevent the chip from being overheated due to overlarge current, once the current exceeds a set value, the circuit is immediately cut off, and the safety factor of the chip is improved. The problems of circuit overheating and the like caused by excessive load current are prevented. The circuit mainly comprises a negative electrodeA load current threshold generation circuit and a minimum load current generation circuit.
The invention utilizes a positive feedback structure with loop gain lower than 1, and the stability is independent of the output load capacitance and the output load current, and the bias current is self-adaptively changed along with the output load current. The method has the advantages of high energy efficiency, independent stability and large output load current range, and can set the load current threshold value to realize the positive effects of overheating protection and the like.
Finally, it should be noted that: the above-mentioned embodiments are merely specific embodiments of the present disclosure, which are used for illustrating the technical solutions of the present disclosure and not for limiting the same, and the scope of the present disclosure is not limited thereto, and although the present disclosure is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive of the technical solutions described in the foregoing embodiments or equivalent technical features thereof within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the embodiments of the present disclosure, and should be construed as being included therein. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (3)

1. A high-efficiency low dropout regulator is characterized by comprising,
an output voltage adjusting circuit including a voltage follower circuit for adjusting an output voltage to be equal to an input reference voltage, a positive feedback loop independent of a load capacitance and a load current and having a loop gain lower than 1, and a gain attenuation circuit for ensuring the loop gain to be smaller than 1;
the output load current limiting circuit is used for overcurrent protection, when the output load current exceeds a set threshold value, the circuit is turned off in time, and the lowest load current providing circuit is used for providing load current when the load is zero; the input current cancellation circuit is used for providing a voltage stabilization mode with infinite input impedance; while its bias current is adaptive to the output load currentThe output voltage regulating circuit comprises a first current mirror, a second current mirror and an NMOS (N-channel metal oxide semiconductor) transistor MN0；
The first current mirror comprises a PMOS transistor MP2AAnd PMOS transistor MP2BAnd the source electrode is correspondingly connected with the PMOS tube MP2AAnd PMOS transistor MP2BDrain cascode PMOS transistor MP4AAnd cascode PMOS transistor MP4BPMOS tube MP2BAnd PMOS transistor MP4BIs a branch of a main current mirror, a PMOS tube MP2AAnd PMOS transistor MP4AIs the slave current mirror branch A; the PMOS tube MP of the main current mirror branch circuit of the first current mirror4BDrain electrode of and NMOS transistor MN8BThe drain electrode of the first current mirror is communicated, the output current end of the secondary current mirror branch A of the first current mirror is communicated with the NMOS tube MN8AThe drain electrode of the first current mirror is communicated with the PMOS tube MP2APMOS transistor MP with current mirror2B、PMOS pipe MP4AAnd PMOS transistor MP4BGrid electrode of the PMOS transistor MP4BA drain electrode of (1); the output load current is loaded in the NMOS transistor MN0Source electrode of (1), PMOS tube MP2APMOS transistor MP with current mirror2B,Source electrode and NMOS transistor MN0The drain electrode of the transistor is connected with a power supply voltage;
NMOS (N-channel metal oxide semiconductor) transistor MN (N-channel metal oxide semiconductor) of main current mirror branch and auxiliary current mirror branch of second current mirror8ANMOS transistor MN8BNMOS transistor MN1AAnd NMOS transistor MN1BThe grid of the NMOS transistor MN0Grid, input reference voltage is connected with a current mirror NMOS tube MN in a main current mirror branch1AThe output voltage end of the source electrode is positioned in a current mirror NMOS tube MN in the slave current mirror branch circuit1BSource electrode of (1), current mirror NMOS transistor MN1BDrain electrode of the NMOS transistor MN0Drain electrode of (1), NMOS tube MN8AAnd NMOS transistor MN8BThe source electrodes of the NMOS transistors are respectively connected with the NMOS transistor MN1AAnd NMOS transistor MN1BA drain electrode of (1);
cascode NMOS transistor MN1AAnd NMOS transistor MN8ANMOS transistor MN with cascode1BAnd NMOS transistor MN8BHave a common gate voltage and connected in parallel with an NMOS transistor MN0A gate electrode of (1).
2. A high efficiency low pressure system as claimed in claim 1The differential voltage stabilizer is characterized in that the gain attenuation circuit is connected in series with an input reference voltage and an NMOS (N-channel metal oxide semiconductor) transistor MN0Resistance R between gates0And a capacitor Cc and an NMOS transistor MN1ASubstrate access resistance R0And a capacitor Cc.
3. The high efficiency LDO of claim 2 wherein said minimum load current supply circuit comprises a resistor R connected in series between the output voltage terminal and the negative supply voltage VSS2。
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CN115291667B (en) * 2021-12-22 2023-08-25 夏芯微电子(上海)有限公司 Wireless communication device and adaptive bias voltage adjustment circuit
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