CN107783588B - Push-pull type quick response LDO circuit - Google Patents
Push-pull type quick response LDO circuit Download PDFInfo
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F7/00—Regulating magnetic variables
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
The application discloses a push-pull type quick response LDO circuit, which comprises: a first control circuit, a second control circuit, a third control circuit, a feedback circuit, a load circuit, an error amplifier EA and a power tube M P The method comprises the steps of carrying out a first treatment on the surface of the Compared with the existing LDO circuit, the circuit structure provided by the application has good performance in various parameter indexes such as low power consumption, large load current, high power supply rejection ratio, transient response and the like, particularly has outstanding performance in the aspect of transient response, and meets the development needs of the future LDO circuit. The circuit structure can be widely applied to SoC chips.
Description
Technical Field
The application relates to a system for adjusting electric variable or magnetic variable, in particular to an LDO (Low Dropout Regulator, LDO, low dropout linear regulator) circuit.
Background
Almost all electronic circuits require a stable voltage source that is maintained within a certain tolerance range to ensure proper operation (typical CPU circuits only allow maximum deviation of the voltage source from nominal voltage by no more than + -3%). The fixed voltage is provided by some kind of voltage regulator. The LDO circuit is one of the voltage regulators.
As shown in fig. 1, a typical LDO circuit includes: reference voltage V ref Error amplifier EA, power tube a1, resistor divider a2, current source a3. The LDO circuit automatically detects the output voltage V through a resistor divider a2 out The error amplifier EA continuously adjusts the current source a3 to maintain the output voltage V out Stable at rated voltage. The LDO circuit with the structure has the problem of low load transient response capability. However, with the continuous development of integrated circuits, the conventional LDO structure cannot meet the requirements of low power consumption, high load current, high power supply rejection ratio, good transient response, and the like, so a new circuit needs to be designed.
Disclosure of Invention
The application aims to provide an LDO circuit which can rapidly cope with load change and has good transient response.
The application solves the technical problems as follows: a push-pull fast response LDO circuit, comprising: a first control circuit, a second control circuit, a third control circuit, a feedback circuit, a load circuit, an error amplifier EA and a power tube M P The method comprises the steps of carrying out a first treatment on the surface of the The first control circuit is configured to: PMOS tube M1, M3, NMOS tube M2, electric capacity C1, resistance R1 are constituteed, the drain electrode of M1 respectively with the drain electrode of M2, the grid of M3, one end of electric capacity C1 are connected, the other end of electric capacity C1 with one end of resistance R1 is connected, the grid of M1 with error amplifier EA's output is connected, the source electrode of M1M 3 respectively with power VDD is connected, the source electrode of M2 is connected with ground GND, the drain electrode of M3 respectively with another of resistance R1End, the power tube M P The substrates of M1 and M3 are respectively connected with the power supply VDD, and the substrate of M2 is connected with the ground GND; the second control circuit is configured to: PMOS tube M4, NMOS tube M5, M6, the drain electrode of M4 is connected with drain electrode, grid electrode of M5 respectively, the grid electrode of M4 is connected with the output of error amplifier EA, the source electrode of M4 is connected with power VDD, the grid electrode of M5 is connected with the grid electrode of M6, the drain electrode of M6 with M P The sources of the M5 and the M6 are respectively connected with the ground GND, the substrate of the M4 is connected with the power supply VDD, and the substrates of the M5 and the M6 are respectively connected with the ground GND; the third control circuit is configured to: PMOS tube M7, NMOS tube M8, M9, operational amplifier AMP, the inverting input of AMP is connected with the grid of M4, the output of error amplifier EA respectively, the output of AMP is connected with the grid of M7, the source of M7 is connected with power supply VDD, the drain of M7 is connected with the grid of M9, the drain of M8, the drain of M9 is connected with the drain of M P The sources of M8 and M9 are connected with the ground GND, the substrate of M7 is connected with the power supply VDD, and the substrates of M8 and M9 are connected with the ground GND; the feedback circuit is composed of: NMOS tube M10, M11, drain electrode, grid electrode of said M10, grid electrode of said M11 connect said push-pull fast response LDO circuit's output voltage end, said output voltage end and said M P The source electrode of the M10 is respectively connected with the drain electrode of the M11 and the non-inverting input end of the error amplifier EA, the source electrode of the M11 is connected with the ground GND, and the substrate of the M11 is connected with the ground GND; the load circuit is configured to: load resistor R L Load capacitor C L Composition of the load resistor R L With the load capacitance C L And in parallel, the load resistor R L Load capacitor C L One end of the voltage source is connected with the output voltage end, and the other end of the voltage source is connected with the ground GND; the inverting input end of the error amplifier EA is connected with the reference voltage V ref 。
Further, the power tube M P Is a PMOS tube.
Further, the reference voltage V ref Is the output voltage of the bandgap reference circuit.
The beneficial effects of the application are as follows: compared with the existing LDO circuit, the circuit structure provided by the application has good performance in various parameter indexes such as low power consumption, large load current, high power supply rejection ratio, transient response and the like, particularly has outstanding performance in the aspect of transient response, and meets the development needs of the future LDO circuit. The circuit structure can be widely applied to SoC chips.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that are required to be used in the description of the embodiments will be briefly described below. It is evident that the drawings described are only some embodiments of the application, but not all embodiments, and that other designs and drawings can be obtained from these drawings by a person skilled in the art without inventive effort.
FIG. 1 is a schematic diagram of a LDO circuit in the background art;
FIG. 2 is a schematic diagram of an LDO circuit according to the present application;
FIG. 3 is when the load voltage V out The change condition of the control loop is controlled during lifting;
fig. 4 is when the load voltage V out The change of the control loop is controlled in a reduced manner.
Detailed Description
The conception, specific structure, and technical effects produced by the present application will be clearly and completely described below with reference to the embodiments and the drawings to fully understand the objects, features, and effects of the present application. It is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments, and that other embodiments obtained by those skilled in the art without inventive effort are within the scope of the present application based on the embodiments of the present application. In addition, all coupling/connection relationships mentioned herein do not refer to direct connection of the components, but rather, refer to the fact that a more optimal coupling structure may be formed by adding or subtracting coupling aids depending on the particular implementation. The technical features in the application can be interactively combined on the premise of no contradiction and conflict.
Embodiment 1, referring to fig. 2, a push-pull fast response LDO circuit comprises: a first control circuit 1, a second control circuit 2, a third control circuit 3, a feedback circuit 4, a load circuit 5, an error amplifier EA, and a power tube M P The method comprises the steps of carrying out a first treatment on the surface of the The power tube M P The first control circuit 1 is a PMOS transistor, and comprises: PMOS tube M1, M3, NMOS tube M2, electric capacity C1, resistance R1 are constituteed, the drain electrode of M1 respectively with the drain electrode of M2, the grid of M3, one end of electric capacity C1 are connected, the other end of electric capacity C1 with one end of resistance R1 is connected, the grid of M1 with error amplifier EA's output is connected, the source of M1 the source of M3 respectively with power VDD is connected, the source of M2 is connected with ground GND, the grid of M2 is connected reference voltage V b1 The drain electrode of the M3 is respectively connected with the other end of the resistor R1 and the power tube M P The substrates of M1 and M3 are respectively connected with the power supply VDD, and the substrate of M2 is connected with the ground GND; the second control circuit 2 is composed of: PMOS tube M4, NMOS tube M5, M6, the drain electrode of M4 is connected with drain electrode, grid electrode of M5 respectively, the grid electrode of M4 is connected with the output of error amplifier EA, the source electrode of M4 is connected with power VDD, the grid electrode of M5 is connected with the grid electrode of M6, the drain electrode of M6 with M P The sources of the M5 and the M6 are respectively connected with the ground GND, the substrate of the M4 is connected with the power supply VDD, and the substrates of the M5 and the M6 are respectively connected with the ground GND; the third control circuit 3 is composed of: PMOS tube M7, NMOS tube M8, M9, operational amplifier AMP, the inverting input end of said AMP is connected with the grid of said M4 and the output end of said error amplifier EA, the homodromous input end of said AMP is connected with reference voltage V b2 The output end of the AMP is connected with the grid of the M7, the source electrode of the M7 is connected with the power supply VDD, the drain electrode of the M7 is connected with the grid of the M9 and the drain electrode of the M8, and the drain electrode of the M9 is connected with the M P The grid of M8 is connected with the reference voltage V b3 The sources of M8 and M9 are connected with the ground GND, the substrate of M7 is connected with the power supply VDD, M8,The substrate of M9 is connected with the ground GND; the feedback circuit 4 is composed of: NMOS tube M10, M11, drain electrode, grid electrode of said M10, grid electrode of said M11 connect said push-pull fast response LDO circuit's output voltage end, said output voltage end and said M P The source electrode of the M10 is respectively connected with the drain electrode of the M11 and the non-inverting input end of the error amplifier EA, the source electrode of the M11 is connected with the ground GND, and the substrate of the M11 is connected with the ground GND; the load circuit 5 is composed of: load resistor R L Load capacitor C L Composition of the load resistor R L With the load capacitance C L And in parallel, the load resistor R L Load capacitor C L One end of the voltage source is connected with the output voltage end, and the other end of the voltage source is connected with the ground GND; the inverting input end of the error amplifier EA is connected with the reference voltage V ref . The reference voltage V ref The bandgap reference circuit can establish a direct current voltage which is independent of power supply and process and has a certain temperature characteristic, so that a stable voltage Vref is provided for the operational amplifier AMP, and the performance of the LDO circuit is improved.
For convenience of description, the junction of the source of M10, the drain of M11, and the non-inverting input terminal of the error amplifier EA is point A, the junction of the output terminal of the error amplifier EA, the M1 gate, the M4 gate, and the inverting input terminal of the operational amplifier AMP is point B, and the power tube M P The junction of the gate of M3, the drain of M6 is point C. The working principle of the application is as follows:
as shown in fig. 3, when the load changes, i.e. when the output voltage V out When rising, the voltage at point a rises, and point a is connected to the non-inverting input terminal of error amplifier EA, so that the voltage at point B rises, the gate voltage of M1 rises, the current flowing through M1 decreases, and the gate voltage of M3 decreases. When the gate voltage of M3 decreases, the current flowing through M3 increases; when the voltage at the point B increases, the gate voltage of M4 increases, the current flowing through M5 decreases, and M6 and M5 form a current mirror, so that the current flowing through M6 also decreases; the current of M3 increases and the current of M6 decreases, so the voltage at point C increases. Electricity at point CPressure rise, flow through M P Is reduced; when the voltage at the point B increases, the voltage at the output terminal of the op AMP decreases because it is connected to the inverting input terminal of the op AMP, the gate voltage of M7 decreases, and the gate voltage of M9 increases when M7 changes from the original off state to on, and the current flowing through M9 increases; m is M P The current of M9 increases to output voltage V out Pulling down to stabilize the load voltage.
As shown in FIG. 4, when the voltage V is outputted out When the voltage at point a decreases, the voltage at output terminal B of EA decreases, the gate voltage of M1 decreases, and the current flowing through M1 increases, thereby increasing the gate voltage of M3. The gate voltage of M3 increases and the current flowing through M3 decreases; when the voltage at point B decreases, the gate voltage of M4 decreases, the current through M4 increases, and the current through M6 increases; when the current flowing through M3 decreases and the current flowing through M6 increases, the voltage at point C decreases, the current flowing through MP increases, and the output voltage V out Pulling up to stabilize the load voltage. When the voltage at point B decreases, the output voltage of AMP is high, and since M7 is PMOS, M7 is in a closed state and does not operate. That is, the third control circuit 3 is not operated, and the third control circuit 3 is not shown in fig. 4 as a prompt.
The circuitry was quantitatively analyzed as follows: term interpretation: i 1 To flow through M1 current, I 2 To flow through M2, I 3 To flow through M3 current, I 4 To flow through M4 current, I 5 To flow through M5 current, I 6 To flow through M6 current, I P To flow through M P Current of I 8 To flow through M8 current, I 9 To flow through M9 current, I 10 To flow through M10 current, I 11 Is the current flowing through M11;
1. feedback circuit 4
The voltage at point A is a function of the output voltage V out And synchronously changing. As can be seen from fig. 2, M10 is connected in a diode connection manner, and thus in a saturation region, M11 may be in a saturation region or may be in a linear region.
1.1 assume M11 is in the saturation region
V GS11 ＝V out (3)
V GS10 ＝V out -V A (4)
I 11 ＝I 10 (5)
Wherein K is i ＝μ n,p C ox (W/L) i i＝1,2…
Obtained from (1), (2), (3), (4), (5)
Deriving (6)
1.2 when M11 is operated in triode region, its current formula is
V DS11 ＝V A (9)
From (1) (5)
From (3) (4) (8) (9) (10)
Deriving (11)
V A Is the voltage of A point, V GS Is the gate-source voltage of MOS tube, V DS Is the drain-source voltage of the CMOS transistor. V (V) TH Is the threshold voltage of the CMOS transistor. Mu (mu) n Is the mobility of electrons, mu p Is the mobility of holes. C (C) ox Is the gate capacitance per unit area. W is the conduction channel width, L is the conduction channel length, and (W/L) is the aspect ratio of the CMOS transistor.
In formula (7) we can adjust the aspect ratio of M10 and M11 to a value greater than zero and formula (12) to a value greater than zero. Thus, it can be seen from equations (7) and (12) that the derivative between the voltage at point a and the output voltage is positive, and therefore, there is a proportional relationship between them. The voltage at point a varies with the output.
2. The control circuit portion is configured to control the operation of the electronic device,
2.1 first control Circuit 1
As shown in fig. 2, M1 and M2 are common source circuits employing current source loads. The PMOS current is set to flow from the source to the drain, and the current flowing through the PMOS tube M1 is
V GS1 ＝VDD-V B (14)
If the voltage change amount at point B is DeltaVB, the voltage change amount is obtained by formulas (13) and (14)
DeltaV when the voltage at point B increases B Is positive, decrease the hour DeltaV B Is negative. From equation (15), it can be seen that when the voltage at point B increases, the current I 1 When the voltage at point B is reduced, the current I 1 Increasing. And because M2 is connected with bias voltage and is equivalent to a current source, it is electrically connected withThe flow is unchanged, thus when I 1 M3 gate voltage decrease at decrease, I 1 The M3 gate voltage increases as it increases.
The current flowing through M3 is
V GS1 ＝VDD-V G3 (17)
Let the variation of the gate voltage of M3 be DeltaV G3 Then can be obtained by the formulas (16) (17)
As can be seen from equation (18), when the M3 gate voltage increases, I 3 Decrease, I when M3 gate voltage decreases 3 Raised.
2.2 second control Circuit 2
The connection mode of the PMOS tubes M4 and M5 in the second control circuit 2 is a common source stage circuit of a load connected by a diode. It differs from the circuit consisting of M1 and M2 only in load, so the current variation of M1 and M4 is the same.
The load M5 of M4 is diode-connected, so that M5 can be equivalently a small-signal resistor. M5 and M6 again constitute a current mirror, so that the currents in M5 and M6 are varied synchronously.
Thus, from an analysis of M1, it can be seen that the current I flowing through M4 increases as the voltage at point B increases 4 Current I flowing through M4 when the point B voltage decreases 4 Increasing. The current is changed identically by M6 and M5, thus I 4 Time of decrease I 6 Also reduce I 4 Time of increase I 6 And also increases.
2.3 Power tube M P
Flow through M P The current of (2) is
V GSP ＝VDD-V C (20)
And output voltage V out Is that
V out ＝I out ·Z out (21)
I out ＝αI P (22)
Z out Is the output impedance.
Let the voltage change at point C be DeltaV C Then can be obtained by the formulas (19), (20), (21) and (22)
From the formula (23), it can be seen that I is the time the voltage at point C increases out Reduction, deltaV C Positive, output voltage V out Lowering and restoring the normal state; point C voltage is reduced I out Increase, deltaV C Positive, output voltage V out Rising, recovering the normal state and stabilizing the load voltage.
2.4 third control Circuit 3
As shown in FIG. 2, the output end of the operational amplifier AMP is connected to M7, and the bias voltage V is connected to M8 b3 . M7 and M8 form a common source stage circuit using a current source load. I 8 The current formula is
From formula (24), it can be seen that when V GS8 Smaller, I 8 And is also relatively small.
Normally, the voltage output by AMP is VDD voltage, so M7 is in the cut-off region, because M7 is a PMOS transistor, M7 is turned on only when the gate-source voltage VGS7 is less than the threshold voltage.
When the voltage at point B increases, the AMP output voltage is zero at this time through the inverting input of the operational amplifier, so that M7 is turned on and the third control circuit 3 starts to operate. At this time the M9 gate voltage increases.
The current formula of M9 is
Let M7 gate voltage change be DeltaV GS9 Then it is obtainable by the formula (25)
As can be seen from equation (26), when the gate voltage of M9 increases, the current in M9 increases, and the output voltage V out Pulling down.
As can be seen from analysis of the feedback circuit 4, the first control circuit 1, and the second control circuit 2, when the output voltage V out At increasing voltage at point B increases, current I in M3 3 Increase the current I in M6 6 Decreases and thus the voltage at point C is pulled high. The voltage at point C increases and flows through M P Is reduced. As is clear from an analysis of the third control circuit 3, the voltage at the point B increases, the voltage at the output terminal of the operational amplifier AMP decreases, the gate voltage of M7 decreases, and the M7 on control circuit starts to operate, so the gate voltage of M9 is pulled high, and the current flowing through M9 increases. To sum up, when the output voltage V out When rising, M P The current in M9 increases, the output voltage V out Pulling down, recovering to normal state, and stabilizing load voltage.
When outputting voltage V out When decreasing, the voltage at point B decreases, the current in M3 decreases, the current in M6 increases, and therefore the voltage at point C is pulled low, the current through MP increases, and the output voltage V out Is pulled up, returns to the normal state and stabilizes the load voltage.
Through simulation, the LDO circuit provided by the application can enable the load voltage of the LDO circuit to be recovered to a normal state within 8ns, and has obvious advantages compared with the traditional LDO circuit.
While the preferred embodiment of the present application has been described in detail, the application is not limited to the embodiments, and various equivalent modifications and substitutions can be made by those skilled in the art without departing from the spirit of the application, and these modifications and substitutions are intended to be included in the scope of the present application as defined in the appended claims.
Claims (3)
1. A push-pull fast response LDO circuit, comprising: a first control circuit, a second control circuit, a third control circuit, a feedback circuit, a load circuit, an error amplifier EA and a power tube M P ；
The first control circuit is configured to: PMOS tube M1, M3, NMOS tube M2, electric capacity C1, resistance R1 are constituteed, the drain electrode of M1 respectively with the drain electrode of M2, the grid of M3, one end of electric capacity C1 are connected, the other end of electric capacity C1 with one end of resistance R1 is connected, the grid of M1 with error amplifier EA's output is connected, the source electrode of M1M 3 respectively with power VDD is connected, the source electrode of M2 is connected with ground GND, the drain electrode of M3 respectively with the other end of resistance R1, power tube M P The substrates of M1 and M3 are respectively connected with the power supply VDD, and the substrate of M2 is connected with the ground GND;
the second control circuit is configured to: PMOS tube M4, NMOS tube M5, M6, the drain electrode of M4 is connected with drain electrode, grid electrode of M5 respectively, the grid electrode of M4 is connected with the output of error amplifier EA, the source electrode of M4 is connected with power VDD, the grid electrode of M5 is connected with the grid electrode of M6, the drain electrode of M6 with M P The sources of the M5 and the M6 are respectively connected with the ground GND, the substrate of the M4 is connected with the power supply VDD, and the substrates of the M5 and the M6 are respectively connected with the ground GND;
the third control circuit is configured to: PMOS tube M7, NMOS tube M8, M9, operational amplifier AMP, the inverting input of AMP is connected with the grid of M4, the output of error amplifier EA respectively, the output of AMP is connected with the grid of M7, the source of M7 is connected with power supply VDD, the drain of M7 is connected with the grid of M9, the drain of M8, the drain of M9 is connected with the drain of M P The sources of M8 and M9 are connected with the ground GND, the substrate of M7 is connected with the power supply VDD, and the M8The substrate of M9 is connected with the ground GND;
the feedback circuit is composed of: NMOS tube M10, M11, drain electrode, grid electrode of said M10, grid electrode of said M11 connect said push-pull fast response LDO circuit's output voltage end, said output voltage end and said M P The source electrode of the M10 is respectively connected with the drain electrode of the M11 and the non-inverting input end of the error amplifier EA, the source electrode of the M11 is connected with the ground GND, and the substrates of the M10 and the M11 are connected with the ground GND;
the load circuit is configured to: load resistor R L Load capacitor C L Composition of the load resistor R L With the load capacitance C L And in parallel, the load resistor R L Load capacitor C L One end of the voltage source is connected with the output voltage end, and the other end of the voltage source is connected with the ground GND;
the inverting input end of the error amplifier EA is connected with the reference voltage V ref 。
2. The push-pull fast response LDO circuit of claim 1, wherein: the power tube M P Is a PMOS tube.
3. A push-pull fast response LDO circuit according to claim 1 or 2, wherein: the reference voltage V ref Is the output voltage of the bandgap reference circuit.
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| CN108227815B (en) * | 2018-03-19 | 2023-11-28 | 佛山科学技术学院 | Self-adaptive dynamic bias LDO circuit applied to low-voltage output |
| CN109062308B (en) * | 2018-09-29 | 2020-06-09 | 上海华虹宏力半导体制造有限公司 | Voltage regulation circuit |
| CN111414037B (en) * | 2020-03-10 | 2022-01-25 | 佛山科学技术学院 | LDO voltage stabilizing circuit |
| CN117539318B (en) * | 2024-01-09 | 2024-03-26 | 龙骧鑫睿(厦门)科技有限公司 | Off-chip capacitor LDO circuit with high power supply rejection ratio |
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