CN102707754A - Low dropout regulator - Google Patents

Low dropout regulator Download PDF

Info

Publication number
CN102707754A
CN102707754A CN2012101736136A CN201210173613A CN102707754A CN 102707754 A CN102707754 A CN 102707754A CN 2012101736136 A CN2012101736136 A CN 2012101736136A CN 201210173613 A CN201210173613 A CN 201210173613A CN 102707754 A CN102707754 A CN 102707754A
Authority
CN
China
Prior art keywords
pmos
pipe
connects
circuit
voltage
Prior art date
Application number
CN2012101736136A
Other languages
Chinese (zh)
Other versions
CN102707754B (en
Inventor
黄从朝
Original Assignee
昆山锐芯微电子有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 昆山锐芯微电子有限公司 filed Critical 昆山锐芯微电子有限公司
Priority to CN201210173613.6A priority Critical patent/CN102707754B/en
Publication of CN102707754A publication Critical patent/CN102707754A/en
Application granted granted Critical
Publication of CN102707754B publication Critical patent/CN102707754B/en

Links

Abstract

The invention discloses a low dropout regulator, which comprises an error amplifier, a buffer circuit, a P-channel metal oxide semiconductor (PMOS) regulation transistor, an N-channel metal oxide semiconductor (NMOS) push-pull tube, a voltage division feedback circuit, a compensation circuit and an output circuit, wherein the gate of the PMOS regulation transistor is connected with the output end of the buffer circuit, the source of the PMOS regulation transistor is connected with power voltage, and the drain of the PMOS regulation transistor is used as the output end of the low dropout regulator; the gate of the NMOS push-pull tube is connected with the output end of the error amplifier, the drain of the NMOS push-pull tube is connected with the drain of the PMOS regulation transistor, and the source of the NMOS push-pull tube is grounded; and the error amplifier, the compensation circuit, the buffer circuit, the PMOS regulation transistor, the voltage division feedback circuit and an output circuit form a main control loop, and the error amplifier, the compensation circuit, the NMOS push-pull tube, the voltage division feedback circuit and the output circuit form an auxiliary control loop. According to the low dropout regulator, the transient response of the regulator can be quickened, and the accuracy of output voltage can be improved.

Description

Low-dropout linear voltage-regulating circuit
Technical field
The present invention relates to technical field of integrated circuits, particularly a kind of low-dropout linear voltage-regulating circuit.
Background technology
(Low Dropout Regulator LDO) is the step-down type dc linear voltage regulator to the linear mu balanced circuit of low pressure differential, and it is ubiquitous in sector applications such as computing machine, communication, instrument and meter, consumer electronics, monitoring camera-shootings along with the development of SOC technology.Though compare with the DC-DC switching voltage converter; The efficient of LDO is low; But it has advantages such as peripheral cell is few, ripple is little, noise is low, chip area is little, circuit structure is simple, so LDO occupies very big proportion in power management class chip always.
Raising along with integrated level; Increasing LDO is as SOC (System on Chip; SOC(system on a chip)) submodule of chip is given certain crucial module for power supply and is integrated in this SOC chip, and integrated a plurality of LDO modules are very general to the different module power supply in the powerful SOC chip.Frequency of operation along with the SOC system improves constantly simultaneously, and it is also more and more serious that digital circuit wherein brings power supply to disturb, and this just needs LDO that performance requirements such as High-speed transient response speed, high output voltage control accuracy, high PSRR, low noise are arranged.
Traditional LDO voltage regulator circuit block diagram is as shown in Figure 1.With reference to figure 1, said LDO voltage regulator circuit is the monocycle degeneration factor that is made up of error amplifier OP, middle buffer level, PMOS adjustment transistor MP, dividing potential drop feedback network, output circuit, miller-compensated circuit.
Particularly, said dividing potential drop feedback network comprises first resistance R _ f 1, second resistance R _ f 2.Said first resistance R _ f 1 and second resistance R _ f 2 are formed partial pressure unit, branch pressure voltage V FBFed back to the normal phase input end of error amplifier OP.The negative-phase input of said error amplifier OP receives reference voltage vref.
Said output circuit is made up of equivalent series resistance ESR and output capacitance C2.Output circuit not only can reduce because the output voltage ripple that causes during load changing, and can also be provided high frequency zero point for the feedback loop of system.
Said miller-compensated circuit comprises miller-compensated resistance R c and miller-compensated capacitor C c, is used for the limit of error amplifier OP output terminal and the limit of PMOS adjustment transistor MP drain electrode are compensated, and feedback control loop can both be stablized under various loading conditions.
Generally speaking in order to guarantee to export enough driving forces; The size of PMOS adjustment transistor MP is all bigger usually; And the big grid stray capacitance (usually at tens pico farads) that large-sized PMOS adjustment transistor MP brings can significantly be slowed down the discharge and recharge speed of middle buffer level to this stray capacitance, and then seriously reduces system's transient response speed.
In addition; For the precision that guarantees output voltage V o and high low frequency PSRR (PSRR); Require error amplifier OP to have high-gain; And high-gain causes the output node impedance of error amplifier OP very big, has seriously reduced the bandwidth of system and then has reduced system's transient response speed on the one hand, has also strengthened the difficulty of system balance on the other hand.
So traditional LDO voltage feedback loop is a slow feedback control loop that comprises multipole point; When load current IL has big sudden change; What output voltage V o not only had a dozens or even hundreds of millivolt owes charging voltage (undershoot) and overcharged voltage (overshoot); And need a long transient process just can return to steady-state value; So just cause its output accuracy not high, can't can clean direct supply reliably be provided SOC (like pel array in the monitoring chip) for more current high-speed high-performances.
Summary of the invention
The problem that the present invention solves provides a kind of low-dropout linear voltage-regulating circuit, with the transient response speed that improves circuit effectively and the precision of output voltage.
For addressing the above problem, the present invention provides a kind of low-dropout linear voltage-regulating circuit, comprising: error amplifier, compensating circuit, buffer circuit, PMOS adjustment transistor, NMOS recommend pipe, dividing potential drop feedback circuit and output circuit;
Said error amplifier is used for the branch pressure voltage and the reference voltage of said dividing potential drop feedback circuit output are compared, and exports comparative result to said buffer circuit;
Said buffer circuit; Be used to carry out impedance matching and adjust transistorized grid stray capacitance node with output impedance node and the PMOS that isolates error amplifier; And after driving being provided, exporting said comparative result to PMOS and adjust transistorized grid for the comparative result that receives;
Said PMOS adjusts transistorized source electrode and connects supply voltage, and drain electrode is as the output terminal of low-dropout linear voltage-regulating circuit;
Said dividing potential drop feedback circuit is used for the voltage of said PMOS adjustment transistor drain is carried out dividing potential drop, and branch pressure voltage is fed back to error amplifier;
The grid that said NMOS recommends pipe connects the output terminal of said error amplifier, and drain electrode connects said PMOS adjustment transistor drain, source ground;
Said output circuit connects said PMOS adjustment transistor drain, is used to reduce output voltage ripple;
One end of said compensating circuit connects supply voltage, and the other end connects the output terminal of said error amplifier, is used for said low-dropout linear voltage-regulating circuit is compensated so that it is stable.
Alternatively, said PMOS adjusts ratio between the breadth length ratio that transistorized breadth length ratio and said NMOS recommend pipe more than or equal to 1000.
Alternatively, said compensating circuit comprises: compensating resistance and building-out capacitor; One end of said building-out capacitor connects supply voltage, and the other end connects an end of said compensating resistance; The other end of said compensating resistance connects the output terminal of error amplifier.
Alternatively, said error amplifier comprises: tail current source and input difference are to, PMOS common-source common-gate current mirror and NMOS constant-current source bias and folded tube;
Said tail current source and input difference are to comprising PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe and the 4th PMOS pipe; Said PMOS common-source common-gate current mirror comprises the 5th PMOS pipe, the 6th PMOS pipe, the 7th PMOS pipe and the 8th PMOS pipe; Said NMOS constant-current source bias and folded tube comprise the 9th NMOS pipe, the tenth NMOS pipe, the 11 NMOS pipe and the 12 NMOS pipe;
The grid of the one PMOS pipe connects first bias voltage, and source electrode connects supply voltage, and drain electrode connects the source electrode of the 2nd PMOS pipe;
The grid of the 2nd PMOS pipe connects second bias voltage, and drain electrode connects the source electrode of the 3rd PMOS pipe and the 4th PMOS pipe;
The branch pressure voltage of the connection dividing potential drop feedback circuit output of the 3rd gate pmos utmost point, drain electrode connects the drain electrode of the 11 NMOS pipe;
The grid of the 4th PMOS pipe connects reference voltage; Drain electrode connects the drain electrode of the 12 NMOS pipe;
The 5th PMOS pipe all is connected the drain electrode that the 7th PMOS manages with the grid of the 6th PMOS pipe, and the 5th PMOS pipe is connected supply voltage with the source electrode of the 6th PMOS pipe, and the drain electrode of the 5th PMOS pipe connects the source electrode of the 7th PMOS pipe; The drain electrode of the 6th PMOS pipe connects the source electrode of the 8th PMOS pipe;
The 7th PMOS pipe all is connected second bias voltage with the grid of the 8th PMOS pipe, and the drain electrode of the 7th PMOS pipe connects the drain electrode of the 9th NMOS pipe;
The drain electrode of the 8th PMOS pipe connects the drain electrode of the tenth NMOS pipe, and as the output terminal of said error amplifier;
The 9th NMOS pipe all is connected the 3rd bias voltage with the grid of the tenth NMOS pipe, and the source electrode of the 9th NMOS pipe connects the drain electrode of the 11 NMOS pipe, and the source electrode of the tenth NMOS pipe connects the drain electrode of the 12 NMOS pipe;
The 11 NMOS pipe all is connected the 4th bias voltage, source grounding with the grid of the 12 NMOS pipe.
Alternatively, said buffer circuit comprises: the 13 PMOS pipe and the 14 PMOS pipe; The source electrode of said the 13 PMOS pipe connects supply voltage, and grid connects first bias voltage, and drain electrode connects the source electrode of the 14 PMOS pipe, and as the output terminal of said buffer circuit; The grounded drain of said the 14 PMOS pipe, grid connects the output terminal of error amplifier.
Alternatively, said dividing potential drop feedback circuit comprises: first divider resistance and second divider resistance; First end of said first divider resistance connects said PMOS adjustment transistor drain, and second end connects first end of second divider resistance, and as the output branch pressure voltage of said dividing potential drop feedback circuit; The second end ground connection of said second divider resistance.
Alternatively, said dividing potential drop feedback circuit also comprises first electric capacity, and an end of said first electric capacity connects said PMOS adjustment transistor drain, and the other end connects second end of first divider resistance.
Compared with prior art, technical scheme of the present invention has the following advantages at least:
Low-dropout linear voltage-regulating circuit comprises that error amplifier, compensating circuit, buffer circuit, PMOS adjustment transistor, NMOS recommend pipe, dividing potential drop feedback circuit and output circuit.Said error amplifier, compensating circuit, buffer circuit, PMOS adjustment transistor, dividing potential drop feedback circuit and output circuit have constituted the main control loop, and this main control loop can provide bigger driving force to satisfy loading demand.Said error amplifier, compensating circuit, NMOS recommend pipe, dividing potential drop feedback circuit and output circuit and have then formed the assist control loop; The breadth length ratio that NMOS in this assist control loop recommends pipe than main control loop PMOS adjust transistorized breadth length ratio little many (it is more than 1000 times of breadth length ratio that NMOS recommends pipe that said PMOS adjusts transistorized breadth length ratio); The stray capacitance of himself is adjusted transistorized stray capacitance with PMOS and is compared and can ignore; Therefore NMOS recommend tube grid electric capacity can be when load current suddenlys change fast charging and discharging; Thereby the negative feedback that can promptly produce the assist control loop suppresses overcharged voltage and the spike of owing charging voltage effectively; Make output voltage quickly recover to stationary value, so not only improved the transient response speed of circuit but also improved the precision of output voltage.
In addition, said NMOS recommends pipe when load current suddenlys change, and can directly skip buffer circuit, thereby has reduced the transmission time-delay of signal in the assist control loop; And; Said NMOS recommends pipe and said PMOS adjusts the push-pull type export structure that transistor has also constituted circuit of the present invention jointly; This push-pull type export structure has the good advantage of the output linearity, thereby has further improved the performance of said low-dropout linear voltage-regulating circuit.
Said compensating circuit is the zero compensation circuit; Compare with miller-compensated circuit of the prior art; Zero compensation circuit in the technical scheme of the present invention can avoid miller-compensated circuit when high frequency, the power supply interference to be introduced directly into the defective of circuit output end, thereby can improve the PSRR of low-dropout linear voltage-regulating circuit effectively.
Description of drawings
Fig. 1 is the synoptic diagram of prior art mesolow difference linear voltage-stabilizing circuit;
Fig. 2 is the synoptic diagram of an embodiment of low-dropout linear voltage-regulating circuit of the present invention;
Fig. 3 is the circuit diagram of an embodiment of low-dropout linear voltage-regulating circuit of the present invention;
Fig. 4 is the gain phase curve figure of low-dropout linear voltage-regulating circuit of the present invention under the 10mA load;
Fig. 5 is the gain phase curve figure of low-dropout linear voltage-regulating circuit of the present invention under the 100mA load;
Fig. 6 is the transient response figure of low-dropout linear voltage-regulating circuit of the present invention when load changing;
Fig. 7 is the load regulation performance plot of low-dropout linear voltage-regulating circuit of the present invention when supply voltage is 3.3V;
Fig. 8 is the line regulation performance plot of low-dropout linear voltage-regulating circuit of the present invention under the 100mA load.
Embodiment
Described in background technology, traditional LDO circuit has that transient response speed is slow, the not high defective of precision of output voltage.
Increased a NMOS in the low-dropout linear voltage-regulating circuit of technical scheme of the present invention and recommended pipe, said NMOS recommends the source ground of pipe, and grid connects the output terminal of error amplifier, and drain electrode connects the output terminal of LDO circuit, i.e. PMOS adjustment transistor drain; And this NMOS recommends very little that the size of pipe can do; Therefore the stray capacitance of its generation is very little; So just can produce response fast; Form a response loop fast, thereby remedied the slow-footed defective of large-sized PMOS adjustment transient response, improved the transient response speed of this circuit greatly.
The stray capacitance that said NMOS recommends pipe is very little; Therefore when load current suddenlys change; Error amplifier is very fast to the speed that discharges and recharges of this stray capacitance; Overcharged voltage in transient process, occurs or owe the charging voltage spike thereby can suppress output voltage at the right time, thus the precision of raising output voltage.
In addition, said NMOS recommends pipe and PMOS adjustment transistor has constituted the push-pull type export structure, thereby has the good advantage of the output linearity, therefore improves the precision of output voltage.
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Set forth detail in the following description so that make much of the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention does not receive the restriction of following disclosed embodiment.
Fig. 2 shows the synoptic diagram of an embodiment of low-dropout linear voltage-regulating circuit of the present invention.With reference to figure 2, said low-dropout linear voltage-regulating circuit comprises: error amplifier OP1, buffer circuit buffer1, PMOS adjustment transistor MP1, NMOS recommend pipe MN1, dividing potential drop feedback circuit 30, output circuit 40 and compensating circuit 50.
As shown in Figure 2; In this embodiment; Said low-dropout linear voltage-regulating circuit comprises two feedback loops; Wherein said error amplifier OP1, compensating circuit 50, buffer circuit buffer1, PMOS adjustment transistor MP1, dividing potential drop feedback circuit 30 and output circuit 40 constitute the main control loop, and the transient response speed of this main control loop is slow, therefore when load current suddenlys change, can cause the output voltage precision not high.
Said error amplifier OP1, compensating circuit 50, NMOS recommend pipe MN1, dividing potential drop feedback circuit 30 and output circuit 40 and have constituted another feedback loop; It is the assist control loop; This assist control loop has the fast advantage of transient response speed; Thereby can suppress overcharged voltage and the spike of owing charging voltage effectively, make output voltage V out quickly recover to stationary value, and then improved the precision of output voltage.
This embodiment remedies the deficiency of main control loop just through above-mentioned assist control loop, thereby has greatly improved the fast and output voltage precision of transient response speed of technical scheme mesolow difference linear voltage-stabilizing circuit of the present invention.
Particularly, the first input end of said error amplifier OP1 (negative-phase input) receives reference voltage V bg; Second input end (normal phase input end) connects the output terminal of dividing potential drop feedback circuit 30, is used to receive the branch pressure voltage Vfb of said dividing potential drop feedback circuit 30 outputs; Said error amplifier OP1 compares said reference voltage V bg and branch pressure voltage Vfb, and exports comparative result to buffer circuit buffer1.
Said buffer circuit buffer1; Be used for said low-dropout linear voltage-regulating circuit is carried out impedance matching with the output high impedance node of isolation error amplifier OP1 and the big stray capacitance node of grid of PMOS adjustment transistor MP1; And after driving being provided, said comparative result is exported to the grid of said PMOS adjustment transistor MP1 for comparative result.
The source electrode of said PMOS adjustment transistor MP1 connects supply voltage VDDA, and drain electrode is used for output voltage V out is exported as the output terminal of said low-dropout linear voltage-regulating circuit.
Said output circuit 40 is used to reduce the ripple of output voltage V out.
Particularly, said output circuit 40 comprises output capacitance CL, equivalent series resistance RL.The end of said equivalent series resistance RL connects the drain electrode of said PMOS adjustment transistor MP1, and the other end connects the end of said output capacitance CL; The other end ground connection GND of said output capacitance CL.
Similar with the output circuit shown in Fig. 1, output circuit 40 not only can reduce because the output voltage ripple that causes during load changing in this embodiment, and can also be provided high frequency zero point for the feedback loop of system.
Said dividing potential drop feedback circuit 30 is connected between the drain electrode and ground GND of said PMOS adjustment transistor MP1, and branch pressure voltage Vfb is fed back to second input end (normal phase input end) of error amplifier OP1.
Particularly, said dividing potential drop feedback circuit 30 is a partial pressure unit, comprising: the first divider resistance R1 and the second divider resistance R2.
The end of the said first divider resistance R1 connects the drain electrode of said PMOS adjustment transistor MP1; The other end connects the end of the second divider resistance R2 and as the output terminal of said dividing potential drop feedback circuit 30, branch pressure voltage Vfb is fed back to error amplifier OP1.Particularly, in the present embodiment, said branch pressure voltage Vfb is received by the grid of the 3rd PMOS pipe M3 among the error amplifier OP1.The other end ground connection of the said second divider resistance R2.
The structure of said dividing potential drop feedback circuit 30 and principle of work and feedback network shown in Figure 1 are similar, so repeat no more at this.
Continuation is with reference to figure 2, and in this embodiment, said dividing potential drop feedback circuit 30 also comprises capacitor C 3.The noise that can be used for reducing circuit of said capacitor C 3, and the gain margin of raising circuit.
Said NMOS recommends the source ground of pipe MN1, and grid connects the output terminal of error amplifier OP1, and drain electrode connects the output terminal of said low-dropout linear voltage-regulating circuit, the drain electrode of promptly said PMOS adjustment transistor MP1.
Particularly, the size that said NMOS recommends pipe MN1 is very little, and for example its breadth length ratio can be 20 μ m/0.5 μ m, and the stray capacitance of himself is like grid source capacitor C gs and gate leakage capacitance Cgd also very little (all below 50fF).
When load current suddenlys change; Assist control loop in this embodiment is accomplished the discharging and recharging in moment of grid source capacitor C gs that said NMOS recommends pipe MN1; Because said NMOS recommends the grid voltage pace of change of pipe MN1 and is exceedingly fast; Its drain terminal voltage will obtain the timely control of assist control loop, has also just suppressed the overcharged voltage that output voltage V out occurs timely or owe the charging voltage spike in transient process; Because overcharged voltage and owe the charging voltage amplitude and weakened greatly by the assist control loop; Therefore the transit time that the output voltage V out of the low-dropout linear voltage-regulating circuit of this embodiment returned to its steady-state value after load changing finished is by shortening greatly; Thereby improved the precision of output voltage greatly, and the load regulation of this circuit is greatly improved also.
First end of said compensating circuit 50 connects supply voltage VDDA, and the other end connects the output terminal of error amplifier OP1.
Particularly, there are two limits of leaning on closerly in low-dropout linear voltage-regulating circuit shown in Figure 2, and a limit is positioned at the output terminal of error amplifier OP1, and another limit is positioned at the output terminal of this circuit, the drain electrode of promptly said PMOS adjustment transistor MP1.The effect of said compensating circuit 50 is to make the bandwidth inner feedback loop of system to have only a dominant pole, to guarantee that feedback control loop all is stable under various conditions.
Said compensating circuit 50 can be miller-compensated circuit.Similar with structure shown in Fig. 1 and connected mode; One end of said miller-compensated circuit connects the output terminal of error amplifier OP1; The other end connects the drain electrode of PMOS adjustment transistor MP1, and its principle of work is well known to those skilled in the art, so repeat no more at this.
But said miller-compensated circuit can directly disturb the output terminal of guiding to low-dropout linear voltage-regulating circuit with power supply when high frequency, thereby worsens the PSRR of circuit.This be because; When high frequency; The short circuit effect of miller-compensated capacitor C c is adjusted PMOS the grid of transistor MP1 with the drain electrode short circuit; And grid voltage and the source voltage (being supply voltage VDDA) of said PMOS adjustment transistor MP1 have the stronger effect of following, so the interference noise of power supply can directly pass to the output terminal of low-dropout linear voltage-regulating circuit through miller-compensated capacitor C c.
Preferably, said compensating circuit 50 can also be the zero compensation circuit.With reference to shown in Figure 3, said compensating circuit 50 comprises compensating resistance Rz and building-out capacitor Cz.The end of said building-out capacitor Cz connects supply voltage VDDA, and the other end connects the end of said compensating resistance Rz, and the other end of said compensating resistance Rz connects the grid that said NMOS recommends pipe MN1.
Different with miller-compensated circuit, the effect of zero compensation circuit shown in Figure 3 is the limit of compensating error amplifier OP1 output terminal, and then makes circuit be in steady state (SS), improves the phase margin of circuit.Adopt zero compensation circuit shown in Figure 3 to avoid effectively when high frequency, power supply being disturbed the defective of directly introducing circuit output end, thereby improved the PSRR of circuit.
Fig. 3 shows the circuit diagram of an embodiment of low-dropout linear voltage-regulating circuit of the present invention.With reference to figure 3, said error amplifier OP1 comprises: tail current source and input difference to 101, PMOS common-source common-gate current mirror 102 and NMOS constant-current source bias and folded tube 103.
Wherein, tail current source and input difference are made up of PMOS pipe M1, the 2nd PMOS pipe M2, the 3rd PMOS pipe M3 and the 4th PMOS pipe M4 101; PMOS common-source common-gate current mirror 102 is made up of the 5th PMOS pipe M5, the 6th PMOS pipe M6, the 7th PMOS pipe M7 and the 8th PMOS pipe M8; NMOS constant-current source bias and folded tube 103 are made up of the 9th NMOS pipe M9, the tenth NMOS pipe M10, the 11 NMOS pipe M11 and the 12 NMOS pipe M12.
The grid of the one PMOS pipe M1 connects the first bias voltage Vb1, and source electrode connects supply voltage VDDA, and drain electrode connects the source electrode of the 2nd PMOS pipe M2.
The grid of the 2nd PMOS pipe M2 connects the second bias voltage Vb2, and drain electrode connects the source electrode of the 3rd PMOS pipe M3 and the 4th PMOS pipe M4.
The 3rd PMOS pipe M3 grid connects the branch pressure voltage Vfb of dividing potential drop feedback circuit 30 outputs, and drain electrode connects the drain electrode of the 11 NMOS pipe M11.
The grid of the 4th PMOS pipe M4 connects reference voltage V bg, and said reference voltage V bg and supply voltage VDDA, temperature and technology all have nothing to do; Drain electrode connects the drain electrode of the 12 NMOS pipe M12.
The 5th PMOS pipe M5 all is connected the drain electrode that the 7th PMOS manages M7 with the grid of the 6th PMOS pipe M6, and the source electrode of the 5th PMOS pipe M5 and the 6th PMOS pipe M6 is connected supply voltage VDDA, and the drain electrode of the 5th PMOS pipe M5 connects the source electrode of the 7th PMOS pipe M7; The drain electrode of the 6th PMOS pipe M6 connects the source electrode of the 8th PMOS pipe M8.
The 7th PMOS pipe M7 all is connected the second bias voltage Vb2 with the grid of the 8th PMOS pipe M8, and the drain electrode of the 7th PMOS pipe M7 connects the drain electrode of the 9th NMOS pipe M9.
The drain electrode of the 8th PMOS pipe M8 connects the drain electrode of the tenth NMOS pipe M10, and as the output terminal of said error amplifier OP1.
The 9th NMOS pipe M9 all is connected the 3rd bias voltage Vb3 with the grid of the tenth NMOS pipe M10, and the source electrode of the 9th NMOS pipe M9 connects the drain electrode of the 11 NMOS pipe M11, and the source electrode of the tenth NMOS pipe M10 connects the drain electrode of the 12 NMOS pipe M12.
The 11 NMOS pipe M11 all is connected the 4th bias voltage Vb4, source grounding GND with the grid of the 12 NMOS pipe M12.
Said error amplifier OP1 is collapsible cascade error amplifier, and is similar with the structure and the principle of collapsible cascade error amplifier in the prior art, so repeat no more at this.
Continuation is with reference to figure 3, and said buffer circuit buffer1 is a source follower, comprising: the 13 PMOS pipe M13 and the 14 PMOS pipe M14.
The source electrode of said the 13 PMOS pipe M13 connects supply voltage VDDA, and grid connects the first bias voltage Vb1, and drain electrode connects the source electrode of the 14 PMOS pipe M14, and as the output terminal of said buffer circuit buffer1.The grounded drain GND of said the 14 PMOS pipe M14, grid connects the output terminal of error amplifier OP1, i.e. the drain electrode of the 8th PMOS pipe M8.
In the present embodiment, said buffer circuit buffer1 is as the intermediate buffering level of low-dropout linear voltage-regulating circuit, and being mainly used in provides impedance matching preferably and for PMOS adjusts transistor MP1 bigger driving force is provided.The middle buffer level of said buffer circuit buffer1 and prior art low-dropout linear voltage-regulating circuit is similar, so repeat no more at this.
Continuation is with reference to figure 3, and the source electrode of said PMOS adjustment transistor MP1 connects supply voltage VDDA, and drain electrode connects an end of dividing potential drop feedback circuit 30, and grid connects the output terminal of buffer circuit buffer1, i.e. the drain electrode of the 13 PMOS pipe M13.
In the present embodiment, the size of said PMOS adjustment transistor MP1 is bigger, and its breadth length ratio can be 1000 times of the said NMOS breadth length ratio of recommending pipe MN1 or more than 1000 times, for example can be 1333 times.
Well known to a person skilled in the art that the load capacity of low-dropout linear voltage-regulating circuit is mainly determined by the breadth length ratio of said PMOS adjustment transistor MP1.In other words, under the constant situation of pressure reduction (dropout) voltage and conducting resistance, LDO circuit load ability is high more in guaranteeing circuit, and the size (breadth length ratio in other words) that said PMOS adjusts transistor MP1 is also big more.
But the breadth length ratio (size in other words) of PMOS adjustment transistor MP1 is big more, and its corresponding parasitic grid source capacitor C gs and gate leakage capacitance Cgd is also big more.When load current IL increases suddenly or reduces suddenly; LDO output voltage V out has a transient state fluctuation; LDO main control loop guarantees that output voltage V out is constant basically because the negative feedback of dividing potential drop feedback circuit 30 will discharge and recharge PMOS adjustment transistor MP1 gate node thereby make this grid voltage adjust to certain suitable value in this transient process.
But; The driving force of error amplifier OP1 and buffer circuit buffer1 (source follower) is limited after all; So big stray capacitance Cgs, Cgd that large scale PMOS adjustment transistor MP1 carries will cause its grid voltage speed of discharging and recharging to become slow all the more, cause LDO output voltage V out very big charging voltage spike (undershoot) and the overcharged voltage spike (overshoot) owed in transient process, to occur.
And that big more undershoot and overshoot voltage must make the output voltage V out of LDO return to the time that steady-state value needs is also long more, this segment length in the time LDO output voltage V out constantly change, thereby seriously influenced precision.In a lot of high-speed applications environment, such resume speed and output accuracy are unacceptable.Typical example is the power supply of pel array in the cmos image sensor (CMOS image sensor); Because reading all of each Pixel Information accomplished in the microsecond level; And all be accompanied by the interference of adjacent lines pixel work; If the pixel power supply is slow to load current transient response speed, offensive horizontal stripe will appear on image.In a word, the main control loop of LDO is a slow loop, the loop that the transient control precision is not high.
In order to solve the problem that main control loop transient response speed is slow, the output voltage precision is not high, increased a NMOS in the present embodiment and recommended pipe MN1.
As shown in Figure 3, said NMOS recommends the source ground of pipe MN1, and drain electrode connects the drain electrode of said PMOS adjustment transistor MP1, and grid connects the output terminal of error amplifier OP1, the drain electrode of promptly said the 8th PMOS pipe M8.
Said NMOS recommends pipe MN1 and constitutes the second feedback loop of the LDO circuit of present embodiment, i.e. assist control loop with error amplifier OP1, dividing potential drop feedback circuit 30 and output circuit 40.
In the present embodiment; The size (breadth length ratio in other words) of recommending pipe MN1 owing to said NMOS is little more a lot of than the size of said PMOS adjustment transistor MP1; Therefore, said NMOS recommends comparing fully and can ignoring of PMOS adjustment transistor MP1 in the pipe MN1 stray capacitance (grid source capacitor C gs, gate leakage capacitance Cgd) of carrying and the main control loop.
When load current IL suddenlys change; It is very fast that the grid stray capacitance that error amplifier OP1 recommends pipe MN1 to NMOS discharges and recharges speed; Therefore, can suppress undershoot and the overshoot due to voltage spikes that LDO output voltage V out occurs at the right time in transient process.
Because undershoot and overshoot due to voltage spikes amplitude are weakened by above-mentioned assist control loop greatly; So LDO output voltage V out can return to steady-state value soon; Be that load changing finishes the quilt stabilization time shortening greatly that back LDO output voltage returns to its steady-state value; Thereby the precision that makes output voltage V out is able to significantly improve, and load regulation also is greatly improved, and is fit to very much be applied in all kinds of high speed SOC chips.In a word, the assist control loop of LDO is a fast loop, can significantly improve the loop of system accuracy.
In addition; Said NMOS recommends the assist control loop at pipe MN1 place when load current suddenlys change; Directly the output signal with error amplifier OP1 transfers to the output terminal of circuit by the negative feedback that said assist control loop forms, and no longer passes through buffer circuit bufffer1 (source follower).So not only reduced the signal transmission time-delay of assist control loop (fast loop); And said NMOS recommends pipe MN1 and constitutes the push-pull type output-stage circuit of present embodiment LDO with PMOS adjustment transistor MP1; Make it have the advantage of push-pull circuit; That is to say that the output linearity of this push-pull type output-stage circuit is better, thereby improved the performance of said LDO circuit.
The inventor has carried out experiment simulation to the low-dropout linear voltage-regulating circuit of technical scheme of the present invention based on Korea S's Dongbu0.18 μ m CIS technology, particularly simulation result such as Fig. 4 ~ shown in Figure 8.
Fig. 4 is the gain phase curve figure of low-dropout linear voltage-regulating circuit of the present invention under the 10mA loading condition.Wherein, the resistance of the equivalent series resistance RL in the output circuit 40 is 0.1 Ω.
Can draw with reference to the N0 point shown in the figure 4 ~ N3 point, the low-dropout linear voltage-regulating circuit of technical scheme of the present invention is that phase margin under the 10mA situation is 81.02deg at load current IL, and gain margin is-44.0dB.
Fig. 5 is the gain phase curve figure of low-dropout linear voltage-regulating circuit of the present invention under the 100mA loading condition.Wherein, the resistance of the equivalent series resistance RL in the output circuit 40 is 0.1 Ω.
Can draw with reference to the N4 point shown in the figure 5 ~ N7 point, it is that phase margin under the 100mA situation is 76.56deg that the low-dropout linear voltage-regulating circuit of technical scheme of the present invention is operated in load current IL, and gain margin is-23.99dB.
Can find out that through Fig. 4 and Fig. 5 the gain margin of the low-dropout linear voltage-regulating circuit of technical scheme of the present invention and phase margin are very big, thereby can guarantee the loop stability of circuit.
Fig. 6 is the transient response figure of low-dropout linear voltage-regulating circuit of the present invention when load changing.Load changing described herein refers to: the situation the when rising edge of load current IL or negative edge are 0.1 μ s.
With reference to the point of the N8 among the figure 6 ~ N10 point, the load current IL of circuit sports 100mA from 0mA when 100 μ s, and when 120 μ s, sports 0mA from 100mA again.
Suddenly change correspondingly with above-mentioned load current; The low-dropout linear voltage-regulating circuit of technical scheme of the present invention the moment (100 μ s) that load current IL rises suddenly transient state appearred and owe the charging voltage spike; Shown in M11 point among Fig. 6 and M12 point, the output voltage of circuit of the present invention becomes 2.989V from 3.0V.But when load current IL rose to 100mA by 0mA suddenly, it is very little that the transient state of circuit is owed charging voltage, has only about 11mV (3V-2.989V=0.011V).
Similarly; The overcharged voltage spike of transient state has appearred in the low-dropout linear voltage-regulating circuit of technical scheme of the present invention in the moment (120 μ s) that load current descends suddenly; Shown in M13 point among Fig. 6 and M14 point, after load current IL descended suddenly, the output voltage of circuit became 3.021V from 3V.But when load current IL dropped to 0mA by 100mA, the transient state overcharged voltage of circuit was also very little, had only about 21mV (3.021V-3V=0.021V).
Can know by above-mentioned analysis; The low-dropout linear voltage-regulating circuit of technical scheme of the present invention can suppress effectively when load current suddenlys change that output voltage occurs in transient process owes charging voltage and overcharged voltage spike, thereby makes output voltage can return to stationary value (the voltage stationary value among Fig. 6 is 3V) soon.
Fig. 7 is the load regulation performance plot of low-dropout linear voltage-regulating circuit of the present invention when supply voltage (VDDA) is 3.3V.
Can know with reference to the point of the N15 among the figure 7, when load current IL when 0mA becomes 100mA, the changing value of the output voltage of technical scheme mesolow difference linear voltage-stabilizing circuit of the present invention is very little, approximately has only 29.6 μ V.In other words, the load regulation of technical scheme mesolow difference linear voltage-stabilizing circuit of the present invention when supply voltage (VDDA) is 3.3V is 0.296 μ V/mA.
Fig. 8 is the line regulation performance plot of low-dropout linear voltage-regulating circuit of the present invention under the 100mA load.
Can know by point of the N16 among Fig. 8 and N17 point, when input voltage when 3.2V changes to 3.7V, output voltage has changed 50.3 μ V, promptly the line regulation of LDO of the present invention is 0.1006mv/V.
Can obtain the main performance index of the low-dropout linear voltage-regulating circuit of technical scheme of the present invention by above-mentioned simulation result.For clearer, show the performance advantage of circuit of the present invention significantly, the inventor also compares the present invention with relevant LDO design, as shown in table 1.
Wherein the 3rd classify main performance index of the present invention as; First classifies people such as Mohammad Al-Shyoukh as adopts the performance index miller-compensated and design of buffer stage output impedance decay technique, and second classifies people such as Yi Wang as adopts the miller-compensated performance index that add the design of transient response intensifier circuit of nested type.
Table 1
Can find out that through the contrast in the table 1 low-dropout linear voltage-regulating circuit of technical scheme of the present invention is owed aspects such as charging voltage, transient state overcharged voltage, transient response release time, load regulation, line regulation in transient state and all increased significantly.
To sum up, comprised main control loop and assist control loop in the low-dropout linear voltage-regulating circuit of technical scheme of the present invention, though said main control loop transient response speed is slower, it can provide bigger driving force; Said assist control loop has the transient response speed that is exceedingly fast, and has greatly improved the precision of output voltage.These two loops complement each other, and make that LDO of the present invention really has at a high speed, high-precision unique advantage.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection domain of technical scheme of the present invention according to technical spirit of the present invention.

Claims (7)

1. a low-dropout linear voltage-regulating circuit is characterized in that, comprising: error amplifier, compensating circuit,
Buffer circuit, PMOS adjustment transistor, NMOS recommend pipe, dividing potential drop feedback circuit and output circuit;
Said error amplifier is used for the branch pressure voltage and the reference voltage of said dividing potential drop feedback circuit output are compared, and exports comparative result to said buffer circuit;
Said buffer circuit; Be used to carry out impedance matching and adjust transistorized grid stray capacitance node with output impedance node and the PMOS that isolates error amplifier; And after driving being provided, exporting said comparative result to PMOS and adjust transistorized grid for the comparative result that receives;
Said PMOS adjusts transistorized source electrode and connects supply voltage, and drain electrode is as the output terminal of low-dropout linear voltage-regulating circuit;
Said dividing potential drop feedback circuit is used for the voltage of said PMOS adjustment transistor drain is carried out dividing potential drop, and branch pressure voltage is fed back to error amplifier;
The grid that said NMOS recommends pipe connects the output terminal of said error amplifier, and drain electrode connects said PMOS adjustment transistor drain, source ground;
Said output circuit connects said PMOS adjustment transistor drain, is used to reduce output voltage ripple;
One end of said compensating circuit connects supply voltage, and the other end connects the output terminal of said error amplifier, is used for said low-dropout linear voltage-regulating circuit is compensated so that it is stable.
2. low-dropout linear voltage-regulating circuit as claimed in claim 1 is characterized in that, said PMOS adjusts ratio between the breadth length ratio that transistorized breadth length ratio and said NMOS recommend pipe more than or equal to 1000.
3. low-dropout linear voltage-regulating circuit as claimed in claim 1 is characterized in that, said compensating circuit comprises: compensating resistance and building-out capacitor; One end of said building-out capacitor connects supply voltage, and the other end connects an end of said compensating resistance; The other end of said compensating resistance connects the output terminal of error amplifier.
4. low-dropout linear voltage-regulating circuit as claimed in claim 1 is characterized in that, said error amplifier comprises: tail current source and input difference are to, PMOS common-source common-gate current mirror and NMOS constant-current source bias and folded tube;
Said tail current source and input difference are to comprising PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe and the 4th PMOS pipe; Said PMOS common-source common-gate current mirror comprises the 5th PMOS pipe, the 6th PMOS pipe, the 7th PMOS pipe and the 8th PMOS pipe; Said NMOS constant-current source bias and folded tube comprise the 9th NMOS pipe, the tenth NMOS pipe, the 11 NMOS pipe and the 12 NMOS pipe;
The grid of the one PMOS pipe connects first bias voltage, and source electrode connects supply voltage, and drain electrode connects the source electrode of the 2nd PMOS pipe;
The grid of the 2nd PMOS pipe connects second bias voltage, and drain electrode connects the source electrode of the 3rd PMOS pipe and the 4th PMOS pipe;
The branch pressure voltage of the connection dividing potential drop feedback circuit output of the 3rd gate pmos utmost point, drain electrode connects the drain electrode of the 11 NMOS pipe;
The grid of the 4th PMOS pipe connects reference voltage; Drain electrode connects the drain electrode of the 12 NMOS pipe;
The 5th PMOS pipe all is connected the drain electrode that the 7th PMOS manages with the grid of the 6th PMOS pipe, and the 5th PMOS pipe is connected supply voltage with the source electrode of the 6th PMOS pipe, and the drain electrode of the 5th PMOS pipe connects the source electrode of the 7th PMOS pipe; The drain electrode of the 6th PMOS pipe connects the source electrode of the 8th PMOS pipe;
The 7th PMOS pipe all is connected second bias voltage with the grid of the 8th PMOS pipe, and the drain electrode of the 7th PMOS pipe connects the drain electrode of the 9th NMOS pipe;
The drain electrode of the 8th PMOS pipe connects the drain electrode of the tenth NMOS pipe, and as the output terminal of said error amplifier;
The 9th NMOS pipe all is connected the 3rd bias voltage with the grid of the tenth NMOS pipe, and the source electrode of the 9th NMOS pipe connects the drain electrode of the 11 NMOS pipe, and the source electrode of the tenth NMOS pipe connects the drain electrode of the 12 NMOS pipe;
The 11 NMOS pipe all is connected the 4th bias voltage, source grounding with the grid of the 12 NMOS pipe.
5. low-dropout linear voltage-regulating circuit as claimed in claim 1 is characterized in that, said buffer circuit comprises: the 13 PMOS pipe and the 14 PMOS pipe;
The source electrode of said the 13 PMOS pipe connects supply voltage, and grid connects first bias voltage, and drain electrode connects the source electrode of the 14 PMOS pipe, and as the output terminal of said buffer circuit;
The grounded drain of said the 14 PMOS pipe, grid connects the output terminal of error amplifier.
6. low-dropout linear voltage-regulating circuit as claimed in claim 1 is characterized in that, said dividing potential drop feedback circuit comprises: first divider resistance and second divider resistance; First end of said first divider resistance connects said PMOS adjustment transistor drain, and second end connects first end of second divider resistance, and as the output branch pressure voltage of said dividing potential drop feedback circuit; The second end ground connection of said second divider resistance.
7. low-dropout linear voltage-regulating circuit as claimed in claim 1 is characterized in that, said dividing potential drop feedback circuit also comprises first electric capacity, and an end of said first electric capacity connects said PMOS adjustment transistor drain, and the other end connects second end of first divider resistance.
CN201210173613.6A 2012-05-30 2012-05-30 Low dropout regulator CN102707754B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201210173613.6A CN102707754B (en) 2012-05-30 2012-05-30 Low dropout regulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201210173613.6A CN102707754B (en) 2012-05-30 2012-05-30 Low dropout regulator

Publications (2)

Publication Number Publication Date
CN102707754A true CN102707754A (en) 2012-10-03
CN102707754B CN102707754B (en) 2014-08-13

Family

ID=46900641

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210173613.6A CN102707754B (en) 2012-05-30 2012-05-30 Low dropout regulator

Country Status (1)

Country Link
CN (1) CN102707754B (en)

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102880218A (en) * 2012-10-12 2013-01-16 西安三馀半导体有限公司 Wide-input range linear voltage regulator
CN103076835A (en) * 2013-01-28 2013-05-01 上海宏力半导体制造有限公司 Low drop-out linear voltage stabilizer and regulation circuit thereof
CN103760942A (en) * 2014-01-07 2014-04-30 无锡芯响电子科技有限公司 Transient enhancement circuit applicable to low dropout regulator
CN104052412A (en) * 2014-06-05 2014-09-17 无锡中星微电子有限公司 Modified miller compensation amplifier
CN104656733A (en) * 2015-02-12 2015-05-27 天津大学 LDO (low dropout regulator) capable of outputting ultra-low quiescent current in self-adaptation way
CN105005351A (en) * 2015-07-23 2015-10-28 中山大学 Cascode fully integrated low-dropout linear voltage regulator circuit
CN105159383A (en) * 2015-08-24 2015-12-16 电子科技大学 Low dropout regulator with high power supply rejection ratio
CN105955390A (en) * 2016-07-01 2016-09-21 唯捷创芯(天津)电子技术股份有限公司 Low-dropout linear regulator module, chip and communication terminal
CN106406411A (en) * 2016-12-08 2017-02-15 上海爱信诺航芯电子科技有限公司 Low dropout regulator circuit and power supply
CN106502302A (en) * 2017-01-10 2017-03-15 南方科技大学 A kind of low pressure difference linear voltage regulator
CN106774578A (en) * 2017-01-10 2017-05-31 南方科技大学 Low pressure difference linear voltage regulator
CN107390772A (en) * 2017-08-31 2017-11-24 电子科技大学 High power supply voltage low-power consumption low pressure difference linear voltage regulator
CN107402594A (en) * 2017-08-31 2017-11-28 电子科技大学 Realize the low-power consumption low pressure difference linear voltage regulator of high power supply voltage transformation
CN108536206A (en) * 2018-03-22 2018-09-14 广州慧智微电子有限公司 A kind of voltage regulator and voltage adjusting method
CN109656300A (en) * 2019-02-27 2019-04-19 电子科技大学 A kind of Fast Load response LDO based on dual power rail power supply
CN110286709A (en) * 2018-03-19 2019-09-27 株式会社东芝 Constant voltage circuit
CN110299843A (en) * 2019-06-14 2019-10-01 上海芯导电子科技有限公司 A kind of composite DC/DC circuit
CN110320963A (en) * 2019-08-05 2019-10-11 昆山锐芯微电子有限公司 Low-dropout linear voltage-regulating circuit
CN111290460A (en) * 2020-02-25 2020-06-16 电子科技大学 Low dropout regulator with high power supply rejection ratio and rapid transient response
CN112015224A (en) * 2020-10-22 2020-12-01 深圳市汇顶科技股份有限公司 Low dropout regulator and power supply circuit
CN110299843B (en) * 2019-06-14 2021-05-25 上海芯导电子科技有限公司 Composite DCDC circuit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10133287B2 (en) * 2015-12-07 2018-11-20 Macronix International Co., Ltd. Semiconductor device having output compensation

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1365302A1 (en) * 2002-05-20 2003-11-26 Texas Instruments Incorporated Low drop-out voltage regulator
US20070241728A1 (en) * 2006-04-18 2007-10-18 Atmel Corporation Low-dropout voltage regulator with a voltage slew rate efficient transient response boost circuit
CN101339443A (en) * 2008-08-08 2009-01-07 武汉大学 Broad output current scope low pressure difference linear manostat
CN101727120A (en) * 2009-11-26 2010-06-09 四川和芯微电子股份有限公司 Linear voltage regulator circuit for rapidly responding to load change without plug-in capacitor
CN102096434A (en) * 2010-12-23 2011-06-15 东南大学 High-slew-rate error amplifier-based high-accuracy and high-speed low dropout (LDO) regulator circuit
CN102279612A (en) * 2011-05-11 2011-12-14 电子科技大学 Low dropout linear regulator
CN102393778A (en) * 2011-08-30 2012-03-28 四川和芯微电子股份有限公司 Low-voltage-difference linear stabilized-voltage circuit and system

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1365302A1 (en) * 2002-05-20 2003-11-26 Texas Instruments Incorporated Low drop-out voltage regulator
US20070241728A1 (en) * 2006-04-18 2007-10-18 Atmel Corporation Low-dropout voltage regulator with a voltage slew rate efficient transient response boost circuit
CN101339443A (en) * 2008-08-08 2009-01-07 武汉大学 Broad output current scope low pressure difference linear manostat
CN101727120A (en) * 2009-11-26 2010-06-09 四川和芯微电子股份有限公司 Linear voltage regulator circuit for rapidly responding to load change without plug-in capacitor
CN102096434A (en) * 2010-12-23 2011-06-15 东南大学 High-slew-rate error amplifier-based high-accuracy and high-speed low dropout (LDO) regulator circuit
CN102279612A (en) * 2011-05-11 2011-12-14 电子科技大学 Low dropout linear regulator
CN102393778A (en) * 2011-08-30 2012-03-28 四川和芯微电子股份有限公司 Low-voltage-difference linear stabilized-voltage circuit and system

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102880218A (en) * 2012-10-12 2013-01-16 西安三馀半导体有限公司 Wide-input range linear voltage regulator
CN102880218B (en) * 2012-10-12 2014-12-17 西安三馀半导体有限公司 Wide-input range linear voltage regulator
CN103076835A (en) * 2013-01-28 2013-05-01 上海宏力半导体制造有限公司 Low drop-out linear voltage stabilizer and regulation circuit thereof
CN103760942A (en) * 2014-01-07 2014-04-30 无锡芯响电子科技有限公司 Transient enhancement circuit applicable to low dropout regulator
CN103760942B (en) * 2014-01-07 2015-10-28 无锡芯响电子科技有限公司 Be applicable to the transient state intensifier circuit of low pressure difference linear voltage regulator
CN104052412A (en) * 2014-06-05 2014-09-17 无锡中星微电子有限公司 Modified miller compensation amplifier
CN104656733A (en) * 2015-02-12 2015-05-27 天津大学 LDO (low dropout regulator) capable of outputting ultra-low quiescent current in self-adaptation way
CN105005351A (en) * 2015-07-23 2015-10-28 中山大学 Cascode fully integrated low-dropout linear voltage regulator circuit
CN105159383A (en) * 2015-08-24 2015-12-16 电子科技大学 Low dropout regulator with high power supply rejection ratio
CN105955390A (en) * 2016-07-01 2016-09-21 唯捷创芯(天津)电子技术股份有限公司 Low-dropout linear regulator module, chip and communication terminal
CN106406411A (en) * 2016-12-08 2017-02-15 上海爱信诺航芯电子科技有限公司 Low dropout regulator circuit and power supply
WO2018129967A1 (en) * 2017-01-10 2018-07-19 南方科技大学 Low drop-out linear voltage regulator
CN106774578A (en) * 2017-01-10 2017-05-31 南方科技大学 Low pressure difference linear voltage regulator
CN106502302B (en) * 2017-01-10 2017-11-10 南方科技大学 A kind of low pressure difference linear voltage regulator
CN106774578B (en) * 2017-01-10 2018-02-27 南方科技大学 Low pressure difference linear voltage regulator
CN106502302A (en) * 2017-01-10 2017-03-15 南方科技大学 A kind of low pressure difference linear voltage regulator
CN107390772A (en) * 2017-08-31 2017-11-24 电子科技大学 High power supply voltage low-power consumption low pressure difference linear voltage regulator
CN107402594B (en) * 2017-08-31 2019-01-18 电子科技大学 Realize the low-power consumption low pressure difference linear voltage regulator of high power supply voltage transformation
CN107402594A (en) * 2017-08-31 2017-11-28 电子科技大学 Realize the low-power consumption low pressure difference linear voltage regulator of high power supply voltage transformation
CN110286709A (en) * 2018-03-19 2019-09-27 株式会社东芝 Constant voltage circuit
CN110286709B (en) * 2018-03-19 2021-05-28 株式会社东芝 Constant voltage circuit
CN108536206A (en) * 2018-03-22 2018-09-14 广州慧智微电子有限公司 A kind of voltage regulator and voltage adjusting method
CN108536206B (en) * 2018-03-22 2020-10-27 广州慧智微电子有限公司 Voltage regulator and voltage regulating method
CN109656300A (en) * 2019-02-27 2019-04-19 电子科技大学 A kind of Fast Load response LDO based on dual power rail power supply
CN110299843A (en) * 2019-06-14 2019-10-01 上海芯导电子科技有限公司 A kind of composite DC/DC circuit
CN110299843B (en) * 2019-06-14 2021-05-25 上海芯导电子科技有限公司 Composite DCDC circuit
CN110320963B (en) * 2019-08-05 2020-10-13 锐芯微电子股份有限公司 Low dropout linear voltage stabilizing circuit
CN110320963A (en) * 2019-08-05 2019-10-11 昆山锐芯微电子有限公司 Low-dropout linear voltage-regulating circuit
CN111290460A (en) * 2020-02-25 2020-06-16 电子科技大学 Low dropout regulator with high power supply rejection ratio and rapid transient response
CN112015224A (en) * 2020-10-22 2020-12-01 深圳市汇顶科技股份有限公司 Low dropout regulator and power supply circuit

Also Published As

Publication number Publication date
CN102707754B (en) 2014-08-13

Similar Documents

Publication Publication Date Title
CN104113212B (en) The apparatus and method of the current balance type of pressure regulator, current sensor and phase equilibrium
CN103376816B (en) Low-dropout voltage regulator
Kim et al. A capacitorless LDO regulator with fast feedback technique and low-quiescent current error amplifier
CN102915060B (en) Low pressure difference linear voltage regulator
TWI395083B (en) Low dropout regulator
US7502719B2 (en) Method and apparatus for overshoot and undershoot errors correction in analog low dropout regulators
EP2564284B1 (en) On-chip low voltage capacitor-less low dropout regulator with q-control
US8294442B2 (en) Low dropout regulator circuit without external capacitors rapidly responding to load change
US6188212B1 (en) Low dropout voltage regulator circuit including gate offset servo circuit powered by charge pump
Lin et al. An active-frequency compensation scheme for CMOS low-dropout regulators with transient-response improvement
US7633280B2 (en) Low drop voltage regulator with instant load regulation and method
US9274537B2 (en) Regulator circuit
Oh et al. A CMOS low-dropout regulator with current-mode feedback buffer amplifier
CN102096434B (en) High-slew-rate error amplifier-based high-accuracy and high-speed low dropout (LDO) regulator circuit
KR102000680B1 (en) Voltage regulator
CN100495281C (en) Low-voltage-difference voltage-stablizer
US8471539B2 (en) Low drop out voltage regulato
US7746047B2 (en) Low dropout voltage regulator with improved voltage controlled current source
US5982226A (en) Optimized frequency shaping circuit topologies for LDOs
US7218087B2 (en) Low-dropout voltage regulator
US9122292B2 (en) LDO/HDO architecture using supplementary current source to improve effective system bandwidth
US9293992B2 (en) Voltage regulator
KR20100074421A (en) Low-dropout voltage regulator, and operating method of the regulator
CN102385410B (en) Slew-rate enhancement circuit and LDO integrating same
US8547077B1 (en) Voltage regulator with adaptive miller compensation

Legal Events

Date Code Title Description
PB01 Publication
C06 Publication
SE01 Entry into force of request for substantive examination
C10 Entry into substantive examination
GR01 Patent grant
C14 Grant of patent or utility model
CP03 Change of name, title or address

Address after: Room 508-511, building a, Modern Plaza, No. 18, Weiye Road, Kunshan Development Zone, Suzhou, Jiangsu

Patentee after: Ruixin Microelectronics Co., Ltd

Address before: Room 508-511, block A, Modern Plaza, 18 Weiye Road, Kunshan, Jiangsu, Suzhou, 215300

Patentee before: BRIGATES MICROELECTRONICS (KUNSHAN) Co.,Ltd.

CP03 Change of name, title or address