CN102789257A - Low dropout regulator - Google Patents
Low dropout regulator Download PDFInfo
- Publication number
- CN102789257A CN102789257A CN2012103166512A CN201210316651A CN102789257A CN 102789257 A CN102789257 A CN 102789257A CN 2012103166512 A CN2012103166512 A CN 2012103166512A CN 201210316651 A CN201210316651 A CN 201210316651A CN 102789257 A CN102789257 A CN 102789257A
- Authority
- CN
- China
- Prior art keywords
- grid
- drain electrode
- pipe
- pmos
- nmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
The invention discloses a low dropout regulator, comprising a current substraction circuit which consists of MOS (metal oxide semiconductor) tubes M4 and M5 and has a load hopping from a light load to a heavy load, a current substraction circuit which consists of M6 and M7 and has a load hopping from a heavy load to a light load, as well as a fast response pathway which consists of M7, M8 and M14 and has a load hopping from a heavy load to a light load. According to the LDO (low dropout regulator) disclosed by the invention, the bias current of an error amplifier is increased only when the circuit is transiently switched, thereby the output transient response is improved, and the quiescent current of the circuit at a steady state is ensured to be very low; when the load hops from the heavy load to the light load, the fast response pathway is increased, the bandwidth of a transient loop is expanded, the output transient characteristic is improved, and the magnitude of output spike voltage is reduced; and furthermore, when the LDO is in a steady state, only an EA main loop is involved in work, thereby the quiescent current of the LDO is not increased.
Description
Technical field
The invention belongs to the power management techniques field, be specifically related to a kind of design with outer big condenser type low pressure difference linear voltage regulator of no sheet of quick load response.
Background technology
(Low-dropoutvoltage regulators LDO) relies on advantages such as cost is low, output noise is little, circuit structure is simple, chip occupying area is little as one type of important circuit in the power management chip and is widely used low pressure difference linear voltage regulator.And modern power management techniques develops towards the SOC direction, and also the performance to LDO has proposed new requirement: 1) lower power consumption, promptly littler quiescent current; 2) better transient response, promptly more excellent compensation way and topological structure; 3) be easy to integratedly, promptly require the outer big electric capacity of no sheet and the compensating circuit of complicacy too.
Common LDO circuit is generally by error amplifier, and voltage-reference is adjusted pipe and feedback circuit and constituted, and is specifically as shown in Figure 1.The output voltage V of general LDO circuit
OUTCan, load transient produce spike very greatly, V when changing
OUTRegain the stable certain hour that needs; And to obtain load transient response fast; Just need to increase quiescent current to improve the speed that discharges and recharges to the power tube grid, therefore common LDO circuit structure can't be taken into account low quiescent current and load transient response fast simultaneously.
In order to improve LDO output transient response, traditional method is to adopt adaptive bias circuit, i.e. error amplifier bias current and the proportional variation of LDO actual loading electric current, but this scheme is at the LDO full load, and the quiescent current of circuit is very big, and efficient is very low.
Summary of the invention
The objective of the invention is to have proposed a kind of low pressure difference linear voltage regulator in order to solve the problems referred to above that existing LDO exists.
Technical scheme of the present invention is: a kind of low pressure difference linear voltage regulator; Specifically comprise: the load of PMOS pipe M4 and NMOS pipe M5 composition is the current subtraction circuit during to heavily loaded saltus step by underloading; The quick response path that PMOS pipe M7, M8, M14, NMOS pipe M6 form; PMOS pipe M9, M10, M15, M16, common gate error amplifier and power P pipe Mp and building-out capacitor C1 that NMOS pipe M11, M12, M13, M17, M18 form;
Concrete annexation is following:
The grid of NMOS pipe M18 is as the first bias voltage input end of said linear voltage regulator; The grid of PMOS pipe M4 and the grid of M7 are connected as the second bias voltage input end of said linear voltage regulator; The source electrode of PMOS pipe M3, M4, M7, M8, M14 all connects external power source, the drain electrode of PMOS pipe M7, and the drain electrode of M8, grid, the grid of M14 links to each other, and the drain electrode of the drain electrode of PMOS pipe M14, NMOS pipe M13, the drain electrode of PMOS pipe M10 connect the grid of power tube PMOS Mp; The drain electrode of PMOS pipe M4, the drain electrode of NMOS pipe M5, drain electrode, the grid of NMOS pipe M12, the grid of NMOS pipe M13 links to each other, and NMOS manages M5, the source grounding current potential of M12, M13, M6, M11; The grid of NMOS pipe M5, the grid of M6, the grid of the grid M7 of M11, drain electrode link to each other; The M6 drain electrode of NMOS pipe links to each other with the drain electrode of PMOS pipe M7, M8; Drain electrode, the grid of the drain electrode of NMOS pipe M11 and PMOS pipe M9, the grid of M10 links to each other, and the source electrode of PMOS pipe M9, M10 connects external power source; The grid of NMOS pipe M17, drain electrode and the drain electrode of PMOS pipe M15 link to each other; The drain electrode of the source electrode of M15 and power tube PMOS Mp links to each other as the output terminal of said linear voltage regulator; The source electrode of power tube PMOS Mp connects external power source, and building-out capacitor C1 is connected between the grid and drain electrode of power tube PMOS Mp; The grid of PMOS pipe M15, the grid of PMOS pipe M16, drain electrode and the drain electrode of NMOS pipe M18 link to each other, the source ground current potential of NMOS pipe M18, the source electrode of PMOS pipe M16 is as the input end of said common gate error amplifier.
Further, described linear voltage regulator also comprises biasing circuit, and described biasing circuit specifically comprises: current source Ib, and NMOS manages M1, M2, PMOS manages M3, resistance R 1 and capacitor C 2, concrete annexation is:
The drain electrode of NMOS pipe M1, grid, the grid of NMOS pipe M2, the end of current source Ib link together; And as the first bias voltage output terminal of said biasing circuit; The other end of current source Ib is connected with external power source; The source grounding current potential of NMOS pipe M1, M2; The drain electrode of NMOS pipe M2 links to each other with drain electrode, the grid of PMOS pipe M3 and afterwards links to each other with first end of capacitor C 2 through resistance R 1, and second end of capacitor C 2 is connected to the output terminal of said linear voltage regulator, and first end of capacitor C 2 is as the second bias voltage output terminal of said biasing circuit.
Further, described linear voltage regulator also comprises voltage buffer, described voltage buffer specifically comprises: PMOS manages M22, and M23, M24, NMOS manages M19, M20, M21, resistance R 2, capacitor C 3, concrete annexation is:
The grid of NMOS pipe M20 and the drain electrode of M24 are connected with the input end of said common gate error amplifier as the output terminal of said voltage buffer, the grid of PMOS pipe M24, the drain electrode of M23, and the drain electrode of NMOS pipe M19 links to each other; The grid of M19 is used to import external reference voltage; The source electrode of NMOS pipe M19, the source electrode of M20, the drain electrode of M21 links to each other; The source ground current potential of NMOS pipe M21; The drain electrode of NMOS pipe M20 links to each other with grid, the drain electrode of PMOS pipe M22, and the source electrode of PMOS pipe M22, M23, M24 connects external power supply, resistance R 2; Be connected on after capacitor C 3 series connection between the drain electrode of grid and M24 of PMOS pipe M24, the grid of M21 is connected with the first bias voltage output terminal of biasing circuit as the first bias voltage input end of voltage buffer.
Beneficial effect of the present invention: LDO of the present invention only increases when the circuit transient state is switched through the bias current that makes error amplifier, has promptly improved LDO output transient response, can guarantee that again circuit quiescent current when stable state is very low, has following advantage:
1, when the load saltus step, utilization capacitive coupling technology and current subtraction technology, the error amplifier EA through employing PUSH PULL output stage strengthen LDO on draw and pull-down capability, improve the output transient response of LDO;
2, during to the underloading saltus step, increase response path fast by heavy duty in load, expand the transient state loop bandwidth of LDO, improve the output transient response of LDO, reduced the size of output spike voltage;
Therefore when 3, LDO is in stable state, have only EA major loop participation work, do not increase the quiescent current of LDO, can't take into account the low quiescent current and the problem of load transient response fast simultaneously thereby solve traditional LDO;
4, error amplifier adopts the common gate configuration of high bandwidth; Do not have at output terminal and use the miller frequency compensation method can realize the stability of loop under the situation of any plug-in capacitor; In conjunction with the low pressure applications characteristic of LDO of the present invention, it is integrated that it is easy to, and is used for the SOC supply module.
Description of drawings
Fig. 1 is existing common LDO structural representation.
Fig. 2 is a LDO electrical block diagram proposed by the invention.
Fig. 3 is the loop baud synoptic diagram when load is jumped heavy duty by underloading of LDO proposed by the invention.
Fig. 4 is the loop baud synoptic diagram when load is jumped underloading by heavy duty of LDO proposed by the invention.
Fig. 5 is the load transient response emulation synoptic diagram of LDO proposed by the invention.
Embodiment
Below in conjunction with accompanying drawing and concrete embodiment the present invention is done further elaboration.
Low pressure difference linear voltage regulator structural representation of the present invention is as shown in Figure 2; Specifically comprise: the load of PMOS pipe M4 and NMOS pipe M5 composition is the current subtraction circuit during to heavily loaded saltus step by underloading; The quick response path that PMOS pipe M7, M8, M14, NMOS pipe M6 form; PMOS pipe M9, M10, M15, M16, common gate error amplifier and power P pipe Mp and building-out capacitor C1 that NMOS pipe M11, M12, M13, M17, M18 form.
As a kind of preferred version, Fig. 2 has provided a kind of way of realization of biasing circuit, specifically comprises: current source Ib, and NMOS manages M1; M2, PMOS manages M3, resistance R 1 and capacitor C 2; Wherein, current source Ib, NMOS manages M1; M2, PMOS pipe M3 has formed quiescent biasing, and resistance R 1 has been formed dynamic bias with capacitor C 2.When the circuit stable state, because capacitor C 2 is equivalent to open circuit, do not work by the capacitance coupling circuit that R1 and C2 form, have only current source Ib, NMOS manages M1, M2, it is that LDO provides biasing that PMOS pipe M3 has formed quiescent biasing; When unstable state, because the variation of output voltage, capacitor C 2 forms paths, and the capacitance coupling circuit and the NMOS that are formed by R1 and C2 manage M1, and M2, PMOS manage M3 and formed dynamic bias one and be all LDO biasing is provided.
In addition, Fig. 2 has also provided a kind of way of realization of voltage buffer, specifically comprises: PMOS manages M22, M23, and M24, NMOS manages M19, M20, M21, resistance R 2, capacitor C 3.
The load that the core of low pressure difference linear voltage regulator of the present invention is made up of M4 and M5 is the current subtraction circuit during to heavily loaded saltus step by underloading; The load that M6 and M7 form is the current subtraction circuit during to the underloading saltus step by heavy duty, and the load of M7, M8 and M14 composition by heavy duty the quick response path during to the underloading saltus step.
When output is jumped underloading by heavy duty; The capacitance coupling circuit that LDO of the present invention at first forms through R1 and C2; The quick response path transient state that the current subtraction circuit that M6, M7 form and M7, M8 and M14 form significantly increases the grid pendulum rate of power tube, and then makes output reach stable ratings through accurate adjusting of EA major loop; When load was jumped heavy duty by underloading, through the capacitance coupling circuit that R1 and C2 form, the current subtraction circuit that M4 and M5 form increased grid pendulum rate through the EA loop, improves transient response.In addition owing to adopt the capacitive coupling technology, so the LDO that the present invention proposes does not increase quiescent current when improving transient response.
Make a concrete analysis of as follows:
1. circuit steady-state analysis: when circuit working during in stable state, capacitor C 2 equivalences in the capacitance coupling circuit are for opening circuit, and then the grid potential of M4 equates with the grid potential of M3, and the quiescent current of M4 is just by bias current I so
bConfirm with M4 pipe sizing ratio with M1 and M2, M3.When circuit is static, have only EA loop participation work in addition, respond loop fast and the operate as normal of LDO is not impacted, be i.e. I
M7=I
M6, I
M4=I
M5+ I
M12
2. circuit large-signal analysis:
(1) in load by underloading during to heavily loaded saltus step, output voltage V
OUTTowards phenomenon, the EA amplifier detects output voltage V under can producing
OUTVariation, feed back to the M5 pipe in the current subtraction circuit, can know electric current I by Fig. 2
M5Reduce; Secondly, capacitor C 2 coupling V
OUTChange in voltage make the grid voltage V of M4
HFDescend electric current I
M4Increase I during owing to stable state
M4=I
M5+ I
M12, so by formula I
M12=I
M4-I
M5Can know I
M12Electric current significantly increases, through M
12With M
13The current mirror relation, I
DISCHElectric current significantly increases, and the EA amplifier detects output voltage V in addition
OUTVariation also can feed back to the M11 pipe in the EA amplifier, can know electric current I by Fig. 2
M11Reduce, can know electric current I by mirror so
M10Reduce, the pendulum rate of the power tube grid when being formed the push-pull type output stage and improved transient state largely by M13 and M11 pipe has like this been improved the transient response of LDO.Can know I by the multiplying power relation of M6 and M17 current mirror in addition
M6Also reduce capacitor C 2 coupling V
OUTChange in voltage make the grid voltage V of M7
HFDescend electric current I
M7Increase.Because I during stable state
M7=I
M6, so by formula I
M8=I
M6-I
M7Can know that this moment, the M8 tube current was zero, responded path blockade fast.Therefore, under the situation of heavily loaded saltus step, significantly improved discharge capability, improved the output transient response of dashing under the LDO the power tube grid through employing capacitive coupling technology and current subtraction device circuit by underloading.
(2) in load by heavy duty during to the underloading saltus step; The capacitance coupling circuit of at first forming through R1 and C2; The quick response path transient state that the current subtraction circuit that M6, M7 form and M7, M8 and M14 form significantly increases the grid pendulum rate of power tube; Its concrete principle of work is following: in load by heavy duty during to the underloading saltus step, output voltage V
OUTCan produce and go up towards phenomenon, the EA amplifier detects output V
OUTVariation, feed back to M6 pipe and make the electric current I that flows through the M6 pipe
M6Increase, in addition capacitor C 2 coupling V
OUTChange in voltage make the grid voltage V of M7
HFRaise electric current I
M7Reduce I during owing to stable state
M7=I
M6, by formula I
M8=I
M6-I
M7Can know the M8 conducting, the high bandwidth current amplifier that forms through M14 and M8 so makes I
CHElectric current increases significantly; Secondly, accurately regulate to make output reach stable ratings through the EA major loop, its concrete principle of work is following: in load by heavy duty during to the underloading saltus step, output voltage V
OUTCan produce and go up towards phenomenon, the EA amplifier detects output V
OUTVariation, feed back to M5 pipe, make and flow through M
5The electric current of pipe increases, in addition capacitor C 2 coupling V
OUTChange in voltage make the grid voltage V of M4
HFRaise electric current I
M4Reduce, formula I is arranged
M12=I
M4-I
M5The electric current that can flow through the M12 pipe reduces, and can know the electric current I that flows through the M13 pipe by mirror
DISH, the EA amplifier detects output voltage V in addition
OUTVariation also can feed back to the M11 pipe in the EA amplifier, can know electric current I by Fig. 2
M11Increase, can know electric current I by mirror so
M10Increase the pendulum rate of the power tube grid when forming push-pull type output stage raising transient state by M13 and M11 pipe like this; Therefore load by heavy duty under the situation of underloading saltus step; At first adopt capacitive coupling technology, current subtraction device circuit significantly to improve charging ability to the power tube grid through quick response path; Improved the output transient response of dashing on the LDO; And then accurately regulate through the EA loop, further improve the transient response of LDO.
The bandwidth of LDO when increasing the load saltus step requires the cutoff frequency of the high pass circuit that resistance R 1 and capacitor C 2 form to be located near the unity gain bandwidth of LDO; In order to realize capacitive coupling effect preferably, the span of capacitor C 2 is generally 0.5pF～2pF in addition, and the large tracts of land size compared that this and power tube take does not take too big chip area.Can certainly use mos capacitance to reduce the shared area of C2.That need here a bit is exactly the C of M4
GSIf electric capacity is the coupling effect of affects capacitor C 2 too, so that the raceway groove of M4 should be got is little as far as possible.Resistance R 1 resistance is big more, and C2 will have better coupling effect when the circuit load transient state is switched, the span of its resistance generally between 0.5M～2M ohm, its specifically can with NWELL resistance or high resistance polysilicon realize.The precision of R1, C2 does not require in addition.
3. circuit small-signal analysis: when load was switched fast, the transient response of LDO output voltage mainly received the band-limited restriction of EA loop, and it is very big and release time is very long that this can cause exporting overshoot voltage.To know that in order analyzing circuit is a transient response how to improve LDO, to be divided into two kinds of situation here and to discuss, the one, when load was jumped heavy duty by underloading, the RC high pass circuit can the efficient extn loop bandwidth; The 2nd, when load was jumped underloading by heavy duty, secondary ring will work fast.
Situation one, load is jumped heavy duty by underloading:
Owing to adopt the RC high pass circuit to detect the variation of output voltage, and its cutoff frequency is set near the unity gain bandwidth of LDO, so this can equivalence increases the loop bandwidth of LDO.The baud synoptic diagram of loop is as shown in Figure 3, can see that the LDO loop is limited, and the cutoff frequency of RC high pass circuit is just near unity gain bandwidth, and after both combined, the LDO loop bandwidth had been expanded widely.
Situation two, load is jumped underloading by heavy duty:
Because the electric current that flows through transistor M7 reduces, make M8 by cut-off state to the saturation region transition, the quick secondary ring that the current amplifier of being made up of transistor M8 and M14 constitutes is started working.Secondary ring and EA major loop are worked simultaneously fast, form bicyclic system.LDO loop baud synoptic diagram is shown in accompanying drawing four, and the EA loop is a high-gain loop, thereby loop bandwidth is very little; Adopt the design of hanging down the live width high bandwidth and respond loop fast; Thereby loop gain is little but loop bandwidth is big, the two collaborative work, and the actual Bode diagram of loop is as shown in Figure 4.Can see; Because the output impedance of LDO diminishes during transient state, the output limit moves to high frequency region, and loop bandwidth increases; Therefore the LDO of the present invention's proposition jumps the characteristic that has combined the high-gain high bandwidth in the underloading process simultaneously in load by heavy duty, has improved the loop transient response.
LDO of the present invention in addition adopts the common gate error amplifier structure of high bandwidth, does not have at output terminal under the situation of any plug-in capacitor and uses the miller frequency compensation method can realize the stability of loop.
LDO load transient response characteristic Simulation result proposed by the invention is as shown in Figure 5.In 100ns, jump the 100mA full load when circuit load, have only 134mV towards spike under the output voltage by the 1mA underloading; When circuit load is jumped the 1mA underloading by 100mA is fully loaded in 100ns, has only 141mV towards spike on the output voltage.This shows that the LDO load transient characteristic that the present invention proposes is greatly improved really.
In sum; LDO proposed by the invention is under the situation that does not increase the LDO quiescent dissipation; Improved the transient response of LDO; Meanwhile do not have outer big electric capacity of sheet and low supply voltage it can be widely used among the SOC, therefore LDO proposed by the invention has well solved existing LDO and can't take into account the low quiescent current and the problem of load transient response fast simultaneously, has satisfied SOC and has used the requirement that the inside supplies power.
Those of ordinary skill in the art will appreciate that embodiment described here is in order to help reader understanding's principle of the present invention, should to be understood that protection scope of the present invention is not limited to such special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combinations that do not break away from essence of the present invention according to these teachings disclosed by the invention, and these distortion and combination are still in protection scope of the present invention.
Claims (5)
1. low pressure difference linear voltage regulator; Specifically comprise: the load of PMOS pipe M4 and NMOS pipe M5 composition is the current subtraction circuit during to heavily loaded saltus step by underloading; The quick response path that PMOS pipe M7, M8, M14, NMOS pipe M6 form; PMOS pipe M9, M10, M15, M16, common gate error amplifier and power P pipe Mp and building-out capacitor C1 that NMOS pipe M11, M12, M13, M17, M18 form;
Concrete annexation is following:
The grid of NMOS pipe M18 is as the first bias voltage input end of said linear voltage regulator; The grid of PMOS pipe M4 and the grid of M7 are connected as the second bias voltage input end of said linear voltage regulator; The source electrode of PMOS pipe M3, M4, M7, M8, M14 all connects external power source, the drain electrode of PMOS pipe M7, and the drain electrode of M8, grid, the grid of M14 links to each other, and the drain electrode of the drain electrode of PMOS pipe M14, NMOS pipe M13, the drain electrode of PMOS pipe M10 connect the grid of power tube PMOS Mp; The drain electrode of PMOS pipe M4, the drain electrode of NMOS pipe M5, drain electrode, the grid of NMOS pipe M12, the grid of NMOS pipe M13 links to each other, and NMOS manages M5, the source grounding current potential of M12, M13, M6, M11; The grid of NMOS pipe M5, the grid of M6, the grid of the grid M7 of M11, drain electrode link to each other; The M6 drain electrode of NMOS pipe links to each other with the drain electrode of PMOS pipe M7, M8; Drain electrode, the grid of the drain electrode of NMOS pipe M11 and PMOS pipe M9, the grid of M10 links to each other, and the source electrode of PMOS pipe M9, M10 connects external power source; The grid of NMOS pipe M17, drain electrode and the drain electrode of PMOS pipe M15 link to each other; The drain electrode of the source electrode of M15 and power tube PMOS Mp links to each other as the output terminal of said linear voltage regulator; The source electrode of power tube PMOS Mp connects external power source, and building-out capacitor C1 is connected between the grid and drain electrode of power tube PMOS Mp; The grid of PMOS pipe M15, the grid of PMOS pipe M16, drain electrode and the drain electrode of NMOS pipe M18 link to each other, the source ground current potential of NMOS pipe M18, the source electrode of PMOS pipe M16 is as the input end of said common gate error amplifier.
2. low pressure difference linear voltage regulator according to claim 1 is characterized in that described linear voltage regulator also comprises biasing circuit; Described biasing circuit specifically comprises: current source Ib, and NMOS manages M1, M2; PMOS manages M3, resistance R 1 and capacitor C 2, and concrete annexation is:
The drain electrode of NMOS pipe M1, grid, the grid of NMOS pipe M2, the end of current source Ib link together; And as the first bias voltage output terminal of said biasing circuit; The other end of current source Ib is connected with external power source; The source grounding current potential of NMOS pipe M1, M2; The drain electrode of the NMOS pipe M2 back that links to each other with drain electrode, the grid of PMOS pipe M3 links to each other with first end of capacitor C 2 through resistance R 1, and it is continuous that second end of capacitor C 2 is connected to output terminal, and first end of capacitor C 2 is as the second bias voltage output terminal of said biasing circuit.
3. low pressure difference linear voltage regulator according to claim 1 and 2 is characterized in that described linear voltage regulator also comprises voltage buffer, and described voltage buffer specifically comprises: PMOS manages M22; M23, M24, NMOS manages M19, M20; M21, resistance R 2, capacitor C 3, concrete annexation is:
The grid of NMOS pipe M20 and the drain electrode of M24 are connected with the input end of said common gate error amplifier as the output terminal of said voltage buffer, the grid of PMOS pipe M24, the drain electrode of M23, and the drain electrode of NMOS pipe M19 links to each other; The grid of M19 is used to import external reference voltage; The source electrode of NMOS pipe M19, the source electrode of M20, the drain electrode of M21 links to each other; The source ground current potential of NMOS pipe M21; The drain electrode of NMOS pipe M20 links to each other with grid, the drain electrode of PMOS pipe M22, and the source electrode of PMOS pipe M22, M23, M24 connects external power supply, resistance R 2; Be connected on after capacitor C 3 series connection between the drain electrode of grid and M24 of PMOS pipe M24, the grid of M21 is connected with the first bias voltage output terminal of biasing circuit as the first bias voltage input end of voltage buffer.
4. low pressure difference linear voltage regulator according to claim 2 is characterized in that, the span of capacitor C 2 is 0.5pF～2pF.
5. according to claim 2 or 4 described low pressure difference linear voltage regulators, it is characterized in that the span of resistance R 1 is at 0.5M～2M ohm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210316651.2A CN102789257B (en) | 2012-08-31 | 2012-08-31 | Low dropout regulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210316651.2A CN102789257B (en) | 2012-08-31 | 2012-08-31 | Low dropout regulator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102789257A true CN102789257A (en) | 2012-11-21 |
| CN102789257B CN102789257B (en) | 2014-04-02 |
Family
ID=47154674
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210316651.2A Expired - Fee Related CN102789257B (en) | 2012-08-31 | 2012-08-31 | Low dropout regulator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102789257B (en) |
Cited By (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104102260A (en) * | 2013-04-03 | 2014-10-15 | 国民技术股份有限公司 | Dual-power supply system |
| CN104122931A (en) * | 2014-07-25 | 2014-10-29 | 电子科技大学 | Low dropout linear regulator with large power supply rejection ratio |
| CN104808734A (en) * | 2015-02-17 | 2015-07-29 | 唯捷创芯(天津)电子技术有限公司 | Adaptive low-voltage difference linear voltage stabilizer with wide withstand voltage range and chip thereof |
| CN104820459A (en) * | 2015-03-18 | 2015-08-05 | 北京兆易创新科技股份有限公司 | LDO circuit |
| CN103792982B (en) * | 2013-11-21 | 2016-05-25 | 无锡芯响电子科技有限公司 | A kind of low pressure difference linear voltage regulator without external capacitor |
| CN105652946A (en) * | 2016-03-04 | 2016-06-08 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | Adaptive-bias low-load-regulation low dropout linear voltage stabilizer |
| CN105807837A (en) * | 2016-03-04 | 2016-07-27 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | Overshoot suppression circuit for low dropout regulator |
| CN106059503A (en) * | 2016-05-31 | 2016-10-26 | 上海华虹宏力半导体制造有限公司 | Voltage buffer amplifier |
| CN106354186A (en) * | 2015-07-21 | 2017-01-25 | 炬芯（珠海）科技有限公司 | Low-voltage-difference linear voltage stabilizer |
| CN106484024A (en) * | 2015-08-31 | 2017-03-08 | 意法半导体国际有限公司 | System and Method for Linear Voltage Regulator |
| CN107024958A (en) * | 2017-04-25 | 2017-08-08 | 电子科技大学 | A kind of linear voltage-stabilizing circuit responded with fast load transient |
| CN107479612A (en) * | 2017-10-16 | 2017-12-15 | 佛山科学技术学院 | A kind of quick response LDO circuit |
| CN107491131A (en) * | 2017-10-16 | 2017-12-19 | 佛山科学技术学院 | A kind of numerical model analysis controls more loop LDO circuits |
| CN107783588A (en) * | 2017-11-10 | 2018-03-09 | 佛山科学技术学院 | A kind of push-pull type quick response LDO circuit |
| CN108508951A (en) * | 2018-04-09 | 2018-09-07 | 广东工业大学 | The LDO regulator circuit of capacitance outside a kind of no piece |
| CN108683167A (en) * | 2018-07-03 | 2018-10-19 | 苏州锴威特半导体有限公司 | A kind of anti-surge circuit of PD equipment |
| CN108762363A (en) * | 2018-06-25 | 2018-11-06 | 电子科技大学 | A kind of LDO circuit of push-pull output stage |
| CN110389614A (en) * | 2019-07-17 | 2019-10-29 | 南开大学 | Efficient low-pressure difference voltage-stablizer |
| CN111474974A (en) * | 2020-04-30 | 2020-07-31 | 上海维安半导体有限公司 | Method for improving L DO transient response when sudden change from heavy load to light load or no load |
| CN113110693A (en) * | 2021-04-23 | 2021-07-13 | 电子科技大学 | Low dropout regulator suitable for high-voltage driving |
| CN113741609A (en) * | 2021-08-30 | 2021-12-03 | 西安电子科技大学 | LDO circuit with adjustable output voltage and quick transient response |
| CN114063695A (en) * | 2021-11-17 | 2022-02-18 | 广东工业大学 | Three-loop off-chip capacitor LDO (low dropout regulator) circuit based on FVF (variable frequency) |
| CN114167933A (en) * | 2021-12-06 | 2022-03-11 | 上海瓴瑞微电子有限公司 | Low-dropout linear regulator circuit with low power consumption and fast transient response |
| CN114546026A (en) * | 2022-03-02 | 2022-05-27 | 上海先楫半导体科技有限公司 | Linear voltage stabilization module and system on chip |
| CN114879792A (en) * | 2022-05-24 | 2022-08-09 | 中国人民解放军国防科技大学 | Double-loop low-dropout linear voltage regulator with flip voltage follower structure |
| CN115309221A (en) * | 2022-08-22 | 2022-11-08 | 西安理工大学 | Fast transient response enhancement circuit applied to LDO (low dropout regulator) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001075663A (en) * | 1999-09-03 | 2001-03-23 | Seiko Instruments Inc | Improvement of transient response characteristics of low-current-consumption linear regulator |
| US20040008077A1 (en) * | 2002-05-30 | 2004-01-15 | Stacy Ho | Voltage regulator with dynamically boosted bias current |
| US7723968B2 (en) * | 2007-03-06 | 2010-05-25 | Freescale Semiconductor, Inc. | Technique for improving efficiency of a linear voltage regulator |
| CN102331807A (en) * | 2011-09-30 | 2012-01-25 | 电子科技大学 | Low-dropout (LDO) linear regulator of integrated slew rate enhancing circuit |
| CN102385408A (en) * | 2011-09-21 | 2012-03-21 | 电子科技大学 | Low dropout linear voltage regulator |
-
2012
- 2012-08-31 CN CN201210316651.2A patent/CN102789257B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001075663A (en) * | 1999-09-03 | 2001-03-23 | Seiko Instruments Inc | Improvement of transient response characteristics of low-current-consumption linear regulator |
| US20040008077A1 (en) * | 2002-05-30 | 2004-01-15 | Stacy Ho | Voltage regulator with dynamically boosted bias current |
| US7723968B2 (en) * | 2007-03-06 | 2010-05-25 | Freescale Semiconductor, Inc. | Technique for improving efficiency of a linear voltage regulator |
| CN102385408A (en) * | 2011-09-21 | 2012-03-21 | 电子科技大学 | Low dropout linear voltage regulator |
| CN102331807A (en) * | 2011-09-30 | 2012-01-25 | 电子科技大学 | Low-dropout (LDO) linear regulator of integrated slew rate enhancing circuit |
Non-Patent Citations (1)
| Title |
|---|
| TSZ YIN MAN等: "A High Slew-Rate Push-Pull Output Amplifier for Low-Quiescent Current Low-Dropout Regulators With Transient-Response Improvement", 《IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II:EXPRESS BRIEFS》 * |
Cited By (45)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104102260B (en) * | 2013-04-03 | 2016-03-02 | 国民技术股份有限公司 | dual power supply system |
| CN104102260A (en) * | 2013-04-03 | 2014-10-15 | 国民技术股份有限公司 | Dual-power supply system |
| CN103792982B (en) * | 2013-11-21 | 2016-05-25 | 无锡芯响电子科技有限公司 | A kind of low pressure difference linear voltage regulator without external capacitor |
| CN104122931A (en) * | 2014-07-25 | 2014-10-29 | 电子科技大学 | Low dropout linear regulator with large power supply rejection ratio |
| CN104122931B (en) * | 2014-07-25 | 2015-10-21 | 电子科技大学 | A kind of low pressure difference linear voltage regulator with high PSRR characteristic |
| CN104808734A (en) * | 2015-02-17 | 2015-07-29 | 唯捷创芯(天津)电子技术有限公司 | Adaptive low-voltage difference linear voltage stabilizer with wide withstand voltage range and chip thereof |
| US10168727B2 (en) | 2015-02-17 | 2019-01-01 | Vanchip (Tianjin) Technology Co., Ltd. | Adaptive low-dropout regulator having wide voltage endurance range, chip and terminal |
| CN104820459A (en) * | 2015-03-18 | 2015-08-05 | 北京兆易创新科技股份有限公司 | LDO circuit |
| CN106354186A (en) * | 2015-07-21 | 2017-01-25 | 炬芯（珠海）科技有限公司 | Low-voltage-difference linear voltage stabilizer |
| CN106484024A (en) * | 2015-08-31 | 2017-03-08 | 意法半导体国际有限公司 | System and Method for Linear Voltage Regulator |
| US9927828B2 (en) | 2015-08-31 | 2018-03-27 | Stmicroelectronics International N.V. | System and method for a linear voltage regulator |
| CN106484024B (en) * | 2015-08-31 | 2019-03-12 | 意法半导体国际有限公司 | System and method for linear voltage regulator |
| CN105807837A (en) * | 2016-03-04 | 2016-07-27 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | Overshoot suppression circuit for low dropout regulator |
| CN105807837B (en) * | 2016-03-04 | 2017-09-19 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | A kind of suppression for low pressure difference linear voltage regulator overshoots circuit |
| CN105652946A (en) * | 2016-03-04 | 2016-06-08 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | Adaptive-bias low-load-regulation low dropout linear voltage stabilizer |
| CN106059503A (en) * | 2016-05-31 | 2016-10-26 | 上海华虹宏力半导体制造有限公司 | Voltage buffer amplifier |
| CN106059503B (en) * | 2016-05-31 | 2019-06-11 | 上海华虹宏力半导体制造有限公司 | Voltage buffer amplifier |
| CN107024958B (en) * | 2017-04-25 | 2018-04-13 | 电子科技大学 | A kind of linear voltage-stabilizing circuit with fast load transient response |
| CN107024958A (en) * | 2017-04-25 | 2017-08-08 | 电子科技大学 | A kind of linear voltage-stabilizing circuit responded with fast load transient |
| CN107491131B (en) * | 2017-10-16 | 2023-02-28 | 佛山科学技术学院 | Digital-analog hybrid control multi-loop LDO circuit |
| CN107491131A (en) * | 2017-10-16 | 2017-12-19 | 佛山科学技术学院 | A kind of numerical model analysis controls more loop LDO circuits |
| CN107479612A (en) * | 2017-10-16 | 2017-12-15 | 佛山科学技术学院 | A kind of quick response LDO circuit |
| CN107479612B (en) * | 2017-10-16 | 2023-02-28 | 佛山科学技术学院 | Quick response LDO circuit |
| CN107783588B (en) * | 2017-11-10 | 2023-11-28 | 佛山科学技术学院 | Push-pull type quick response LDO circuit |
| CN107783588A (en) * | 2017-11-10 | 2018-03-09 | 佛山科学技术学院 | A kind of push-pull type quick response LDO circuit |
| CN108508951B (en) * | 2018-04-09 | 2020-04-28 | 广东工业大学 | LDO voltage regulator circuit without off-chip capacitor |
| CN108508951A (en) * | 2018-04-09 | 2018-09-07 | 广东工业大学 | The LDO regulator circuit of capacitance outside a kind of no piece |
| CN108762363B (en) * | 2018-06-25 | 2020-02-18 | 电子科技大学 | LDO circuit of push-pull output stage |
| CN108762363A (en) * | 2018-06-25 | 2018-11-06 | 电子科技大学 | A kind of LDO circuit of push-pull output stage |
| CN108683167B (en) * | 2018-07-03 | 2024-04-09 | 苏州锴威特半导体股份有限公司 | Anti-surge circuit of PD equipment |
| CN108683167A (en) * | 2018-07-03 | 2018-10-19 | 苏州锴威特半导体有限公司 | A kind of anti-surge circuit of PD equipment |
| CN110389614A (en) * | 2019-07-17 | 2019-10-29 | 南开大学 | Efficient low-pressure difference voltage-stablizer |
| CN110389614B (en) * | 2019-07-17 | 2020-07-03 | 南开大学 | High-efficiency low dropout regulator |
| CN111474974A (en) * | 2020-04-30 | 2020-07-31 | 上海维安半导体有限公司 | Method for improving L DO transient response when sudden change from heavy load to light load or no load |
| CN113110693A (en) * | 2021-04-23 | 2021-07-13 | 电子科技大学 | Low dropout regulator suitable for high-voltage driving |
| CN113741609A (en) * | 2021-08-30 | 2021-12-03 | 西安电子科技大学 | LDO circuit with adjustable output voltage and quick transient response |
| CN113741609B (en) * | 2021-08-30 | 2022-09-16 | 西安电子科技大学 | LDO circuit with adjustable output voltage and quick transient response |
| CN114063695A (en) * | 2021-11-17 | 2022-02-18 | 广东工业大学 | Three-loop off-chip capacitor LDO (low dropout regulator) circuit based on FVF (variable frequency) |
| CN114063695B (en) * | 2021-11-17 | 2023-03-10 | 广东工业大学 | Three-loop LDO (low dropout regulator) circuit without off-chip capacitor based on FVF (variable frequency) |
| CN114167933A (en) * | 2021-12-06 | 2022-03-11 | 上海瓴瑞微电子有限公司 | Low-dropout linear regulator circuit with low power consumption and fast transient response |
| CN114546026A (en) * | 2022-03-02 | 2022-05-27 | 上海先楫半导体科技有限公司 | Linear voltage stabilization module and system on chip |
| CN114879792A (en) * | 2022-05-24 | 2022-08-09 | 中国人民解放军国防科技大学 | Double-loop low-dropout linear voltage regulator with flip voltage follower structure |
| CN114879792B (en) * | 2022-05-24 | 2024-04-19 | 中国人民解放军国防科技大学 | Double-loop low-dropout linear voltage regulator with turnover voltage follower structure |
| CN115309221A (en) * | 2022-08-22 | 2022-11-08 | 西安理工大学 | Fast transient response enhancement circuit applied to LDO (low dropout regulator) |
| CN115309221B (en) * | 2022-08-22 | 2024-03-01 | 西安理工大学 | Quick transient response enhancing circuit applied to LDO |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102789257B (en) | 2014-04-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102789257B (en) | Low dropout regulator | |
| CN102707757B (en) | Dynamic discharge circuit and LDO integrated with same | |
| CN102385410B (en) | Slew-rate enhancement circuit and LDO integrating same | |
| CN100432886C (en) | Double ring low differential voltage linear voltage stabilizer circuit | |
| CN103713682B (en) | Low pressure difference linear voltage regulator | |
| CN102609025B (en) | Dynamic current doubling circuit and linear voltage regulator integrated with the circuit | |
| CN102279612A (en) | Low dropout linear regulator | |
| CN202486643U (en) | High-bandwidth low-voltage difference linear voltage-stabilizing source, system and chip | |
| CN202033682U (en) | LDO (low dropout regulator) | |
| CN102830741A (en) | Dual-loop low dropout regulator | |
| CN104181972B (en) | A kind of low pressure difference linear voltage regulator with high PSRR characteristic | |
| CN103729003B (en) | Without the low pressure difference linearity source of stable pressure of the outer electric capacity of sheet | |
| CN103105883A (en) | Linear voltage regulator with load detection circuit and dynamic zero compensation circuit | |
| CN103513688B (en) | Low pressure difference linear voltage regulator | |
| CN102778911A (en) | Voltage buffer circuit and low dropout regulator (LDO) integrated with voltage buffer circuit | |
| CN111522389A (en) | Wide-input low-dropout linear voltage stabilizing circuit | |
| CN103472882B (en) | Low dropout regulator of integrated slew rate enhancement circuit | |
| CN104216455B (en) | For the low-power consumption reference voltage source circuit of 4G communication chip | |
| CN106155162A (en) | A kind of low pressure difference linear voltage regulator | |
| CN106168828A (en) | A kind of power supply circuits with overcurrent protection function | |
| CN105955387A (en) | Double-ring protection low drop out (LDO) linear voltage regulator | |
| CN105739585A (en) | Low-power-consumption LDO circuit for radio frequency circuit | |
| CN211878488U (en) | Wide-input low-dropout linear voltage stabilizing circuit | |
| CN105577140A (en) | Crystal oscillator drive circuit | |
| CN104881071A (en) | Low-power reference voltage source |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140402 Termination date: 20160831 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |