CN103472882B - Low dropout regulator of integrated slew rate enhancement circuit - Google Patents
Low dropout regulator of integrated slew rate enhancement circuit Download PDFInfo
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- CN103472882B CN103472882B CN201310460162.9A CN201310460162A CN103472882B CN 103472882 B CN103472882 B CN 103472882B CN 201310460162 A CN201310460162 A CN 201310460162A CN 103472882 B CN103472882 B CN 103472882B
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Abstract
The invention relates to the field of power management technology. The invention discloses a low dropout regulator of an integrated slew rate enhancement circuit. The technical scheme of the invention comprises a slew rate enhancement circuit, an operational amplifier, a compensating pipe, a first resistor, a second resistor, a third resistor, a fourth resistor and a first capacitor. According to the low dropout regulator of the integrated slew rate enhancement circuit, due to the adoption of the slew rate enhancement circuit, when output voltage rushes up or down, the slew rate enhancement circuit can output driving current which is not restricted by a bias current source and quickly adjusts the grid changes of the compensating pipe, so as to compensate the changes of the load current, greatly solve the problem that the slew rate and bandwidth of an error amplifier are restricted in a low power consumption mode, and reduce the peak of the output voltage. An on-chip integration technology is adopted, no high off-chip load capacitance is needed, and the system cost is reduced.
Description
Technical field
The present invention relates to power management techniques, particularly one can be applicable to the design of the OCL output capacitance-less type low pressure difference linear voltage regulator (Low Dropout Regulator, LDO) in SOC (System on Chip) chip.
Background technology
Along with the development of SOC technology, require that increasing functional module is integrated in inside same IC to improve its level of integrated system.Wherein, LDO is simple with its circuit and the advantage that area occupied is little becomes indispensable supply module important in SOC system.
In order to reducing tab external component number and number of pins, therefore to grow a lot space without the outer bulky capacitor LDO of sheet.As shown in Figure 1, in figure, resistance RA and resistance RB forms the sample circuit of output voltage VO UT to traditional LDO framework, and resistance ROUT is pull-up resistor, and electric capacity COUT is filter capacitor.Operational amplifier OTA is according to the size of reference voltage VREF and feedback voltage V FB, and outputting drive voltage controls unlatching and the shutoff of Correctional tube MP1, realizes the adjustment of output voltage VO UT.Due to error amplifier OTA Slew Rate and Bandwidth-Constrained under low-power consumption mode, there is larger defect without the outer bulky capacitor LDO of sheet compared with traditional LDO, be faced with the dual-pressure of underloading bad stability and transient response variation.
Summary of the invention
The object of the invention is to solve the existing transient response problem existed without the outer bulky capacitor low pressure difference linear voltage regulator of sheet, propose a kind of no-output bulky capacitor type LDO that can be applicable in SOC, take into account transient response, output voltage precision, little chip area and low-power consumption.
The present invention solve the technical problem, the technical scheme adopted is, the low pressure difference linear voltage regulator of integrated slew rate enhancing circuit, is characterized in that, comprises slew rate enhancing circuit, operational amplifier, Correctional tube, the first resistance, the second resistance, the 3rd resistance, the 4th resistance, the first electric capacity; Wherein, the reverse input end of operational amplifier connects the second reference voltage, and in-phase input end connects one end of the second resistance and one end of the 3rd resistance, and output terminal connects one end of the control pole of Correctional tube and the output terminal of slew rate enhancing circuit and the first electric capacity; The input end of Correctional tube connects supply voltage, the output terminal of Correctional tube and one end of the first resistance be connected with one end of the 4th resistance as described low pressure difference linear voltage regulator output terminal and be connected the first input end of slew rate enhancing circuit, the other end of the 4th resistance connects the other end of the first electric capacity; The other end of the first resistance is connected with the other end of the second resistance and is connected the second input end of slew rate enhancing circuit; 3rd input end of slew rate enhancing circuit connects the first reference voltage; The other end of the 3rd resistance connects earth potential.
Further, described slew rate enhancing circuit comprises, PMOS: M1, M4, M6, M7, M8, M14, M15, M16, M17 and NMOS tube: M2, M3, M5, M9, M10, M11, M12, M13, M18 and resistance R21 and electric capacity C21, wherein the grid of PMOS M1, M6 with M16 is all connected the first bias voltage Vb1, source electrode connects supply voltage, M4, M17 source electrode connects supply voltage, and M1 drain electrode connects grid and the drain electrode of M2 respectively, and the drain electrode of M16 is connected to the source electrode of M14 and M15; The grid of M14 is the 3rd input end of slew rate enhancing circuit, and drain electrode connects the grid of M11 and M12 and the drain electrode of M11 respectively; The grid of M15 is the second input end of slew rate enhancing circuit, and the drain electrode of M15 connects the drain electrode of M12 and M13 and the grid of M13 and M18 respectively; The drain electrode of M18 is connected to the grid of M17, M4 and the drain electrode of M17; The grid of M7, M8 is all connected to the drain electrode of M7, and source electrode all connects supply voltage, and the drain electrode of M7 is connected to the drain electrode of M5 and M6, and the drain electrode of M8 connects the output terminal of drain electrode as slew rate enhancing circuit of M10; The source electrode of NMOS tube M2, M3, M5, M11, M12, M13, M18 all connects ground, the drain electrode of M2 connects M1 drain electrode and the grid of M2 and one end of R21, the other end of resistance R21 connects the grid of NMOS tube M3 and the grid of NMOS tube M5, the drain electrode of M3, M5 connects the drain electrode of M4, M6 respectively, and the grid of M2 connects the drain electrode of M2 and M1; The source grounding of NMOS tube M9, M10, the drain electrode of M9 is connected with the grid of M9 and M10 and is connected to the drain electrode of M3 and M4; One end of electric capacity C21 connects the grid of M3, and the other end is as the first input end of slew rate enhancing circuit.
Preferably, described Correctional tube is PMOS, and described Correctional tube controls the grid of very PMOS, and described Correctional tube input end is the source electrode of PMOS, and described Correctional tube output terminal is the drain electrode of PMOS.
The invention has the beneficial effects as follows, owing to adopting slew rate enhancing circuit proposed by the invention, when output voltage generation upper punch or undershoot, slew rate enhancing circuit can both export the drive current not being limited to bias current source size, the gate variation of rapid adjustment Correctional tube, with the change of compensating load electric current, overcome the problem of error amplifier Slew Rate and Bandwidth-Constrained under low-power consumption mode greatly, reduce output voltage spike.Meanwhile, the present invention adopts integrated technology on sheet, no longer needs the outer load capacitance of large sheet, reduces system cost.
Accompanying drawing explanation
The topology diagram of the existing LDO circuit of Fig. 1;
Fig. 2 low differential voltage linear voltage stabilizer circuit topology diagram of the present invention;
The circuit diagram of Fig. 3 slew rate enhancing circuit of the present invention;
Frequency response Bode diagram when Fig. 4 low pressure difference linear voltage regulator underloading of the present invention is jumped heavily loaded;
Frequency response Bode diagram during Fig. 5 low pressure difference linear voltage regulator of the present invention heavily loaded jumping underloading;
Transient result under Fig. 6 low pressure difference linear voltage regulator different loads of the present invention condition.
Embodiment
Below in conjunction with the drawings and the specific embodiments, describe technical scheme of the present invention in detail.
Low pressure difference linear voltage regulator of the present invention as shown in Figure 2, comprising: slew rate enhancing circuit SRE, operational amplifier OTA, Correctional tube M0, the first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, the first electric capacity C1.Wherein, the reverse input end of operational amplifier connects the second reference voltage V REF2, and output terminal connects the grid of Correctional tube M0 and the output terminal of slew rate enhancing circuit.The source electrode of Correctional tube M0 connects supply voltage VDD, and the drain electrode of Correctional tube M0 is as the output terminal VOUT of low pressure difference linear voltage regulator.The first input end in1 of slew rate enhancing circuit connects the output terminal VOUT of low pressure difference linear voltage regulator, second input end in2 of slew rate enhancing circuit is connected to the common port VFB1 of the first resistance R1 and the second resistance R2, and the 3rd input end in3 of slew rate enhancing circuit connects the first reference voltage V REF1.The other end of the first resistance R1 connects the output terminal VOUT of low pressure difference linear voltage regulator, the in-phase input end of the other end concatenation operation amplifier of the second resistance R2.The VFB of input end in the same way of second resistance R2 one end concatenation operation amplifier and one end of the 3rd resistance R3, the other end of the 3rd resistance R3 connects ground.The output terminal of one end concatenation operation amplifier of the first electric capacity C1, the other end connects one end of the 4th resistance R4, and the other end of the 4th resistance R4 is connected to the output terminal VOUT of low pressure difference linear voltage regulator.In Fig. 2, resistance RL is pull-up resistor.
Slew rate enhancing circuit of the present invention as shown in Figure 3, comprises, PMOS: M1, M4, M6, M7, M8, M14, M15, M16, M17 and NMOS tube: M2, M3, M5, M9, M10, M11, M12, M13, M18 and resistance R21 and electric capacity C21.Wherein the grid of PMOS M1, M6 with M16 is all connected bias voltage Vb1, and source electrode connects supply voltage VDD, and M4, M17 source electrode connects supply voltage.M1, M6 drain electrode connects the drain electrode of M2, M5 respectively, and the drain electrode of M16 is connected to the source electrode of M14 and M15.The grid of PMOS M14 connects the 3rd input end in3 (the first reference voltage VREF1) of slew rate enhancing circuit, and drain electrode connects the grid of M11 and M12 and the drain electrode of M11 respectively.The grid of PMOS M15 connects the second input end in2 (VFB1 end) of slew rate enhancing circuit, and drain electrode connects the drain electrode of M12 and M13 and the grid of M13 and M18 respectively.The drain electrode of PMOS M18 is connected to the grid of PMOS M17 and PMOS M4 and the drain electrode of M17.The grid of PMOS M7, M8 is all connected to the drain electrode of M7, and source electrode all connects supply voltage VDD, and the drain electrode of M7 is connected to the drain electrode of M5 and M6, and the drain electrode of M8 connects the output terminal VG of drain electrode as slew rate enhancing circuit of M10.The source electrode of NMOS tube M2, M3, M5, M11, M12, M13, M18 all connects ground, the drain electrode of M2 connects M1 drain electrode and the grid of M2 and one end of R21, the other end of resistance R21 connects the grid of NMOS tube M3 and the grid of NMOS tube M5, the drain electrode of M3, M5 connects the drain electrode of M4, M6 respectively, and the grid of M2 connects the drain electrode of M2 and M1.The source grounding of NMOS tube M9, M10, the drain electrode of M9 is connected with the grid of M9 and M10 and is connected to the drain electrode of M3 and M4.One end of electric capacity C1 connects the grid of NMOS tube M3, and the other end is as the input end VFB of slew rate enhancing circuit.
Here, M11, M12, M13, M14, M15 and M16 form trsanscondutance amplifier, and M3, M4 form the first current subtractor, and M5, M6 form the second current subtractor, and M7, M8 form upper punch current mirror module, and M9, M10 form undershoot current mirror module.
The effect of slew rate enhancing circuit is when load current changes, and can change the grid voltage of Correctional tube fast, thus within the extremely short time, adjusts output voltage stabilization to determined value.For ease of analyzing, suppose that the drain current of M1 is I, M11, the breadth length ratio ratio of M12 and M13 is (m+1): m:1.Under stable case, in trsanscondutance amplifier, the electric current of the electric current of M16 to be the electric current of 2I, M11 be I, M12 is
the electric current of M13 is
during design, in the first current subtractor, the image current of M3 is greater than the electric current of M4, then now M3 pipe work is in linear zone, and this current subtractor exports as low level, so transistor M9, M10 all do not work; In like manner, in the second current subtractor, M6 is operated in linear zone, and transistor M7, M8 also do not work.So slew rate enhancing circuit does not have an impact to LDO quiescent operation state and loop stability at steady state.
When output load current diminishes suddenly, output voltage has larger upwards pulse, the grid being coupled to transistor M3, M5 is started during the cutoff frequency of the Hi-pass filter that this pulse voltage is formed higher than electric capacity C21 and resistance R21, thus making the drain electrode of M3, M5 obtain very large electric current, this pulse voltage reduces the dynamic current of M4 by trsanscondutance amplifier effect simultaneously; For the current subtractor of M3, M4 composition, M3 will continue to operate in linear zone, exporting is still low level, then M9, M10 still do not work, and for the current subtractor that M5, M6 form, due to the unexpected increase of the drain current of M5, M7, M8 is made to have electric current to export, for Correctional tube M0 gate charges, thus the grid voltage of M0 increases rapidly, reduces the size of Correctional tube output current.When output load current becomes large suddenly, output voltage has a very high downward pulse, and this pulse voltage is coupled to the grid of transistor M3, M5 by electric capacity C21, thus the drain current of M3, M5 is diminished.For the current subtractor of M5, M6 composition, M6 will continue to operate in linear zone, and exporting is still high level, then M7, M8 then can not work; For the current subtractor of M3, M4 composition, this pulse voltage makes the output current of M13 rise rapidly by trsanscondutance amplifier effect, then M4 ER effect is very large; For the current subtractor of M3, M4 composition, due to the unexpected increase of M4 drain current, the unexpected reduction of M3 electric current, make M9 and M10 generation current rapidly, for the gate discharge of Correctional tube M0, thus drag down rapidly M0 grid voltage, finally make the output voltage of LDO be adjusted to determined value rapidly.
Can see in above-mentioned slew rate enhancing circuit, when upper punch occurs, by the coupling of R21C21D, M5 is produced gate charges that large electric current is Correctional tube, and this electric current increases with upper punch voltage and increases, and therefore slew rate enhancing circuit gate charging current is not limited; When undershoot occurs, VFB1 voltage can reduce, and now the electric current of M13 can increase rapidly, due to the existence of M12, M13 electric current is maximum can become original m+1 doubly, thus greatly increases the electric current of M4, and therefore this slew rate enhancing circuit undershoot discharge current is also substantially unrestricted.Therefore this slew rate enhancing circuit optimizes upper punch and undershoot effect greatly.In addition, in order to the variable quantity making trsanscondutance amplifier input end farthest extract output voltage, therefore when choosing reference voltage, do not select the reference voltage identical with EA, but select the maximum voltage of the common-mode input range ensureing trsanscondutance amplifier.
Be directed to slew rate enhancing circuit, when output voltage generation saltus step, RC Hi-pass filter only has effect when high frequency; And trsanscondutance amplifier all has effect when low frequency and high frequency, and when R21C21 Hi-pass filter or trsanscondutance amplifier have effect, the mutual conductance of LDO loop increases, and the analysis therefore for circuit stability is absolutely necessary.For the LDO without the outer electric capacity of sheet, its dominant pole position is at Correctional tube grid, and secondary pole location is positioned at LDO output terminal, and dominant pole and time limit are respectively
Wherein ROUTOTA is OTA output terminal resistance; Cpar is Correctional tube parasitic gate electric capacity; C
m=g
m0r
aLLc
1for miller capacitance is at the electric capacity of Correctional tube grid equivalence; R
aLL=R
l// (R
1+ R
2+ R
3) //r
omp0for LDO output equivalent resistance; Cl is for exporting stray capacitance, and its value is less than 100pF.When slew rate enhancing circuit is started working, ROUTOTA can be made to diminish, now dynamic dominant pole position can increase, and the trsanscondutance amplifier in slew rate enhancing circuit all works when load jump.When underloading jumps heavy duty, frequency response Bode diagram as shown in Figure 4, wherein the dotted line place of upwarping for Hi-pass filter work time, because RL is very little, secondary pole location is higher, when slew rate enhancing circuit works, stability is no problem, and RC Hi-pass filter and trsanscondutance amplifier therefore now can be made all to work; But when underloading is jumped in heavy duty, frequency response Bode diagram as shown in Figure 5, wherein the dotted line place of upwarping for Hi-pass filter work time, RL is comparatively large, and secondary pole location is lower, if slew rate enhancing circuit is started working when low frequency, loop can be made unstable, because upper punch electric current increases with the increase of output voltage amplitude of variation, there is no the restriction of Slew Rate, so trsanscondutance amplifier does not need to participate in regulating, ensure better loop stability.Therefore the grid of M6 pipe is not connected to the grid of M17, the stability of system during heavily loaded saltus step underloading can be ensured like this.In addition, when load jump, in order to ensure the stable and fast response speed of system, during saltus step, time pole location should be arranged on about 2.2 times of bandwidth GBW.
Slew rate enhancing circuit in the present invention also can be applicable in other LDO circuit design, the adjustment electric current exported by slew rate enhancing circuit, Correctional tube grid voltage change in traditional LDO circuit can be reduced affect slowly, substantially increase the Slew Rate of LDO, and effectively reduce output voltage spike, utilize this design can obtain the LDO of a high Slew Rate, load current is saltus step between 100uA to 100mA, rise and fall are along when being 0.5u, its input waveform as shown in Figure 6, upper punch 180mV, undershoot 120mV.
Because this invention is integrated LDO on sheet, adopt compensation technique in sheet, therefore no longer need the outer electric capacity of large sheet.
Claims (2)
1. the low pressure difference linear voltage regulator of integrated slew rate enhancing circuit, is characterized in that, comprises slew rate enhancing circuit, operational amplifier, Correctional tube, the first resistance, the second resistance, the 3rd resistance, the 4th resistance, the first electric capacity; Wherein, the reverse input end of operational amplifier connects the second reference voltage, and in-phase input end connects one end of the second resistance and one end of the 3rd resistance, and output terminal connects one end of the control pole of Correctional tube and the output terminal of slew rate enhancing circuit and the first electric capacity; The input end of Correctional tube connects supply voltage, the output terminal of Correctional tube and one end of the first resistance be connected with one end of the 4th resistance as described low pressure difference linear voltage regulator output terminal and be connected the first input end of slew rate enhancing circuit, the other end of the 4th resistance connects the other end of the first electric capacity; The other end of the first resistance is connected with the other end of the second resistance and is connected the second input end of slew rate enhancing circuit; 3rd input end of slew rate enhancing circuit connects the first reference voltage; The other end of the 3rd resistance connects earth potential;
Described slew rate enhancing circuit comprises, PMOS: M1, M4, M6, M7, M8, M14, M15, M16, M17 and NMOS tube: M2, M3, M5, M9, M10, M11, M12, M13, M18 and resistance R21 and electric capacity C21, wherein the grid of PMOS M1, M6 with M16 is all connected the first bias voltage Vb1, source electrode connects supply voltage, M4, M17 source electrode connects supply voltage, M1 drain electrode connects grid and the drain electrode of M2 respectively, and the drain electrode of M16 is connected to the source electrode of M14 and M15; The grid of M14 is the 3rd input end of slew rate enhancing circuit, and drain electrode connects the grid of M11 and M12 and the drain electrode of M11 respectively; The grid of M15 is the second input end of slew rate enhancing circuit, and the drain electrode of M15 connects the drain electrode of M12 and M13 and the grid of M13 and M18 respectively; The drain electrode of M18 is connected to the grid of M17, M4 and the drain electrode of M17; The grid of M7, M8 is all connected to the drain electrode of M7, and source electrode all connects supply voltage, and the drain electrode of M7 is connected to the drain electrode of M5 and M6, and the drain electrode of M8 connects the output terminal of drain electrode as slew rate enhancing circuit of M10; The source electrode of NMOS tube M2, M3, M5, M11, M12, M13, M18 all connects ground, the drain electrode of M2 connects M1 drain electrode and the grid of M2 and one end of R21, the other end of resistance R21 connects the grid of NMOS tube M3 and the grid of NMOS tube M5, the drain electrode of M3, M5 connects the drain electrode of M4, M6 respectively, and the grid of M2 connects the drain electrode of M2 and M1; The source grounding of NMOS tube M9, M10, the drain electrode of M9 is connected with the grid of M9 and M10 and is connected to the drain electrode of M3 and M4; One end of electric capacity C21 connects the grid of M3, and the other end is as the first input end of slew rate enhancing circuit.
2. the low pressure difference linear voltage regulator of integrated slew rate enhancing circuit according to claim 1, it is characterized in that, described Correctional tube is PMOS, described Correctional tube controls the grid of very PMOS, described Correctional tube input end is the source electrode of PMOS, and described Correctional tube output terminal is the drain electrode of PMOS.
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Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104076854B (en) * | 2014-06-27 | 2016-02-03 | 电子科技大学 | A kind of without electric capacity low pressure difference linear voltage regulator |
| CN104699162B (en) * | 2015-03-27 | 2016-04-20 | 西安紫光国芯半导体有限公司 | A kind of low pressure difference linear voltage regulator of quick response |
| CN107240940B (en) * | 2016-03-29 | 2020-06-30 | 快捷半导体(苏州)有限公司 | USB connector discharging method and circuit |
| US10444778B2 (en) * | 2016-08-09 | 2019-10-15 | Nxp Usa, Inc. | Voltage regulator |
| CN106301264B (en) * | 2016-08-12 | 2019-04-16 | 中国科学院上海高等研究院 | A kind of enhanced operational amplifier of Slew Rate |
| CN106774575B (en) * | 2016-12-29 | 2019-05-31 | 北京兆易创新科技股份有限公司 | A kind of low pressure difference linear voltage regulator |
| CN106873697B (en) * | 2017-03-30 | 2018-05-29 | 西安邮电大学 | A kind of fast response circuit and method for low pressure difference linear voltage regulator |
| CN109164861A (en) * | 2018-10-31 | 2019-01-08 | 上海海栎创微电子有限公司 | A kind of low pressure difference linear voltage regulator of fast transient response |
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| US5223753A (en) * | 1991-07-26 | 1993-06-29 | Samsung Electronics Co., Ltd. | Slew rate speed-up circuit |
| US5939870A (en) * | 1998-09-17 | 1999-08-17 | Intel Corporation | Voltage regulator |
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| CN102279612A (en) * | 2011-05-11 | 2011-12-14 | 电子科技大学 | Low dropout linear regulator |
| CN102339584A (en) * | 2010-07-19 | 2012-02-01 | 美格纳半导体有限公司 | Slew rate boost circuit, output buffer having the same, and method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7218083B2 (en) * | 2005-02-25 | 2007-05-15 | O2Mincro, Inc. | Low drop-out voltage regulator with enhanced frequency compensation |
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| US5223753A (en) * | 1991-07-26 | 1993-06-29 | Samsung Electronics Co., Ltd. | Slew rate speed-up circuit |
| US5939870A (en) * | 1998-09-17 | 1999-08-17 | Intel Corporation | Voltage regulator |
| CN101421683A (en) * | 2006-04-18 | 2009-04-29 | 爱特梅尔公司 | Low-dropout voltage regulator with a voltage slew rate efficient transient response boost circuit |
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| CN102279612A (en) * | 2011-05-11 | 2011-12-14 | 电子科技大学 | Low dropout linear regulator |
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