CN102707754B - Low dropout regulator - Google Patents
Low dropout regulator Download PDFInfo
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- CN102707754B CN102707754B CN201210173613.6A CN201210173613A CN102707754B CN 102707754 B CN102707754 B CN 102707754B CN 201210173613 A CN201210173613 A CN 201210173613A CN 102707754 B CN102707754 B CN 102707754B
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Abstract
The invention discloses a low dropout regulator, which comprises an error amplifier, a buffer circuit, a P-channel metal oxide semiconductor (PMOS) regulation transistor, an N-channel metal oxide semiconductor (NMOS) push-pull tube, a voltage division feedback circuit, a compensation circuit and an output circuit, wherein the gate of the PMOS regulation transistor is connected with the output end of the buffer circuit, the source of the PMOS regulation transistor is connected with power voltage, and the drain of the PMOS regulation transistor is used as the output end of the low dropout regulator; the gate of the NMOS push-pull tube is connected with the output end of the error amplifier, the drain of the NMOS push-pull tube is connected with the drain of the PMOS regulation transistor, and the source of the NMOS push-pull tube is grounded; and the error amplifier, the compensation circuit, the buffer circuit, the PMOS regulation transistor, the voltage division feedback circuit and an output circuit form a main control loop, and the error amplifier, the compensation circuit, the NMOS push-pull tube, the voltage division feedback circuit and the output circuit form an auxiliary control loop. According to the low dropout regulator, the transient response of the regulator can be quickened, and the accuracy of output voltage can be improved.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly a kind of low-dropout linear voltage-regulating circuit.
Background technology
The linear mu balanced circuit of low voltage difference (Low Dropout Regulator, LDO) is step-down type dc linear voltage regulator, and along with the development of SOC technology, it is ubiquitous in sector applications such as computing machine, communication, instrument and meter, consumer electronics, monitoring camera-shootings.Although compare with DC-DC switching voltage converter, the efficiency of LDO is lower, but it has the advantages such as peripheral cell is few, ripple is little, noise is low, chip area is little, circuit structure is simple, so LDO occupies very large proportion in power management class chip always.
Raising along with integrated level, increasing LDO is as SOC(System on Chip, SOC (system on a chip)) submodule of chip is given certain crucial module for power supply and is integrated in this SOC chip, and in powerful SOC chip, integrated a plurality of LDO modules give different module for power supply very general.Frequency of operation along with SOC system improves constantly simultaneously, and it is also more and more serious that digital circuit wherein brings power supply to disturb, and this just needs LDO to have the performance requirements such as High-speed transient response speed, high output voltage control accuracy, high PSRR, low noise.
Traditional LDO voltage regulator circuit block diagram as shown in Figure 1.With reference to figure 1, described LDO voltage regulator circuit is the monocycle degeneration factor consisting of error amplifier OP, middle buffer level, PMOS adjustment transistor MP, dividing potential drop feedback network, output circuit, miller-compensated circuit.
Particularly, described dividing potential drop feedback network comprises the first resistance R _ f 1, the second resistance R _ f 2.Described the first resistance R _ f 1 and the second resistance R _ f 2 form partial pressure unit, branch pressure voltage V
fBbe fed back to the normal phase input end of error amplifier OP.The negative-phase input of described error amplifier OP receives reference voltage vref.
Described output circuit is comprised of equivalent series resistance ESR and output capacitance C2.The output voltage ripple that output circuit causes in the time of not only can reducing due to load changing, and can also be provided high frequency zero point for the feedback loop of system.
Described miller-compensated circuit comprises miller-compensated resistance R c and miller-compensated capacitor C c, for the limit of the limit of error amplifier OP output terminal and PMOS adjustment transistor MP drain electrode is compensated, feedback control loop can be stablized under various loading conditions.
Generally in order to guarantee that output has enough driving forces, the size that PMOS adjusts transistor MP is conventionally all larger, and the large grid stray capacitance (conventionally at tens pico farads) that large-sized PMOS adjustment transistor MP brings can significantly slow down the discharge and recharge speed of middle buffer level to this stray capacitance, and then seriously reduce system's transient response speed.
In addition, in order to guarantee the precision of output voltage V o and high low frequency PSRR(Power Supply Rejection Ratio), require error amplifier OP to there is high-gain, and high-gain causes the output node impedance of error amplifier OP very large, seriously reduce the bandwidth of system and then reduced system's transient response speed on the one hand, also strengthened on the other hand the difficulty of system balance.
So traditional LDO voltage feedback loop is a slow feedback control loop that comprises multipole point, when load current IL has large sudden change, output voltage V o not only has charge less voltage (undershoot) and the overcharged voltage (overshoot) of dozens or even hundreds of millivolt, and need a long transient process just can return to steady-state value, so just cause its output accuracy not high, cannot be for more current high-speed high-performance energy SOC(are as pel array in monitoring chip) clean direct supply is reliably provided.
Summary of the invention
The problem that the present invention solves is to provide a kind of low-dropout linear voltage-regulating circuit, effectively to improve the precision of transient response speed and the output voltage of circuit.
For addressing the above problem, the invention provides a kind of low-dropout linear voltage-regulating circuit, comprising: error amplifier, compensating circuit, buffer circuit, PMOS adjust transistor, NMOS recommends pipe, dividing potential drop feedback circuit and output circuit;
Described error amplifier, for branch pressure voltage and the reference voltage of described dividing potential drop feedback circuit output are compared, and exports comparative result to described buffer circuit;
Described buffer circuit, for carrying out impedance matching, to isolate output impedance node and the PMOS of error amplifier, adjust transistorized grid stray capacitance node, and provide after driving at the comparative result for receiving, export described comparative result to PMOS and adjust transistorized grid;
Described PMOS adjusts transistorized source electrode and connects supply voltage, and drain electrode is as the output terminal of low-dropout linear voltage-regulating circuit;
Described dividing potential drop feedback circuit, carries out dividing potential drop for described PMOS being adjusted to the voltage of transistor drain, and branch pressure voltage is fed back to error amplifier;
The grid that described NMOS recommends pipe connects the output terminal of described error amplifier, and drain electrode connects described PMOS and adjusts transistorized drain electrode, source ground;
Described output circuit connects described PMOS and adjusts transistorized drain electrode, for reducing output voltage ripple;
One end of described compensating circuit connects supply voltage, and the other end connects the output terminal of described error amplifier, for described low-dropout linear voltage-regulating circuit is compensated so that it is stable.
Alternatively, the ratio that described PMOS adjusts between the breadth length ratio that transistorized breadth length ratio and described NMOS recommend pipe is more than or equal to 1000.
Alternatively, described compensating circuit comprises: compensating resistance and building-out capacitor; One end of described building-out capacitor connects supply voltage, and the other end connects one end of described compensating resistance; The other end of described compensating resistance connects the output terminal of error amplifier.
Alternatively, described error amplifier comprises: tail current source and input difference are to, PMOS common-source common-gate current mirror and NMOS constant-current source bias and folded tube;
Described tail current source and input difference are to comprising a PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe and the 4th PMOS pipe; Described PMOS common-source common-gate current mirror comprises the 5th PMOS pipe, the 6th PMOS pipe, the 7th PMOS pipe and the 8th PMOS pipe; Described NMOS constant-current source bias and folded tube comprise the 9th NMOS pipe, the tenth NMOS pipe, the 11 NMOS pipe and the 12 NMOS pipe;
The grid of the one PMOS pipe connects the first bias voltage, and source electrode connects supply voltage, and drain electrode connects the source electrode of the 2nd PMOS pipe;
The grid of the 2nd PMOS pipe connects the second bias voltage, and drain electrode connects the source electrode of the 3rd PMOS pipe and the 4th PMOS pipe;
The branch pressure voltage of the connection dividing potential drop feedback circuit output of the 3rd gate pmos utmost point, drain electrode connects the drain electrode of the 11 NMOS pipe;
The grid of the 4th PMOS pipe connects reference voltage; Drain electrode connects the drain electrode of the 12 NMOS pipe;
The 5th PMOS manages the drain electrode that is all connected the 7th PMOS pipe with the grid of the 6th PMOS pipe, and the 5th PMOS pipe is connected supply voltage with the source electrode of the 6th PMOS pipe, and the drain electrode of the 5th PMOS pipe connects the source electrode of the 7th PMOS pipe; The drain electrode of the 6th PMOS pipe connects the source electrode of the 8th PMOS pipe;
The 7th PMOS pipe is all connected the second bias voltage with the grid of the 8th PMOS pipe, and the drain electrode of the 7th PMOS pipe connects the drain electrode of the 9th NMOS pipe;
The drain electrode of the 8th PMOS pipe connects the drain electrode of the tenth NMOS pipe, and as the output terminal of described error amplifier;
The 9th NMOS pipe is all connected the 3rd bias voltage with the grid of the tenth NMOS pipe, and the source electrode of the 9th NMOS pipe connects the drain electrode of the 11 NMOS pipe, and the source electrode of the tenth NMOS pipe connects the drain electrode of the 12 NMOS pipe;
The 11 NMOS pipe is all connected the 4th bias voltage with the grid of the 12 NMOS pipe, source grounding.
Alternatively, described buffer circuit comprises: the 13 PMOS pipe and the 14 PMOS pipe; The source electrode of described the 13 PMOS pipe connects supply voltage, and grid connects the first bias voltage, and drain electrode connects the source electrode of the 14 PMOS pipe, and as the output terminal of described buffer circuit; The grounded drain of described the 14 PMOS pipe, grid connects the output terminal of error amplifier.
Alternatively, described dividing potential drop feedback circuit comprises: the first divider resistance and the second divider resistance; The first end of described the first divider resistance connects described PMOS and adjusts transistorized drain electrode, and the second end connects the first end of the second divider resistance, and as the output branch pressure voltage of described dividing potential drop feedback circuit; The second end ground connection of described the second divider resistance.
Alternatively, described dividing potential drop feedback circuit also comprises the first electric capacity, and one end of described the first electric capacity connects described PMOS and adjusts transistorized drain electrode, and the other end connects the second end of the first divider resistance.
Compared with prior art, technical solution of the present invention at least has the following advantages:
Low-dropout linear voltage-regulating circuit comprises that error amplifier, compensating circuit, buffer circuit, PMOS adjust transistor, NMOS recommends pipe, dividing potential drop feedback circuit and output circuit.Described error amplifier, compensating circuit, buffer circuit, PMOS are adjusted transistor, dividing potential drop feedback circuit and output circuit and have been formed main control loop, and this main control loop can provide larger driving force to meet loading demand.And described error amplifier, compensating circuit, NMOS recommends pipe, dividing potential drop feedback circuit and output circuit have formed auxiliary control loop, NMOS in this auxiliary control loop recommends the breadth length ratio of pipe and adjusts transistorized breadth length ratio much smaller (it is the more than 1000 times of breadth length ratio that NMOS recommends pipe that described PMOS adjusts transistorized breadth length ratio) than main control loop PMOS, the stray capacitance of himself is adjusted transistorized stray capacitance with PMOS and is compared and can ignore, therefore NMOS recommend tube grid electric capacity can be when load current suddenlys change fast charging and discharging, thereby auxiliary control loop can promptly produce negative feedback suppresses the spike of overcharged voltage and charge less voltage effectively, make output voltage quickly recover to stationary value, so not only improve the transient response speed of circuit but also improved the precision of output voltage.
In addition, described NMOS recommends pipe when load current suddenlys change, and can directly skip buffer circuit, thereby has reduced the transmission time delay of signal in auxiliary control loop; And, described NMOS recommends pipe and described PMOS adjusts the push-pull type export structure that transistor has also formed circuit of the present invention jointly, this push-pull type export structure has advantages of that output linearity degree is good, thereby has further improved the performance of described low-dropout linear voltage-regulating circuit.
Described compensating circuit is zero compensation circuit, compare with miller-compensated circuit of the prior art, zero compensation circuit in technical solution of the present invention can avoid miller-compensated circuit when high frequency, power supply to be disturbed and is introduced directly into the defect of circuit output end, thereby can effectively improve the Power Supply Rejection Ratio of low-dropout linear voltage-regulating circuit.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of prior art mesolow difference linear voltage-stabilizing circuit;
Fig. 2 is the schematic diagram of an embodiment of low-dropout linear voltage-regulating circuit of the present invention;
Fig. 3 is the circuit diagram of an embodiment of low-dropout linear voltage-regulating circuit of the present invention;
Fig. 4 is the gain phase curve figure of low-dropout linear voltage-regulating circuit of the present invention under 10mA load;
Fig. 5 is the gain phase curve figure of low-dropout linear voltage-regulating circuit of the present invention under 100mA load;
Fig. 6 is the transient response figure of low-dropout linear voltage-regulating circuit of the present invention when load changing;
Fig. 7 is the load regulation performance plot of low-dropout linear voltage-regulating circuit of the present invention when supply voltage is 3.3V;
Fig. 8 is the line regulation performance plot of low-dropout linear voltage-regulating circuit of the present invention under 100mA load.
Embodiment
As described in the background art, traditional LDO circuit has that transient response speed is slow, the not high defect of precision of output voltage.
In the low-dropout linear voltage-regulating circuit of technical solution of the present invention, increased a NMOS and recommended pipe, described NMOS recommends the source ground of pipe, and grid connects the output terminal of error amplifier, and drain electrode connects the output terminal of LDO circuit, and PMOS adjusts transistorized drain electrode; And this NMOS recommends very little that the size of pipe can do, therefore the stray capacitance of its generation is very little, so just can produce fast response, formed a response loop fast, thereby made up large-sized PMOS and adjusted the slow-footed defect of transient response, greatly improved the transient response speed of this circuit.
The stray capacitance that described NMOS recommends pipe is very little, therefore when load current suddenlys change, error amplifier is very fast to the speed that discharges and recharges of this stray capacitance, thereby can suppress at the right time output voltage and occur overcharged voltage or charge less due to voltage spikes in transient process, thereby the precision of raising output voltage.
In addition, described NMOS recommends pipe and PMOS adjustment transistor has formed push-pull type export structure, thereby has advantages of that output linearity degree is good, therefore improves the precision of output voltage.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization without prejudice to intension of the present invention in the situation that.Therefore the present invention is not subject to the restriction of following public embodiment.
Fig. 2 shows the schematic diagram of an embodiment of low-dropout linear voltage-regulating circuit of the present invention.With reference to figure 2, described low-dropout linear voltage-regulating circuit comprises: error amplifier OP1, buffer circuit buffer1, PMOS adjust transistor MP1, NMOS and recommend pipe MN1, dividing potential drop feedback circuit 30, output circuit 40 and compensating circuit 50.
As shown in Figure 2, in this embodiment, described low-dropout linear voltage-regulating circuit comprises two feedback loops, wherein said error amplifier OP1, compensating circuit 50, buffer circuit buffer1, PMOS adjust transistor MP1, dividing potential drop feedback circuit 30 and output circuit 40 and form main control loop, the transient response speed of this main control loop is slow, therefore when load current suddenlys change, can cause output voltage precision not high.
Described error amplifier OP1, compensating circuit 50, NMOS recommend pipe MN1, dividing potential drop feedback circuit 30 and output circuit 40 and have formed another feedback loop, assist control loop, this auxiliary control loop has advantages of that transient response speed is fast, thereby the spike that can effectively suppress overcharged voltage and charge less voltage, make output voltage V out quickly recover to stationary value, and then improved the precision of output voltage.
Present embodiment makes up the deficiency of main control loop just by above-mentioned auxiliary control loop, thereby has greatly improved the fast and output voltage precision of the transient response speed of technical solution of the present invention mesolow difference linear voltage-stabilizing circuit.
Particularly, the first input end of described error amplifier OP1 (negative-phase input) receives reference voltage V bg; The second input end (normal phase input end) connects the output terminal of dividing potential drop feedback circuit 30, for receiving the branch pressure voltage Vfb of described dividing potential drop feedback circuit 30 outputs; Described error amplifier OP1 compares described reference voltage V bg and branch pressure voltage Vfb, and exports comparative result to buffer circuit buffer1.
Described buffer circuit buffer1, for described low-dropout linear voltage-regulating circuit being carried out to impedance matching with the output high impedance node of isolation error amplifier OP1 and the large stray capacitance node of grid of PMOS adjustment transistor MP1, and providing after driving for comparative result, export described comparative result to grid that described PMOS adjusts transistor MP1.
The source electrode that described PMOS adjusts transistor MP1 connects supply voltage VDDA, and drain electrode is as the output terminal of described low-dropout linear voltage-regulating circuit, for output voltage V out is exported.
Described output circuit 40 is for reducing the ripple of output voltage V out.
Particularly, described output circuit 40 comprises output capacitance CL, equivalent series resistance RL.One end of described equivalent series resistance RL connects the drain electrode that described PMOS adjusts transistor MP1, and the other end connects one end of described output capacitance CL; The other end ground connection GND of described output capacitance CL.
Similar with the output circuit shown in Fig. 1, to cause when output circuit 40 not only can reduce due to load changing in present embodiment output voltage ripple, and can also be provided high frequency zero point for the feedback loop of system.
Described dividing potential drop feedback circuit 30 is connected between the drain electrode and ground GND of described PMOS adjustment transistor MP1, and branch pressure voltage Vfb is fed back to the second input end (normal phase input end) of error amplifier OP1.
Particularly, described dividing potential drop feedback circuit 30 is partial pressure unit, comprising: the first divider resistance R1 and the second divider resistance R2.
One end of described the first divider resistance R1 connects the drain electrode that described PMOS adjusts transistor MP1; The other end connects one end of the second divider resistance R2 and as the output terminal of described dividing potential drop feedback circuit 30, branch pressure voltage Vfb is fed back to error amplifier OP1.Particularly, in the present embodiment, described branch pressure voltage Vfb is received by the grid of the 3rd PMOS pipe M3 in error amplifier OP1.The other end ground connection of described the second divider resistance R2.
Feedback network shown in the structure of described dividing potential drop feedback circuit 30 and principle of work and Fig. 1 is similar, therefore do not repeat them here.
Continuation is with reference to figure 2, and in the present embodiment, described dividing potential drop feedback circuit 30 also comprises capacitor C 3.Described capacitor C 3 can be for reducing the noise in circuit, and improve the gain margin of circuit.
Described NMOS recommends the source ground of pipe MN1, and grid connects the output terminal of error amplifier OP1, and drain electrode connects the output terminal of described low-dropout linear voltage-regulating circuit, and described PMOS adjusts the drain electrode of transistor MP1.
Particularly, the size that described NMOS recommends pipe MN1 is very little, and for example its breadth length ratio can be 20 μ m/0.5 μ m, and the stray capacitance of himself, as grid source capacitor C gs and gate leakage capacitance Cgd also very little (all below 50fF).
When load current suddenlys change, the the discharging and recharging in moment of grid source capacitor C gs that auxiliary control loop in present embodiment is recommended pipe MN1 to described NMOS completes, the grid voltage pace of change of recommending pipe MN1 due to described NMOS is exceedingly fast, its drain terminal voltage will obtain the timely control of auxiliary control loop, has also just suppressed timely overcharged voltage or charge less due to voltage spikes that output voltage V out occurs in transient process; Because overcharged voltage and charge less voltage amplitude are assisted control loop greatly to weaken, therefore greatly shortened the transit time that the output voltage V out that load changing finishes the low-dropout linear voltage-regulating circuit of rear present embodiment returns to its steady-state value, thereby greatly improved the precision of output voltage, and the load regulation of this circuit is also greatly improved.
The first end of described compensating circuit 50 connects supply voltage VDDA, and the other end connects the output terminal of error amplifier OP1.
Particularly, there are two limits of leaning on closerly in the low-dropout linear voltage-regulating circuit shown in Fig. 2, and a limit is positioned at the output terminal of error amplifier OP1, and another limit is positioned at the output terminal of this circuit, and described PMOS adjusts the drain electrode of transistor MP1.The effect of described compensating circuit 50 is to make the bandwidth inner feedback loop of system to only have a dominant pole, to guarantee that feedback control loop is all stable under various conditions.
Described compensating circuit 50 can be miller-compensated circuit.Similar with the structure shown in Fig. 1 and connected mode, one end of described miller-compensated circuit connects the output terminal of error amplifier OP1, the other end connects the drain electrode that PMOS adjusts transistor MP1, and its principle of work is well known to those skilled in the art, therefore do not repeat them here.
But described miller-compensated circuit can directly disturb by power supply the output terminal of guiding to low-dropout linear voltage-regulating circuit when high frequency, thereby worsen the Power Supply Rejection Ratio of circuit.This be because, when high frequency, the short circuit effect of miller-compensated capacitor C c is adjusted PMOS the grid of transistor MP1 together with drain electrode short circuit, and grid voltage and the source voltage (being supply voltage VDDA) of described PMOS adjustment transistor MP1 have stronger Following effect, so the interference noise of power supply can directly pass to the output terminal of low-dropout linear voltage-regulating circuit through miller-compensated capacitor C c.
Preferably, described compensating circuit 50 can also be zero compensation circuit.Shown in figure 3, described compensating circuit 50 comprises compensating resistance Rz and building-out capacitor Cz.One end of described building-out capacitor Cz connects supply voltage VDDA, and the other end connects one end of described compensating resistance Rz, and the other end of described compensating resistance Rz connects the grid that described NMOS recommends pipe MN1.
Different from miller-compensated circuit, the effect of the zero compensation circuit shown in Fig. 3 is the limit of compensating error amplifier OP1 output terminal, and then makes circuit in steady state (SS), improves the phase margin of circuit.Adopt the zero compensation circuit shown in Fig. 3 effectively to avoid, when high frequency, power supply is disturbed to the defect of directly introducing circuit output end, thereby improved the Power Supply Rejection Ratio of circuit.
Fig. 3 shows the circuit diagram of an embodiment of low-dropout linear voltage-regulating circuit of the present invention.With reference to figure 3, described error amplifier OP1 comprises: tail current source and input difference to 101, PMOS common-source common-gate current mirror 102 and NMOS constant-current source bias and folded tube 103.
Wherein, tail current source and input difference consist of a PMOS pipe M1, the 2nd PMOS pipe M2, the 3rd PMOS pipe M3 and the 4th PMOS pipe M4 101; PMOS common-source common-gate current mirror 102 consists of the 5th PMOS pipe M5, the 6th PMOS pipe M6, the 7th PMOS pipe M7 and the 8th PMOS pipe M8; NMOS constant-current source bias and folded tube 103 consist of the 9th NMOS pipe M9, the tenth NMOS pipe M10, the 11 NMOS pipe M11 and the 12 NMOS pipe M12.
The grid of the one PMOS pipe M1 connects the first bias voltage Vb1, and source electrode connects supply voltage VDDA, and drain electrode connects the source electrode of the 2nd PMOS pipe M2.
The grid of the 2nd PMOS pipe M2 connects the second bias voltage Vb2, and drain electrode connects the source electrode of the 3rd PMOS pipe M3 and the 4th PMOS pipe M4.
The 3rd PMOS pipe M3 grid connects the branch pressure voltage Vfb of dividing potential drop feedback circuit 30 outputs, and drain electrode connects the drain electrode of the 11 NMOS pipe M11.
The grid of the 4th PMOS pipe M4 connects reference voltage V bg, and described reference voltage V bg and supply voltage VDDA, temperature and technique all have nothing to do; Drain electrode connects the drain electrode of the 12 NMOS pipe M12.
The 5th PMOS pipe M5 is all connected with the grid of the 6th PMOS pipe M6 the drain electrode that the 7th PMOS manages M7, and the 5th PMOS pipe M5 is connected supply voltage VDDA with the source electrode of the 6th PMOS pipe M6, and the drain electrode of the 5th PMOS pipe M5 connects the source electrode that the 7th PMOS manages M7; The drain electrode of the 6th PMOS pipe M6 connects the source electrode of the 8th PMOS pipe M8.
The 7th PMOS pipe M7 is all connected the second bias voltage Vb2 with the grid of the 8th PMOS pipe M8, and the drain electrode of the 7th PMOS pipe M7 connects the drain electrode of the 9th NMOS pipe M9.
The drain electrode of the 8th PMOS pipe M8 connects the drain electrode of the tenth NMOS pipe M10, and as the output terminal of described error amplifier OP1.
The 9th NMOS pipe M9 is all connected the 3rd bias voltage Vb3 with the grid of the tenth NMOS pipe M10, and the source electrode of the 9th NMOS pipe M9 connects the drain electrode of the 11 NMOS pipe M11, and the source electrode of the tenth NMOS pipe M10 connects the drain electrode of the 12 NMOS pipe M12.
The 11 NMOS pipe M11 is all connected the 4th bias voltage Vb4, source grounding GND with the grid of the 12 NMOS pipe M12.
Described error amplifier OP1 is Foldable cascade error amplifier, similar with structure and the principle of Foldable cascade error amplifier in prior art, therefore do not repeat them here.
Continuation is with reference to figure 3, and described buffer circuit buffer1 is source follower, comprising: the 13 PMOS pipe M13 and the 14 PMOS pipe M14.
The source electrode of described the 13 PMOS pipe M13 connects supply voltage VDDA, and grid connects the first bias voltage Vb1, and drain electrode connects the source electrode of the 14 PMOS pipe M14, and as the output terminal of described buffer circuit buffer1.The grounded drain GND of described the 14 PMOS pipe M14, grid connects the output terminal of error amplifier OP1, i.e. the drain electrode of the 8th PMOS pipe M8.
In the present embodiment, described buffer circuit buffer1, as the intermediate buffering level of low-dropout linear voltage-regulating circuit, is mainly used in providing good impedance matching and provides larger driving force for PMOS adjusts transistor MP1.The middle buffer level of described buffer circuit buffer1 and prior art low-dropout linear voltage-regulating circuit is similar, therefore do not repeat them here.
Continuation is with reference to figure 3, and the source electrode that described PMOS adjusts transistor MP1 connects supply voltage VDDA, and drain electrode connects one end of dividing potential drop feedback circuit 30, and grid connects the output terminal of buffer circuit buffer1, i.e. the drain electrode of the 13 PMOS pipe M13.
In the present embodiment, the size that described PMOS adjusts transistor MP1 is larger, and its breadth length ratio can be the more than 1000 times or 1000 times of breadth length ratio that described NMOS recommends pipe MN1, for example, can be 1333 times.
Well known to a person skilled in the art, the load capacity of low-dropout linear voltage-regulating circuit is mainly determined by the breadth length ratio of described PMOS adjustment transistor MP1.In other words, the in the situation that in guaranteeing circuit, pressure reduction (dropout) voltage and conducting resistance being constant, LDO circuit load ability is higher, and the size (breadth length ratio in other words) that described PMOS adjusts transistor MP1 is also larger.
It is larger that but PMOS adjusts the breadth length ratio (size in other words) of transistor MP1, and parasitic grid source capacitor C gs and the gate leakage capacitance Cgd of its correspondence are also larger.When load current IL increases suddenly or reduces suddenly, LDO output voltage V out has a transient wave, LDO main control loop, because the negative feedback of dividing potential drop feedback circuit 30 will discharge and recharge PMOS adjustment transistor MP1 gate node in this transient process, guarantees that output voltage V out is substantially constant thereby make this grid voltage adjust to certain suitable value.
But, error amplifier OP1 and buffer circuit buffer1(source follower) driving force be limited after all, so large stray capacitance Cgs, Cgd that large scale PMOS adjustment transistor MP1 carries will cause its grid voltage to discharge and recharge speed, become slow all the more, cause LDO output voltage V out in transient process, to occur very large charge less due to voltage spikes (undershoot) and overcharged voltage spike (overshoot).
And that larger undershoot and overshoot voltage must make the output voltage V out of LDO return to the time that steady-state value needs is also longer, in this rapid lapse of time, LDO output voltage V out constantly changes, thereby has seriously affected precision.In a lot of high-speed applications environment, such resume speed and output accuracy are unacceptable.Typical example is the power supply of pel array in cmos image sensor (CMOS image sensor), due to reading in Microsecond grade of each Pixel Information completed, and be all accompanied by the interference of adjacent lines pixel work, if pixel power supply is slow to load current transient response speed, will on image, there is offensive horizontal stripe.In a word, the main control loop of LDO is a slow loop, the loop that transient control precision is not high.
In order to solve the problem that main control loop transient response speed is slow, output voltage precision is not high, in the present embodiment, increased a NMOS and recommended pipe MN1.
As shown in Figure 3, described NMOS recommends the source ground of pipe MN1, and drain electrode connects the drain electrode that described PMOS adjusts transistor MP1, and grid connects the output terminal of error amplifier OP1, i.e. the drain electrode of described the 8th PMOS pipe M8.
Described NMOS recommends the second feedback loop that pipe MN1 and error amplifier OP1, dividing potential drop feedback circuit 30 form the LDO circuit of the present embodiment together with output circuit 40, i.e. auxiliary control loop.
In the present embodiment, the size (breadth length ratio in other words) of recommending pipe MN1 due to described NMOS is little more a lot of than the size of described PMOS adjustment transistor MP1, therefore, described NMOS recommends the pipe MN1 stray capacitance (grid source capacitor C gs, gate leakage capacitance Cgd) of carrying and PMOS in main control loop to adjust comparing of transistor MP1 completely negligible.
When load current IL suddenlys change, error amplifier OP1 recommends the grid stray capacitance of pipe MN1 to NMOS, and to discharge and recharge speed very fast, therefore, can suppress at the right time undershoot and the overshoot due to voltage spikes that LDO output voltage V out occurs in transient process.
Because undershoot and overshoot due to voltage spikes amplitude are weakened greatly by above-mentioned auxiliary control loop, so LDO output voltage V out can return to steady-state value soon, be that load changing finishes the stabilization time that rear LDO output voltage returns to its steady-state value and greatly shortened, thereby the precision of output voltage V out is significantly improved, load regulation is also greatly improved, and is applicable to being very much applied in all kinds of high speed SOC chips.In a word, the auxiliary control loop of LDO is a fast loop, can significantly improve the loop of system accuracy.
In addition, described NMOS recommends the auxiliary control loop at pipe MN1 place when load current suddenlys change, the negative feedback directly output signal of error amplifier OP1 being formed by described auxiliary control loop transfers to the output terminal of circuit, and no longer passes through buffer circuit bufffer1(source follower).The signal that has so not only reduced auxiliary control loop (fast loop) transmits time delay, and described NMOS recommends pipe MN1 and PMOS and adjusts the push-pull type output-stage circuit that forms the present embodiment LDO together with transistor MP1, make it there is push-pull circuit, that is to say, the output linearity degree of this push-pull type output-stage circuit is better, thereby has improved the performance of described LDO circuit.
Inventor has carried out experiment simulation to the low-dropout linear voltage-regulating circuit of technical solution of the present invention based on Korea S's Dongbu0.18 μ m CIS technique, and simulation result is as shown in Fig. 4 ~ Fig. 8 particularly.
Fig. 4 is the gain phase curve figure of low-dropout linear voltage-regulating circuit of the present invention under 10mA loading condition.Wherein, the resistance of the equivalent series resistance RL in output circuit 40 is 0.1 Ω.
With reference to the N0 point ~ N3 point shown in figure 4, can draw, the low-dropout linear voltage-regulating circuit of technical solution of the present invention is that phase margin in 10mA situation is 81.02deg at load current IL, and gain margin is-44.0dB.
Fig. 5 is the gain phase curve figure of low-dropout linear voltage-regulating circuit of the present invention under 100mA loading condition.Wherein, the resistance of the equivalent series resistance RL in output circuit 40 is 0.1 Ω.
With reference to the N4 point ~ N7 point shown in figure 5, can draw, it is that phase margin in 100mA situation is 76.56deg that the low-dropout linear voltage-regulating circuit of technical solution of the present invention is operated in load current IL, and gain margin is-23.99dB.
By Fig. 4 and Fig. 5, can find out, the gain margin of the low-dropout linear voltage-regulating circuit of technical solution of the present invention and phase margin are very large, thereby can guarantee the loop stability of circuit.
Fig. 6 is the transient response figure of low-dropout linear voltage-regulating circuit of the present invention when load changing.Load changing described herein refers to: the situation when rising edge of load current IL or negative edge are 0.1 μ s.
With reference to the N8 point ~ N10 point in figure 6, the load current IL of circuit sports 100mA from 0mA when 100 μ s, and from 100mA, sports 0mA again when 120 μ s.
Suddenly change correspondingly with above-mentioned load current, there is the charge less due to voltage spikes of transient state in the moment (100 μ s) that the low-dropout linear voltage-regulating circuit of technical solution of the present invention rises suddenly at load current IL, as shown in M11 point in Fig. 6 and M12 point, the output voltage of circuit of the present invention becomes 2.989V from 3.0V.But when load current IL rises to 100mA by 0mA suddenly, the transient state charge less voltage of circuit is very little, only has about 11mV(3V-2.989V=0.011V).
Similarly, there is the overcharged voltage spike of transient state in the moment (120 μ s) that the low-dropout linear voltage-regulating circuit of technical solution of the present invention declines suddenly at load current, as shown in M13 point in Fig. 6 and M14 point, after load current IL declines suddenly, the output voltage of circuit becomes 3.021V from 3V.But when load current IL drops to 0mA by 100mA, the transient state overcharged voltage of circuit is also very little, only has about 21mV(3.021V-3V=0.021V).
As the above analysis, the low-dropout linear voltage-regulating circuit of technical solution of the present invention can effectively suppress charge less voltage and the overcharged voltage spike that output voltage occurs in transient process when load current suddenlys change, thereby makes output voltage can return to soon stationary value (the voltage stabilization value in Fig. 6 is 3V).
Fig. 7 is the load regulation performance plot of low-dropout linear voltage-regulating circuit of the present invention when supply voltage (VDDA) is 3.3V.
Known with reference to the N15 point in figure 7, when load current IL becomes 100mA from 0mA, the changing value of the output voltage of technical solution of the present invention mesolow difference linear voltage-stabilizing circuit is very little, approximately only has 29.6 μ V.In other words, the load regulation of technical solution of the present invention mesolow difference linear voltage-stabilizing circuit when supply voltage (VDDA) is 3.3V is 0.296 μ V/mA.
Fig. 8 is the line regulation performance plot of low-dropout linear voltage-regulating circuit of the present invention under 100mA load.
N16 point and N17 point in Fig. 8 are known, and when input voltage changes to 3.7V from 3.2V, output voltage has changed 50.3 μ V, and the line regulation of LDO of the present invention is 0.1006mv/V.
By above-mentioned simulation result, can be obtained the main performance index of the low-dropout linear voltage-regulating circuit of technical solution of the present invention.For performance advantage clearer, that show significantly circuit of the present invention, inventor also compares the present invention to relevant LDO design, as shown in table 1.
Wherein the 3rd classify main performance index of the present invention as, first classifies the people such as Mohammad Al-Shyoukh as adopts the performance index miller-compensated and design of buffer stage output impedance decay technique, and second classifies the people such as Yi Wang as adopts Nested Miller compensation to add the performance index of transient response intensifier circuit design.
Table 1
By the contrast in table 1, can find out, the low-dropout linear voltage-regulating circuit of technical solution of the present invention all increases significantly at aspects such as transient state charge less voltage, transient state overcharged voltage, transient response release time, load regulation, line regulations.
To sum up, the low-dropout linear voltage-regulating circuit of technical solution of the present invention has comprised main control loop and auxiliary control loop, although described main control loop transient response speed is slower, it can provide larger driving force; Described auxiliary control loop has the transient response speed being exceedingly fast, and has greatly improved the precision of output voltage.These two loops complement each other, and make LDO of the present invention really have high speed, high-precision unique advantage.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection domain of technical solution of the present invention.
Claims (7)
1. a low-dropout linear voltage-regulating circuit, is characterized in that, comprising: error amplifier, compensating circuit, buffer circuit, PMOS adjust transistor, NMOS recommends pipe, dividing potential drop feedback circuit and output circuit;
Described error amplifier, for branch pressure voltage and the reference voltage of described dividing potential drop feedback circuit output are compared, and exports comparative result to described buffer circuit;
Described buffer circuit, for carrying out impedance matching, to isolate output impedance node and the PMOS of error amplifier, adjust transistorized grid stray capacitance node, and provide after driving at the comparative result for receiving, export described comparative result to PMOS and adjust transistorized grid;
Described PMOS adjusts transistorized source electrode and connects supply voltage, and drain electrode is as the output terminal of low-dropout linear voltage-regulating circuit;
Described dividing potential drop feedback circuit, carries out dividing potential drop for described PMOS being adjusted to the voltage of transistor drain, and branch pressure voltage is fed back to error amplifier;
The grid that described NMOS recommends pipe connects the output terminal of described error amplifier, and drain electrode connects described PMOS and adjusts transistorized drain electrode, source ground;
Described output circuit connects described PMOS and adjusts transistorized drain electrode, for reducing output voltage ripple;
One end of described compensating circuit connects supply voltage, and the other end connects the output terminal of described error amplifier, for described low-dropout linear voltage-regulating circuit is compensated so that it is stable.
2. low-dropout linear voltage-regulating circuit as claimed in claim 1, is characterized in that, the ratio that described PMOS adjusts between the breadth length ratio that transistorized breadth length ratio and described NMOS recommend pipe is more than or equal to 1000.
3. low-dropout linear voltage-regulating circuit as claimed in claim 1, is characterized in that, described compensating circuit comprises: compensating resistance and building-out capacitor; One end of described building-out capacitor connects supply voltage, and the other end connects one end of described compensating resistance; The other end of described compensating resistance connects the output terminal of error amplifier.
4. low-dropout linear voltage-regulating circuit as claimed in claim 1, is characterized in that, described error amplifier comprises: tail current source and input difference are to, PMOS common-source common-gate current mirror and NMOS constant-current source bias and folded tube;
Described tail current source and input difference are to comprising a PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe and the 4th PMOS pipe; Described PMOS common-source common-gate current mirror comprises the 5th PMOS pipe, the 6th PMOS pipe, the 7th PMOS pipe and the 8th PMOS pipe; Described NMOS constant-current source bias and folded tube comprise the 9th NMOS pipe, the tenth NMOS pipe, the 11 NMOS pipe and the 12 NMOS pipe;
The grid of the one PMOS pipe connects the first bias voltage, and source electrode connects supply voltage, and drain electrode connects the source electrode of the 2nd PMOS pipe;
The grid of the 2nd PMOS pipe connects the second bias voltage, and drain electrode connects the source electrode of the 3rd PMOS pipe and the 4th PMOS pipe;
The branch pressure voltage of the connection dividing potential drop feedback circuit output of the 3rd gate pmos utmost point, drain electrode connects the drain electrode of the 11 NMOS pipe;
The grid of the 4th PMOS pipe connects reference voltage; Drain electrode connects the drain electrode of the 12 NMOS pipe;
The 5th PMOS manages the drain electrode that is all connected the 7th PMOS pipe with the grid of the 6th PMOS pipe, and the 5th PMOS pipe is connected supply voltage with the source electrode of the 6th PMOS pipe, and the drain electrode of the 5th PMOS pipe connects the source electrode of the 7th PMOS pipe; The drain electrode of the 6th PMOS pipe connects the source electrode of the 8th PMOS pipe;
The 7th PMOS pipe is all connected the second bias voltage with the grid of the 8th PMOS pipe, and the drain electrode of the 7th PMOS pipe connects the drain electrode of the 9th NMOS pipe;
The drain electrode of the 8th PMOS pipe connects the drain electrode of the tenth NMOS pipe, and as the output terminal of described error amplifier;
The 9th NMOS pipe is all connected the 3rd bias voltage with the grid of the tenth NMOS pipe, and the source electrode of the 9th NMOS pipe connects the drain electrode of the 11 NMOS pipe, and the source electrode of the tenth NMOS pipe connects the drain electrode of the 12 NMOS pipe;
The 11 NMOS pipe is all connected the 4th bias voltage with the grid of the 12 NMOS pipe, source grounding.
5. low-dropout linear voltage-regulating circuit as claimed in claim 1, is characterized in that, described buffer circuit comprises: the 13 PMOS pipe and the 14 PMOS pipe;
The source electrode of described the 13 PMOS pipe connects supply voltage, and grid connects the first bias voltage, and drain electrode connects the source electrode of the 14 PMOS pipe, and as the output terminal of described buffer circuit;
The grounded drain of described the 14 PMOS pipe, grid connects the output terminal of error amplifier.
6. low-dropout linear voltage-regulating circuit as claimed in claim 1, is characterized in that, described dividing potential drop feedback circuit comprises: the first divider resistance and the second divider resistance; The first end of described the first divider resistance connects described PMOS and adjusts transistorized drain electrode, and the second end connects the first end of the second divider resistance, and as the output branch pressure voltage of described dividing potential drop feedback circuit; The second end ground connection of described the second divider resistance.
7. low-dropout linear voltage-regulating circuit as claimed in claim 6, is characterized in that, described dividing potential drop feedback circuit also comprises the first electric capacity, and one end of described the first electric capacity connects described PMOS and adjusts transistorized drain electrode, and the other end connects the second end of the first divider resistance.
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