CN103076835A - Low drop-out linear voltage stabilizer and regulation circuit thereof - Google Patents
Low drop-out linear voltage stabilizer and regulation circuit thereof Download PDFInfo
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- CN103076835A CN103076835A CN2013100327822A CN201310032782A CN103076835A CN 103076835 A CN103076835 A CN 103076835A CN 2013100327822 A CN2013100327822 A CN 2013100327822A CN 201310032782 A CN201310032782 A CN 201310032782A CN 103076835 A CN103076835 A CN 103076835A
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Abstract
The invention discloses a low drop-out linear voltage stabilizer and a regulation circuit thereof. The low drop-out linear voltage stabilizer comprises a first PMOS (P-channel metal oxide semiconductor) transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS (N-channel metal oxide semiconductor) transistor and a first current source, wherein the grid electrode of the first PMOS transistor is connected with the drain electrode of the third PMOS transistor and the drain electrode of the first NMOS transistor; first voltage is input into the source electrode of the first PMOS transistor; the drain electrode is connected with the source electrode of the second PMOS transistor; the drain electrode of the first PMOS transistor is suitable to connect with the output end of the low drop-out linear voltage stabilizer; the grid electrode of the second PMOS transistor is suitable to connect with the output end of an error amplifier or buffer unit of the low drop-out linear voltage stabilizer; the drain electrode of the second PMOS transistor is connected with the source electrode of the first NMOS transistor and the first end of first current source; second voltage is input into the grid electrode of the third PMOS transistor, and the first voltage is input into the source electrode of the third PMOS transistor; the first voltage is input to the grid electrode of the first NMOS transistor; the second voltage is input into the second end of the first current source; and the voltage value of the first voltage is more than the voltage value of the second voltage.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly a kind of low pressure difference linear voltage regulator and Circuit tuning thereof.
Background technology
The linear mu balanced circuit of low voltage difference (Low Dropout Regulator, LDO) be the step-down type dc linear voltage regulator, along with SOC(System on Chip, SOC (system on a chip)) development of technology, it is ubiquitous in sector applications such as computing machine, communication, instrument and meter, consumer electronics, monitoring camera-shootings.Although compare with the DC-DC switching voltage converter, the efficient of LDO is low, but it has the advantages such as peripheral cell is few, ripple is little, noise is low, chip area is little, circuit structure is simple, so LDO occupies very large proportion in power management class chip always.
Along with the raising of integrated level, increasing LDO gives certain crucial module for power supply as the submodule of SOC chip and is integrated in this SOC chip, and integrated a plurality of LDO modules give different module for power supply very general in the powerful SOC chip.Frequency of operation along with the SOC system improves constantly simultaneously, and it is also more and more serious that digital circuit wherein brings power supply to disturb, and this just needs LDO that the performance requirements such as High-speed transient response speed, high output voltage control accuracy, high PSRR, low noise are arranged.
As shown in Figure 1, existing LDO circuit comprises that error amplifier OP, buffer cell buffer, PMOS adjust the degeneration factor that transistor MP, dividing potential drop feedback network, output circuit etc. consist of.
Described dividing potential drop feedback network comprises the first resistance R 1, the second resistance R 2.Described the first resistance R 1 and the second resistance R 2 form partial pressure unit, and branch pressure voltage VF is fed back to the normal phase input end of error amplifier OP.The negative-phase input input reference voltage vref of described error amplifier OP.
Described output circuit is comprised of equivalent series resistance ESR and output capacitance CL.Output circuit not only can reduce because the output voltage ripple that causes during load changing, and can also be provided high frequency zero point for the feedback loop of system.
In the LDO course of work, the voltage die of LDO output end vo ut can cause the lower voltage of branch pressure voltage VF, the branch pressure voltage VF that reduces is by after error amplifier OP and the buffer cell buffer, finally be reflected to the also corresponding reduction of grid voltage that PMOS adjusts transistor MP, the reduction of grid voltage is so that PMOS adjusts the leakage current increase of transistor MP, thereby improve the voltage of LDO output end vo ut, make it return to the front magnitude of voltage of bust.
In the adjustment process of output voltage, the change in voltage of LDO output end vo ut need to be adjusted transistor MP grid by just being reflected to PMOS after error amplifier OP and the buffer cell buffer.And the transistor size that error amplifier OP adopts is all larger, and to adjust the required time of transistor MP grid longer so the variation voltage of LDO output end vo ut finally is reflected to PMOS, causes the voltage recovery rate of LDO output end vo ut slower.
Summary of the invention
The problem that the present invention solves be existing low pressure difference linear voltage regulator to the output voltage regulating power that changes a little less than.
For addressing the above problem, technical solution of the present invention provides a kind of Circuit tuning of low pressure difference linear voltage regulator, comprising: a PMOS transistor, the 2nd PMOS transistor, the 3rd PMOS transistor, the first nmos pass transistor and the first current source;
The transistorized grid of a described PMOS connects the drain electrode of the transistorized drain electrode of described the 3rd PMOS and the first nmos pass transistor, source electrode is inputted the first voltage, drain electrode connects the transistorized source electrode of described the 2nd PMOS, and the transistorized drain electrode of a described PMOS is suitable for being connected with the output terminal of described low pressure difference linear voltage regulator;
The transistorized grid of described the 2nd PMOS is suitable for being connected with the error amplifier of described low pressure difference linear voltage regulator or the output terminal of buffer cell, and drain electrode connects the source electrode of described the first nmos pass transistor and the first end of the first current source;
The transistorized grid input of described the 3rd PMOS second voltage, source electrode is inputted described the first voltage;
The grid of described the first nmos pass transistor is inputted described the first voltage;
The second end of described the first current source is inputted described second voltage;
The magnitude of voltage of described the first voltage is greater than the magnitude of voltage of described second voltage.
Optionally, a described PMOS transistor, the 2nd PMOS transistor, the 3rd PMOS transistor and the first nmos pass transistor all are operated in the saturation region.
Technical solution of the present invention also provides a kind of low pressure difference linear voltage regulator, comprising: error amplifier, the first resistance, the second resistance and Circuit tuning;
The first end of described the first resistance is the output terminal of described low pressure difference linear voltage regulator, and the second end connects the first end of described the second resistance and the second input end of described error amplifier;
The second end input second voltage of described the second resistance;
The first input end input reference voltage of described error amplifier;
Described Circuit tuning comprises: a PMOS transistor, the 2nd PMOS transistor, the 3rd PMOS transistor, the first nmos pass transistor and the first current source;
The transistorized grid of a described PMOS connects the drain electrode of the transistorized drain electrode of described the 3rd PMOS and the first nmos pass transistor, and source electrode is inputted the first voltage, and drain electrode connects the output terminal of the transistorized source electrode of described the 2nd PMOS and described low pressure difference linear voltage regulator;
The transistorized grid of described the 2nd PMOS connects the output terminal of the error amplifier of described low pressure difference linear voltage regulator, and drain electrode connects the source electrode of described the first nmos pass transistor and the first end of the first current source;
The transistorized grid of described the 3rd PMOS is inputted described second voltage, and source electrode connects described the first voltage;
The grid of described the first nmos pass transistor is inputted described the first voltage;
The second end of described the first current source is inputted described second voltage;
The magnitude of voltage of described the first voltage is greater than the magnitude of voltage of described second voltage.
Optionally, a described PMOS transistor, the 2nd PMOS transistor, the 3rd PMOS transistor and the first nmos pass transistor all are operated in the saturation region.
Optionally, described error amplifier comprises: the 4th PMOS transistor, the 5th PMOS transistor, the 6th PMOS transistor, the 7th PMOS transistor, the second nmos pass transistor, the 3rd nmos pass transistor, the 4th nmos pass transistor, the 5th nmos pass transistor and the second current source;
The transistorized grid of described the 4th PMOS connects the drain electrode of described the 4th PMOS transistor drain, the transistorized grid of the 6th PMOS and the second nmos pass transistor, and source electrode is inputted described the first voltage;
The transistorized grid of described the 5th PMOS connects the drain electrode of described the 5th PMOS transistor drain, the transistorized grid of the 7th PMOS and the 3rd nmos pass transistor, and source electrode is inputted described the first voltage;
The transistorized source electrode of described the 6th PMOS is inputted described the first voltage, and drain electrode connects drain electrode, the grid of the 4th nmos pass transistor and the grid of the 5th nmos pass transistor of described the 4th nmos pass transistor;
The transistorized source electrode of described the 7th PMOS is inputted described the first voltage, and drain electrode connects the grid of the drain electrode of described the 5th nmos pass transistor and the 5th nmos pass transistor and as the output terminal of described error amplifier;
The grid of described the second nmos pass transistor is the second input end of described error amplifier, and source electrode connects the first end of described the second current source and the source electrode of the 3rd nmos pass transistor;
The grid of described the 3rd nmos pass transistor is the first input end of described error amplifier;
The source electrode of described the 4th nmos pass transistor is inputted described second voltage;
The source electrode of described the 5th nmos pass transistor is inputted described second voltage;
The second end of described the second current source is inputted described second voltage.
Optionally, described the 4th PMOS transistor, the 5th PMOS transistor, the 6th PMOS transistor, the 7th PMOS transistor, the second nmos pass transistor, the 3rd nmos pass transistor, the 4th nmos pass transistor and the 5th nmos pass transistor all are operated in the saturation region.
Optionally, described low pressure difference linear voltage regulator also comprises buffer cell, the transistorized grid of described the 2nd PMOS is connected with the output terminal of error amplifier by described buffer cell, and described buffer cell is suitable for described low pressure difference linear voltage regulator is carried out impedance matching.
Optionally, described low pressure difference linear voltage regulator also comprises: resistance in series and output capacitance; The first end of described resistance in series connects the output terminal of described low pressure difference linear voltage regulator, and the second end of described resistance in series connects the first end of described output capacitance, and the second end of described output capacitance is inputted described second voltage.
Compared with prior art, technical solution of the present invention has the following advantages at least:
When the output end voltage of low pressure difference linear voltage regulator reduced, the corresponding reduction of the transistorized drain voltage meeting of the 2nd PMOS in the Circuit tuning that the embodiment of the invention provides caused the also corresponding reduction of the transistorized grid voltage of a PMOS then; And the voltage of reduction can also be by error amplifier so that the also corresponding reduction of the transistorized grid voltage of the 2nd PMOS; By a PMOS transistor and the transistorized acting in conjunction of the 2nd PMOS, so that the output end voltage of low pressure difference linear voltage regulator returns to rapidly the front magnitude of voltage of voltage drop, its response speed is very fast, so that the output end voltage of low pressure difference linear voltage regulator is more stable.
Description of drawings
Fig. 1 is the circuit diagram of prior art mesolow difference linear voltage-stabilizing circuit;
Fig. 2 is the circuit diagram of the Circuit tuning of the embodiment of the invention one;
Fig. 3 is the circuit diagram of the low-dropout linear voltage-regulating circuit of the embodiment of the invention two;
Fig. 4 is the circuit diagram of the error amplifier of the embodiment of the invention two;
Fig. 5 is the circuit diagram of the low-dropout linear voltage-regulating circuit of the embodiment of the invention three.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.According to following explanation, advantages and features of the invention will be clearer.
Just as described in the background art, the situation of bust can occur in the voltage of LDO output end vo ut in the LDO course of work, for example need LDO to provide the device of voltage to access suddenly LDO, and the voltage of described variation need to just can feed back to the grid that PMOS adjusts transistor MP afterwards through stray capacitance larger error amplifier OP and buffer cell buffer, time is longer, has reduced the regulating power of LDO to output voltage.
As shown in Figure 2, in order to address the above problem, the embodiment of the invention one provides a kind of Circuit tuning of low pressure difference linear voltage regulator, comprising: a PMOS transistor MP1, the 2nd PMOS transistor MP2, the 3rd PMOS transistor MP3, the first nmos pass transistor MN1 and the first current source IL1.
The grid of a described PMOS transistor MP1 connects the drain electrode of described the 3rd PMOS transistor MP3 and the drain electrode of the first nmos pass transistor MN1, source electrode is inputted the first voltage VCC, drain electrode connects the source electrode of described the 2nd PMOS transistor MP2, and the drain electrode of a described PMOS transistor MP1 is suitable for being connected with the output terminal of described low pressure difference linear voltage regulator.
The grid of described the 2nd PMOS transistor MP2 is suitable for being connected with the error amplifier of described low pressure difference linear voltage regulator or the output terminal of buffer cell, and drain electrode connects the source electrode of described the first nmos pass transistor MN1 and the first end of the first current source IL1.
The grid input second voltage GND of described the 3rd PMOS transistor MP3, source electrode is inputted described the first voltage VCC.
The grid of described the first nmos pass transistor MN1 is inputted described the first voltage VCC.
The second end of described the first current source IL1 is inputted described second voltage GND.
The magnitude of voltage of described the first voltage VCC is greater than the magnitude of voltage of described second voltage GND.Optionally, described the first voltage VCC is supply voltage, and described second voltage GND is ground voltage.
A described PMOS transistor MP1, the 2nd PMOS transistor MP2, the 3rd PMOS transistor MP3 and the first nmos pass transistor MN1 all are operated in the saturation region.
Described the first current source IL1 can select the comparatively suitable current source of output current according to actual needs, and the larger efficient of output current is higher.
When the output end voltage of low pressure difference linear voltage regulator reduced, the corresponding reduction of the drain voltage VC of embodiment one described the 2nd PMOS transistor MP2 meeting caused the also corresponding reduction of grid voltage VB of a PMOS transistor MP1 then; And the voltage of reduction also passes through error amplifier OP so that the also corresponding reduction of the grid voltage of the 2nd PMOS transistor MP2; By the acting in conjunction of a PMOS transistor MP1 and the 2nd PMOS transistor MP2, so that the output end voltage of low pressure difference linear voltage regulator returns to rapidly the front magnitude of voltage of voltage drop.The stray capacitance of the Circuit tuning that the embodiment of the invention one provides is far smaller than the stray capacitance of error amplifier, so its response speed is very fast, so that the output end voltage of low pressure difference linear voltage regulator is more stable.
As shown in Figure 3, the embodiment of the invention two provides a kind of low pressure difference linear voltage regulator, comprising: error amplifier OP, the first resistance R 1, the second resistance R 2 and Circuit tuning 1.
The first end of described the first resistance R 1 is the output end vo ut of described low pressure difference linear voltage regulator, and the second end connects the first end of described the second resistance R 2 and the second input end IN2 of described error amplifier OP.
The second end input second voltage GND of described the second resistance R 2.
The first input end IN1 input reference voltage of described error amplifier OP.
Described Circuit tuning 1 can adopt the Circuit tuning of above-described embodiment one, wherein, the drain electrode of a described PMOS transistor MP1 is connected with the output end vo ut of low pressure difference linear voltage regulator, and the grid of described the 2nd PMOS transistor MP2 is connected with the output terminal OUT1 of the error amplifier of low pressure difference linear voltage regulator.
As shown in Figure 4, described error amplifier OP can comprise: the 4th PMOS transistor MP4, the 5th PMOS transistor MP5, the 6th PMOS transistor MP6, the 7th PMOS transistor MP7, the second nmos pass transistor MN2, the 3rd nmos pass transistor MN3, the 4th nmos pass transistor MN4, the 5th nmos pass transistor MN5 and the second current source IL2.
The grid of described the 4th PMOS transistor MP4 connects described the 4th PMOS transistor MP4 drain electrode, the grid of the 6th PMOS transistor MP6 and the drain electrode of the second nmos pass transistor MN2, and source electrode is inputted described the first voltage VCC.
The grid of described the 5th PMOS transistor MP5 connects described the 5th PMOS transistor MP5 drain electrode, the grid of the 7th PMOS transistor MP7 and the drain electrode of the 3rd nmos pass transistor MN3, and source electrode is inputted described the first voltage VCC.
The source electrode of described the 6th PMOS transistor MP6 is inputted described the first voltage VCC, and drain electrode connects drain electrode, the grid of the 4th nmos pass transistor MN4 and the grid of the 5th nmos pass transistor MN5 of described the 4th nmos pass transistor MN4.
The source electrode of described the 7th PMOS transistor MP7 is inputted described the first voltage VCC, and drain electrode connects the grid of the drain electrode of described the 5th nmos pass transistor MN5 and the 5th nmos pass transistor MN5 and as the output terminal OUT1 of described error amplifier OP.
The grid of described the second nmos pass transistor MN2 is the second input end IN2 of described error amplifier, and source electrode connects the first end of described the second current source IL2 and the source electrode of the 3rd nmos pass transistor MN3.
The grid of described the 3rd nmos pass transistor MN3 is the first input end IN1 of described error amplifier.
The source electrode of described the 4th nmos pass transistor MN4 is inputted described second voltage GND.
The source electrode of described the 5th nmos pass transistor MN5 is inputted described second voltage GND.
The second end of described the second current source IL2 connects the described second voltage GND of IN2.
It will be understood by those skilled in the art that described error amplifier OP is not limited to structure shown in Figure 4, can also adopt other to realize the circuit structure of identical function.
The present embodiment two can also comprise output circuit, and described output circuit comprises: resistance in series ESR and output capacitance CL.The first end of described resistance in series ESR connects the output end vo ut of low pressure difference linear voltage regulator, and the second end connects the first end of output capacitance CL.The second end input second voltage GND of described output capacitance CL.Described output circuit not only can reduce because the output voltage ripple that causes during load changing, and can also be provided high frequency zero point for the feedback loop of system.
In embodiment two, when the output end voltage of low pressure difference linear voltage regulator reduces, the voltage that reduces passes through Circuit tuning so that the grid voltage of a PMOS transistor MP1 descends, and, the voltage that reduces also passes through error amplifier OP so that the grid voltage of the 2nd PMOS transistor MP2 descends, the one PMOS transistor MP1 and the 2nd PMOS transistor MP2 are all as adjusting transistor, by the acting in conjunction of a PMOS transistor MP1 and the 2nd PMOS transistor MP2, can recover faster the output end voltage of low pressure difference linear voltage regulator.
As shown in Figure 5, the embodiment of the invention three is with the difference of embodiment two, and the grid of the 2nd PMOS transistor MP2 is connected with the output terminal OUT1 of error amplifier OP by buffer cell buffer in the Circuit tuning 1.Described buffer cell buffer can carry out impedance matching to described low-dropout linear voltage-regulating circuit, and the circuit structure of described buffer cell buffer can adopt existing circuit structure, no longer launches explanation at this.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection domain of technical solution of the present invention according to technical spirit of the present invention.
Claims (8)
1. the Circuit tuning of a low pressure difference linear voltage regulator is characterized in that, comprising: a PMOS transistor, the 2nd PMOS transistor, the 3rd PMOS transistor, the first nmos pass transistor and the first current source;
The transistorized grid of a described PMOS connects the drain electrode of the transistorized drain electrode of described the 3rd PMOS and the first nmos pass transistor, source electrode is inputted the first voltage, drain electrode connects the transistorized source electrode of described the 2nd PMOS, and the transistorized drain electrode of a described PMOS is suitable for being connected with the output terminal of described low pressure difference linear voltage regulator;
The transistorized grid of described the 2nd PMOS is suitable for being connected with the error amplifier of described low pressure difference linear voltage regulator or the output terminal of buffer cell, and drain electrode connects the source electrode of described the first nmos pass transistor and the first end of the first current source;
The transistorized grid input of described the 3rd PMOS second voltage, source electrode is inputted described the first voltage;
The grid of described the first nmos pass transistor is inputted described the first voltage;
The second end of described the first current source is inputted described second voltage;
The magnitude of voltage of described the first voltage is greater than the magnitude of voltage of described second voltage.
2. Circuit tuning as claimed in claim 1 is characterized in that, a described PMOS transistor, the 2nd PMOS transistor, the 3rd PMOS transistor and the first nmos pass transistor all are operated in the saturation region.
3. a low pressure difference linear voltage regulator is characterized in that, comprising: error amplifier, the first resistance, the second resistance and Circuit tuning;
The first end of described the first resistance is the output terminal of described low pressure difference linear voltage regulator, and the second end connects the first end of described the second resistance and the second input end of described error amplifier;
The second end input second voltage of described the second resistance;
The first input end input reference voltage of described error amplifier;
Described Circuit tuning comprises: a PMOS transistor, the 2nd PMOS transistor, the 3rd PMOS transistor, the first nmos pass transistor and the first current source;
The transistorized grid of a described PMOS connects the drain electrode of the transistorized drain electrode of described the 3rd PMOS and the first nmos pass transistor, and source electrode is inputted the first voltage, and drain electrode connects the output terminal of the transistorized source electrode of described the 2nd PMOS and described low pressure difference linear voltage regulator;
The transistorized grid of described the 2nd PMOS connects the output terminal of the error amplifier of described low pressure difference linear voltage regulator, and drain electrode connects the source electrode of described the first nmos pass transistor and the first end of the first current source;
The transistorized grid of described the 3rd PMOS is inputted described second voltage, and source electrode connects described the first voltage;
The grid of described the first nmos pass transistor is inputted described the first voltage;
The second end of described the first current source is inputted described second voltage;
The magnitude of voltage of described the first voltage is greater than the magnitude of voltage of described second voltage.
4. low pressure difference linear voltage regulator as claimed in claim 3 is characterized in that, a described PMOS transistor, the 2nd PMOS transistor, the 3rd PMOS transistor and the first nmos pass transistor all are operated in the saturation region.
5. low pressure difference linear voltage regulator as claimed in claim 3, it is characterized in that, described error amplifier comprises: the 4th PMOS transistor, the 5th PMOS transistor, the 6th PMOS transistor, the 7th PMOS transistor, the second nmos pass transistor, the 3rd nmos pass transistor, the 4th nmos pass transistor, the 5th nmos pass transistor and the second current source;
The transistorized grid of described the 4th PMOS connects the drain electrode of described the 4th PMOS transistor drain, the transistorized grid of the 6th PMOS and the second nmos pass transistor, and source electrode is inputted described the first voltage;
The transistorized grid of described the 5th PMOS connects the drain electrode of described the 5th PMOS transistor drain, the transistorized grid of the 7th PMOS and the 3rd nmos pass transistor, and source electrode is inputted described the first voltage;
The transistorized source electrode of described the 6th PMOS is inputted described the first voltage, and drain electrode connects drain electrode, the grid of the 4th nmos pass transistor and the grid of the 5th nmos pass transistor of described the 4th nmos pass transistor;
The transistorized source electrode of described the 7th PMOS is inputted described the first voltage, and drain electrode connects the grid of the drain electrode of described the 5th nmos pass transistor and the 5th nmos pass transistor and as the output terminal of described error amplifier;
The grid of described the second nmos pass transistor is the second input end of described error amplifier, and source electrode connects the first end of described the second current source and the source electrode of the 3rd nmos pass transistor;
The grid of described the 3rd nmos pass transistor is the first input end of described error amplifier;
The source electrode of described the 4th nmos pass transistor is inputted described second voltage;
The source electrode of described the 5th nmos pass transistor is inputted described second voltage;
The second end of described the second current source is inputted described second voltage.
6. low pressure difference linear voltage regulator as claimed in claim 5, it is characterized in that, described the 4th PMOS transistor, the 5th PMOS transistor, the 6th PMOS transistor, the 7th PMOS transistor, the second nmos pass transistor, the 3rd nmos pass transistor, the 4th nmos pass transistor and the 5th nmos pass transistor all are operated in the saturation region.
7. low pressure difference linear voltage regulator as claimed in claim 3, it is characterized in that, also comprise buffer cell, the transistorized grid of described the 2nd PMOS is connected with the output terminal of error amplifier by described buffer cell, and described buffer cell is suitable for described low pressure difference linear voltage regulator is carried out impedance matching.
8. low pressure difference linear voltage regulator as claimed in claim 3 is characterized in that, also comprises: resistance in series and output capacitance; The first end of described resistance in series connects the output terminal of described low pressure difference linear voltage regulator, and the second end of described resistance in series connects the first end of described output capacitance, and the second end of described output capacitance is inputted described second voltage.
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| CN111665893A (en) * | 2020-06-23 | 2020-09-15 | 上海安路信息科技有限公司 | Low dropout regulator of NMOS output power tube |
| CN111665893B (en) * | 2020-06-23 | 2022-02-01 | 上海安路信息科技股份有限公司 | Low dropout regulator of NMOS output power tube |
| CN115079765A (en) * | 2022-08-23 | 2022-09-20 | 上海韬润半导体有限公司 | Linear voltage regulator and integrated circuit device including the same |
| CN116069108A (en) * | 2023-04-03 | 2023-05-05 | 上海安其威微电子科技有限公司 | LDO circuit with quick response |
| CN116069108B (en) * | 2023-04-03 | 2023-07-07 | 上海安其威微电子科技有限公司 | LDO circuit with quick response |
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