CN102279612A - Low dropout linear regulator - Google Patents

Abstract

The invention discloses a low dropout linear regulator. Aiming at the complex structure of the existing low dropout linear regulator, the low dropout linear regulator (LDO) comprises an error amplifier, a feedback sampling network, a biasing circuit and a rocking rate enhancement circuit and is characterized in that: one portion of the rocking rate enhancement circuit is included in the error amplifier; the error amplifier comprises a first P-channel metal oxide semiconductor (PMOS) transistor, a second PMOS transistor, a first N-channel metal oxide semiconductor (NMOS) transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor; the first NMOS transistor and the second NMOS transistor are as the composition portions of the rocking rate enhancement circuit; and the rocking rate enhancement circuit further comprises a first capacitor and a second capacitor. In the regulator, the rocking rate enhancement circuit is formed by two NMOS transistors and two capacitors without excessive additional auxiliary circuits so that the structure is simple and the power consumption is low. On the premise of not reducing performance, the regulator can be applied to a low voltage and has extremely rapid transient response.

Description

A kind of low pressure difference linear voltage regulator

Technical field

The invention belongs to the power management techniques field, be specifically related to the design of a kind of low pressure difference linear voltage regulator (LDO, Low Dropout Regulator).

Background technology

As the solution of improving full battery supply set quiescent dissipation and battery-powered time, power management module plays important effect.Low pressure difference linear voltage regulator is as an important kind in the power management module, owing to providing low noise, high-precision supply voltage to be widely used can for the analog module of noise-sensitive.Along with the widespread use of portable set, new requirement has also been proposed for the performance of LDO: lower power consumption, promptly littler quiescent current; Better transient response, promptly more excellent compensation way and topological structure.

Low pressure, no electric capacity LDO for can only integrated limited load capacitance have proposed multiple Slew Rate intensifier circuit and have realized quick load transient response.In order to guarantee low quiescent current, current many advanced persons' Slew Rate intensifier circuit (SRE, Slew Rate Enhancement) all is designed to the function of load current, but this design can cause big power consumption under heavy duty, and traditional limited output voltage swing of SRE voltage buffer is not suitable at operation at low power supply voltage it.And other some designs, such as adopting the capacitive coupling technology, more complicated and needing increases many other auxiliary circuits, and these auxiliary circuits can limit it and use on base amplifier.

Summary of the invention

The objective of the invention is to have proposed a kind of low pressure difference linear voltage regulator for the baroque problem of the low pressure difference linear voltage regulator that solves existing quick load transient response.

Technical scheme of the present invention: a kind of low pressure difference linear voltage regulator, comprise error amplifier, feedback sample network, biasing circuit and Slew Rate intensifier circuit, it is characterized in that, the part of Slew Rate intensifier circuit is contained among the error amplifier, and error amplifier comprises PMOS pipe, the 2nd PMOS pipe, NMOS pipe, the 2nd NMOS pipe and the 3rd NMOS pipe, the 4th NMOS pipe; Wherein NMOS pipe and the 2nd NMOS pipe are again as the ingredient of Slew Rate intensifier circuit, and the Slew Rate intensifier circuit also comprises first electric capacity and second electric capacity; The feedback sample network comprises the 3rd PMOS pipe, first resistance, second resistance and the 3rd resistance;

Concrete annexation is as follows: PMOS pipe, the 2nd PMOS pipe are connected with the supply voltage of outside respectively with the source electrode of the 3rd PMOS pipe, the grid leak short circuit of a PMOS pipe, and link to each other with the grid of the 2nd PMOS pipe, the drain electrode of a NMOS pipe; The drain electrode of the 2nd PMOS pipe links to each other with the drain electrode of the 2nd NMOS pipe, the grid of the one NMOS pipe links to each other with the grid of the 3rd NMOS pipe, the grid of the 2nd NMOS pipe links to each other with the grid of the 4th NMOS pipe, the source electrode of the one NMOS pipe links to each other with the drain electrode of the 3rd NMOS pipe, the source electrode of the 2nd NMOS pipe links to each other with the drain electrode of the 4th NMOS pipe and as the input end of described low pressure difference linear voltage regulator, the 3rd NMOS pipe links to each other with biasing circuit with the source electrode of the 4th NMOS pipe, the source electrode of the 2nd NMOS pipe links to each other with an end of first electric capacity, the other end of first electric capacity links to each other with an end of second electric capacity, and as the output terminal of described low pressure difference linear voltage regulator, the other end of second electric capacity links to each other with the input end of biasing circuit; The grid of the 3rd PMOS pipe links to each other with the drain electrode of the 2nd PMOS pipe, and first, second, third resistance is connected between the drain electrode and ground of the 3rd PMOS pipe in turn; Second links to each other with the grid of the 3rd NMOS pipe with the tie point of the 3rd resistance.

Further, described biasing circuit comprises the 5th NMOS pipe, the 6th NMOS pipe and the 7th NMOS pipe, the source electrode of wherein said NMOS pipe is ground connection respectively, the grid of described NMOS pipe links to each other with the drain electrode of the 5th NMOS pipe respectively, the drain electrode of the 6th NMOS pipe connects the source electrode of the 4th NMOS pipe of described error amplifier, the drain electrode of the 5th NMOS pipe is as the input termination external current source of biasing circuit, and the drain electrode of the 7th NMOS pipe connects the output terminal of described low pressure difference linear voltage regulator.

Further, described low pressure difference linear voltage regulator also comprises compensating circuit, described compensating circuit comprises the 3rd electric capacity, the 4th electric capacity and the 4th resistance, wherein, one end of the 3rd electric capacity links to each other with the grid of the 3rd PMOS pipe of feedback sample network, the other end links to each other with an end of the 4th resistance, and the other end of the 4th resistance links to each other with an end of the output terminal of described low pressure difference linear voltage regulator and the 4th electric capacity, and the other end of the 4th electric capacity links to each other with the grid of the 4th NMOS pipe of error amplifier.

Beneficial effect of the present invention: linear voltage regulator of the present invention has constituted the Slew Rate intensifier circuit by two NMOS pipes and two electric capacity, do not need too much extra auxiliary circuit, simple in structure, power consumption is lower, do not reducing under the performance prerequisite, can be applied to have the transient response that is exceedingly fast under the low pressure.

Description of drawings

Fig. 1 is a low pressure difference linear voltage regulator structural representation of the present invention.

Fig. 2 is the integrated circuit synoptic diagram of low pressure difference linear voltage regulator of the present invention.

Fig. 3 is the small-signal equivalent circuit synoptic diagram of low pressure difference linear voltage regulator of the present invention.

Embodiment

The invention will be further elaborated below in conjunction with accompanying drawing and specific embodiment.

Low pressure difference linear voltage regulator structural representation of the present invention as shown in Figure 1, comprise error amplifier Slew Rate intensifier circuit and feedback sample network, and the Slew Rate intensifier circuit is to be integrated between error amplifier and the output VOUT, and CF1, CF2 are used for carrying out miller compensation and phase lead compensation respectively.

Integrated circuit synoptic diagram such as Fig. 2 of LDO of the present invention, a kind of low pressure difference linear voltage regulator, comprise error amplifier, feedback sample network, biasing circuit and Slew Rate intensifier circuit, the part of Slew Rate intensifier circuit is contained among the error amplifier, and error amplifier comprises that a PMOS pipe MP1, the 2nd PMOS pipe MP2, NMOS pipe MN1, the 2nd NMOS pipe MN2 and the 3rd NMOS pipe MN3, the 4th NMOS manage MN4; Wherein NMOS pipe MN1 and the 2nd NMOS pipe MN2 are again as the ingredient of Slew Rate intensifier circuit, and the Slew Rate intensifier circuit also comprises first capacitor C 1 and second capacitor C 2; The feedback sample network comprises the 3rd PMOS pipe MP3, the first resistance R F1, the second resistance R F2 and the 3rd resistance R F3;

Concrete annexation is as follows: the source electrode of a PMOS pipe MP1, the 2nd PMOS pipe MP2 and the 3rd PMOS pipe MP3 is connected with the supply voltage VDD of outside respectively, the one PMOS manages the grid leak short circuit of MP1, and links to each other with the grid of the 2nd PMOS pipe MP2, the drain electrode of NMOS pipe MN1; The drain electrode of the 2nd PMOS pipe MP2 links to each other with the drain electrode of the 2nd NMOS pipe MN2, the grid of the one NMOS pipe MN1 links to each other with the grid of the 3rd NMOS pipe MN3, the grid of the 2nd NMOS pipe MN2 links to each other with the grid of the 4th NMOS pipe, the source electrode of the one NMOS pipe MN1 links to each other with the drain electrode of the 3rd NMOS pipe MN3, the source electrode of the 2nd NMOS pipe MN2 links to each other with the drain electrode of the 4th NMOS pipe MN4, and as the input end of described LDO, input reference voltage VREF, the 3rd NMOS pipe MN3 links to each other with biasing circuit with the source electrode of the 4th NMOS pipe MN4, the source electrode of the 2nd NMOS pipe MN2 links to each other with an end of first capacitor C 1, the other end of first capacitor C 1 links to each other with an end of second capacitor C 2, and as the output terminal VOUT of described LDO, the other end of second capacitor C 2 links to each other with the input end of biasing circuit; The grid of the 3rd PMOS pipe MP3 links to each other with the drain electrode of the 2nd PMOS pipe MP2, and the first resistance R F1, the second resistance R F2 and the 3rd resistance R F3 are connected between the drain electrode and ground of the 3rd PMOS pipe MP3 in turn; The tie point VFB of the second resistance R F2 and the 3rd resistance R F3 links to each other with the grid of the 3rd NMOS pipe MN3.Here the 3rd PMOS pipe MP3 is a power tube.

Here, biasing circuit comprises the 5th NMOS pipe MN5, the 6th NMOS pipe MN6 and the 7th NMOS pipe MN7, the source electrode of wherein said NMOS pipe is ground connection respectively, the grid of described NMOS pipe links to each other with the drain electrode of the 5th NMOS pipe MN5 respectively, the drain electrode of the 6th NMOS pipe MN6 connects the source electrode of the 4th NMOS pipe MN4 of described error amplifier, the drain electrode of the 5th NMOS pipe MN5 is as the input termination external current source IB of biasing circuit, and the drain electrode of the 7th NMOS pipe MN7 connects the output terminal of described LDO.

Here, described LDO also comprises compensating circuit, described compensating circuit comprises the 3rd capacitor C F1, the 4th capacitor C F2 and the 4th resistance R C, wherein, the end of the 3rd capacitor C F1 links to each other with the grid of the 3rd PMOS of feedback sample network pipe MP3, the other end links to each other with the end of the 4th resistance R C, and the other end of the 4th resistance R C links to each other with the end of the output terminal of LDO and the 4th capacitor C F2, and the other end of the 4th capacitor C F2 links to each other with the grid of the 4th NMOS pipe MN4 of error amplifier.

LDO of the present invention can be counted as two-stage amplifier, and wherein MP1, MP2, MN3 and MN4 are as the single electrode voltage amplifier of the first order, and power tube MP3 is as the second level input of amplifier, and MN5, MN7 and MN6 form biasing circuit.

The Slew Rate intensifier circuit comprises as the capacitive coupling feedforward compensation: MN1, MN2 and C1, C2.Because the application of capacitive coupling method no matter be all not have unnecessary quiescent current to append to major loop under underload or heavy duty, and only is quiescent current IQ.Owing to only used several devices and some mirror-image structures, made this structure can be used in the general differential amplifier.

The minimum voltage of power tube grid is for making MN6, MN2 be operated in the saturation region, wherein M5 work linear zone, that is: V _{Dsat, MN6}+ V _{Ds, MN4}+ V _{Dsat, MN2}=V _Low＜V _{Dsat, MN6}+ V _{Dsat, MN4}+ V _{Dsat, MN2}

V wherein _{Dsat, MN4}, V _{Dsat, MN6}, V _{Dsat, MN2}Be respectively the saturated drain-source voltage of MN4, MN6, MN2, V _{Ds, MN4}Be the drain-source voltage of MN4 when the linear zone, V _LowMinimum voltage for the power tube grid.

And traditional Slew Rate strengthens the general source follower of using as impact damper, and this is limited in its dynamic range | V _THP|+2V _OV: V _IN-V _OV(V wherein _THPBe the threshold voltage of PMOS pipe, V _OVBe the overdrive voltage of metal-oxide-semiconductor, V _INSupply voltage VDD for the outside).And the dynamic range of the power tube grid potential that the present invention mentions is (V _Low: V _IN-V _OV), make it be more suitable for low pressure applications.

LDO small-signal model proposed by the invention as shown in Figure 3.A _IAnd r _oThe equivalent voltage gain and the output resistance that are divided into the single-stage differential amplifier of the first order, g _MpiRepresent the mutual conductance of i PMOS pipe, g _MniRepresent the mutual conductance of i NMOS pipe, R _LOADBe pull-up resistor, the equivalent output resistance of output terminal can be write as R _LOADP(R _F1+ R _F2+ R _F3).Ignore high frequency zero limit, transition function

Can be expressed as

$H\left(s\right)=g_{\mathrm{mp}3}{r}_{\mathrm{eq}}{A}_1\frac{R_{F3}}{R_{F1}+R_{F2}+R_{F3}}\frac{(1+\frac{s}{z_m})(1+\frac{s}{z_f})}{(1+\frac{s}{p_1})(1+\frac{s}{p_2})(1+\frac{s}{p_f})}$ Formula (1)

Wherein $z_m=1/(R_C-\frac{1}{g_{\mathrm{mp}3}})C_{F1}$ Formula (2)

z _f=1/[(R _F1+ R _F2) C _F2] formula (3)

p ₁=1/r _EqC _LFormula (4)

p ₂=1/g _Mp3r _Eqr ₀C _F1Formula (5)

p _f=1/{[(R _F1+ R _F2) PR _F3] C _F2Formula (6)

Z wherein _m, z _fDifference is two zero points of LDO for this reason, p ₁, p ₂, p _fBe respectively dominant pole, the first non-dominant pole, the second non-dominant pole, C _F1, C _F2, C _LThe value of representing the 3rd capacitor C F1, the 4th capacitor C F2, load capacitance respectively; R _F1, R _F2, R _F3The resistance of representing the first resistance R F1, the second resistance R F2, the 3rd resistance R F3 resistance respectively; r _Eq, r ₀The output resistance of representing whole LDO output resistance, error amplifier respectively.

The voltage gain that has the first order amplifier of Slew Rate intensifier circuit can be by obtaining the gain phase Calais on two different paths, that is:

$A_1=A_{\mathrm{PATH}1}+A_{\mathrm{PATH}2}\≈g_{\mathrm{mn}\mathrm{3,4}}{r}_{o2}\frac{1+{\mathrm{sC}}_1/g_{\mathrm{mn}\mathrm{3,4}}}{1+{\mathrm{sC}}_1/g_{\mathrm{mn}2}}$ Formula (7)

Wherein path 1 comprises MN3, MN1, MP1, MP2, and path 2 comprises C1, MN2, and A _PATH1, A _PATH2Represent the gain of path 1 and path 2 respectively, g _Mn3,4Be the mutual conductance of MN3 or MN4, r _O2The output resistance of expression MP2, g _Mn2The mutual conductance of expression MN2.

Compare with traditional single-stage LDO, increased the z at zero point of a left half-plane _SRE=g _Mn3,4/ C _LWith a limit p _SRE=g _Mn2/ C ₁, here, C ₁Represent first electric capacity.Under underloaded situation, z _f, p _fBe designed into the low frequency place, z _SREMove on to p _fNear.Work as p _SREBe equivalent to only have during greater than unity gain bandwidth (UGB, Unity Gain Bandwidth) one zero point z _fIn unity gain bandwidth.Work as z _fBeing used for offsetting second limit (is p during underload ₂, be p under the heavy duty ₁) time, frequency compensation at this moment become simple and also efficient high.Under heavy duty, the z that does not use _mCan design at p _SREThe spread bandwidth of coming so just can obtain the unity gain bandwidth of a broad.

The transient response of tradition LDO is owing to the Slew Rate of power tube grid is restricted.Can see V by Fig. 2 _XThe maximum static Slew Rate of point is:

${\mathrm{SR}}_{\left(\mathrm{static}\right)}=\frac{I_{\mathrm{BIAS}}}{C_{\mathrm{Par}}+C_{F1}}$ Formula (8)

Here I _BIASThe bias current that expression is come in from biasing circuit, C _ParRepresent external electric capacity.Clearly, the quasistatic Slew Rate is restricted in low pressure or the design of small size power tube.But when using capacitive coupling feedforward compensation circuit, form a fast path by capacitor C 1 and metal-oxide-semiconductor MN2, so just can be with limited quiescent current at V _XThe big dynamic Slew Rate of last generation is improved transient response.

Transient state during with decline is analyzed.Suppose V _OUTThe change in voltage of point can be ignored, and works as V _OUTWhen point voltage descends, the gate discharge current of power tube M1 Can change.At this moment, the bias current I that obtains from MN6 _BIASTurn-off by second capacitor C 2, C2 is as multiplication capacitor here.

${\mathrm{SR}}_{(\mathrm{step}-\mathrm{down})}=\frac{C1}{(C_{\mathrm{Par}}+C_{F1})}\frac{{\mathrm{dV}}_{\mathrm{OUT}}}{\mathrm{dT}}$ Formula (9)

Work as V _OUTWhen point voltage rises:

${\mathrm{SR}}_{(\mathrm{step}-\mathrm{up})}=\frac{1}{(C_{\mathrm{Par}}+C_{F1})}[\frac{{(W/L)}_{M7}}{{(W/L)}_{M6}}\frac{{\mathrm{dV}}_{\mathrm{OUT}}}{\mathrm{dT}}C2+I_{\mathrm{BIAS}}]$ Formula (10)

Formula (9) and formula (10) show that dynamic Slew Rate is enhanced, and do not rely on load simultaneously, but are proportional to Δ V _OUTCompare with formula (8), under the load transient situation of change, when the Slew Rate scope can be than static state big several times.

In the present embodiment, the 0.13 μ mCMOS process modeling of use SMIC has carried out emulation to the LDO of 1.5V supply voltage, 10mV load.Input voltage based on minimum is 1.5V, when using the load capacitance of 0.2nF to carry out emulation, at the electric current that drives 50mA and only need the quiescent current of 17 μ m.Frequency response characteristic is under heavy duty (10mA) and two kinds of situations of underload (0mA), and it is stable being 50 ° in phase margin, and the unity gain bandwidth of this moment can reach 7.3MHz when heavy duty, the overshoot of output voltage simultaneously or down towards the time have only 170mV.

Low pressure difference linear voltage regulator of the present invention has very big load regulation by using the capacitive coupling Feedforward Compensation Technology, and circuit structure is simple, can be used for common differential amplifier.The structure of the present invention that shows simulation result can realize low quiescent current, ultrafast load transient response, is fit to be applied to low-pressure system.

Those of ordinary skill in the art will appreciate that embodiment described here is in order to help reader understanding's principle of the present invention, should to be understood that protection scope of the present invention is not limited to such special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combinations that do not break away from essence of the present invention according to these technology enlightenments disclosed by the invention, and these distortion and combination are still in protection scope of the present invention.

Claims (3)

1. low pressure difference linear voltage regulator, comprise error amplifier, feedback sample network, biasing circuit and Slew Rate intensifier circuit, it is characterized in that, the part of Slew Rate intensifier circuit is contained among the error amplifier, and error amplifier comprises PMOS pipe, the 2nd PMOS pipe, NMOS pipe, the 2nd NMOS pipe and the 3rd NMOS pipe, the 4th NMOS pipe; Wherein NMOS pipe and the 2nd NMOS pipe are again as the ingredient of Slew Rate intensifier circuit, and the Slew Rate intensifier circuit also comprises first electric capacity and second electric capacity; The feedback sample network comprises the 3rd PMOS pipe, first resistance, second resistance and the 3rd resistance;

Concrete annexation is as follows: PMOS pipe, the 2nd PMOS pipe are connected with the supply voltage of outside respectively with the source electrode of the 3rd PMOS pipe, the grid leak short circuit of a PMOS pipe, and link to each other with the grid of the 2nd PMOS pipe, the drain electrode of a NMOS pipe; The drain electrode of the 2nd PMOS pipe links to each other with the drain electrode of the 2nd NMOS pipe, the grid of the one NMOS pipe links to each other with the grid of the 3rd NMOS pipe, the grid of the 2nd NMOS pipe links to each other with the grid of the 4th NMOS pipe, the source electrode of the one NMOS pipe links to each other with the drain electrode of the 3rd NMOS pipe, the source electrode of the 2nd NMOS pipe links to each other with the drain electrode of the 4th NMOS pipe and as the input end of described low pressure difference linear voltage regulator, the 3rd NMOS pipe links to each other with biasing circuit with the source electrode of the 4th NMOS pipe, the source electrode of the 2nd NMOS pipe links to each other with an end of first electric capacity, the other end of first electric capacity links to each other with an end of second electric capacity, and as the output terminal of described low pressure difference linear voltage regulator, the other end of second electric capacity links to each other with the input end of biasing circuit; The grid of the 3rd PMOS pipe links to each other with the drain electrode of the 2nd PMOS pipe, and first, second, third resistance is connected between the drain electrode and ground of the 3rd PMOS pipe in turn; Second links to each other with the grid of the 3rd NMOS pipe with the tie point of the 3rd resistance.

2. low pressure difference linear voltage regulator according to claim 1, it is characterized in that, described biasing circuit comprises the 5th NMOS pipe, the 6th NMOS pipe and the 7th NMOS pipe, the source electrode of wherein said NMOS pipe is ground connection respectively, the grid of described NMOS pipe links to each other with the drain electrode of the 5th NMOS pipe respectively, the drain electrode of the 6th NMOS pipe connects the source electrode of the 4th NMOS pipe of described error amplifier, the drain electrode of the 5th NMOS pipe is as the input termination external current source of biasing circuit, and the drain electrode of the 7th NMOS pipe connects the output terminal of described low pressure difference linear voltage regulator.

3. low pressure difference linear voltage regulator according to claim 1 and 2, it is characterized in that, described low pressure difference linear voltage regulator also comprises compensating circuit, described compensating circuit comprises the 3rd electric capacity, the 4th electric capacity and the 4th resistance, wherein, one end of the 3rd electric capacity links to each other with the grid of the 3rd PMOS pipe of feedback sample network, the other end links to each other with an end of the 4th resistance, the other end of the 4th resistance links to each other with an end of the output terminal of described low pressure difference linear voltage regulator and the 4th electric capacity, and the other end of the 4th electric capacity links to each other with the grid of the 4th NMOS pipe of error amplifier.