CN101140478A - Low pressure difference linearity voltage stabilizer for enhancing performance by amplifier embedded compensation network - Google Patents
Low pressure difference linearity voltage stabilizer for enhancing performance by amplifier embedded compensation network Download PDFInfo
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- CN101140478A CN101140478A CNA2007101213202A CN200710121320A CN101140478A CN 101140478 A CN101140478 A CN 101140478A CN A2007101213202 A CNA2007101213202 A CN A2007101213202A CN 200710121320 A CN200710121320 A CN 200710121320A CN 101140478 A CN101140478 A CN 101140478A
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Abstract
A low voltage differential linear regulator utilizes an embedded compensation network in an amplifier to improve performance, which embeds a compensation network composed of resistances and capacitances into an amplifier to increase one or a plurality of pole-zero pairs with their pole-zero frequency lower than pole frequency in a transfer function of a feedback loop without changing static operating point of the amplifier and increasing static current. Frequency of the pole-zero pairs can be accurately confirmed to enhance stability of the feedback loop of the low voltage differential linear regulator, expand loop unit gain bandwidth and increase phase margin and DC and low-frequency gain of the loop, thus enhancing performance of the low voltage differential linear regulator.
Description
Technical Field
The invention relates to a low dropout regulator, in particular to a low dropout regulator which utilizes an amplifier built-in compensation network to improve the performance.
Background
Closed loop negative feedback systems are commonly used in linear integrated circuits. For example, in a Low-Dropout linear Regulator (LDO), a feedback loop is required to obtain a stable output Voltage. According to the Nyquist criterion, to ensure the stability of a closed-loop system, the phase shift of the loop at unity gain should be less than 180 degrees. Whereas in practical circuit designs it is generally desirable that the phase shift of the loop at a unit gain is less than 135 degrees (i.e. the phase margin is greater than 45 degrees). In most cases, the control of the phase shift is achieved by adding a compensation circuit in the feedback loop.
Fig. 1 shows a first typical LDO circuit in the prior art. The circuit consists of a voltage reference circuit 101, a first-stage differential amplifier 102, a power tube 104, a voltage division sampling network 105, an output capacitor 106 and a load 107. The voltage reference circuit 101 generates a constant reference voltage V that is independent of variations in supply voltage, temperature, and the like REF . Output voltage V of LDO OUT The feedback voltage V is generated after the sampling of the partial pressure sampling network 105 FB . Reference voltage V REF And a feedback voltage V FB Connected to the inverting input terminal and the non-inverting input terminal of the first stage differential amplifier 102, respectively, the voltage difference is amplified by the first stage differential amplifier 102 to generate a control signal for adjusting the operating state of the power transistor 104, thereby ensuring the output voltage V of the LDO OUT It is still nominal when the supply voltage, operating temperature, load conditions change.
In the feedback loop shown in fig. 1, there are two low frequency poles, one at the output of LDO (denoted as P1) and the other at the gate of power tube 104 (denoted as P2). Pole P1 is defined by C of output capacitor 106 OUT (usually 0.1 uF-10 uF) and the impedance of the output end of the LDO; pole P2 is formed by the gate capacitance of power tube 104 and the first stage differenceThe output impedance of the amplifier 102 is formed. Since the LDO needs to drive a large load current (e.g., 200 mA), the power transistor 104 has a large size and a large gate capacitanceLarge so that pole P2 is at low frequency. In addition, the circuit has a higher frequency pole located at the non-inverting input (denoted as P3) of the first stage differential amplifier 102. The existence of these three poles makes the feedback system a potentially unstable system.
To ensure stable operation of the LDO, one compensation method used in the circuit of FIG. 1 is to use the equivalent series resistance R of the output capacitor 106 ESR And an output capacitor C OUT Generating a low frequency zero Z ESR The zero point is used for offsetting the low-frequency pole P2, the other low-frequency pole P1 is used as a main pole of the loop, and the high-frequency pole P3 is arranged outside a unit gain bandwidth (UGF), so that the phase margin of the system is ensured to be larger than 45 degrees.
Fig. 2 shows a second typical LDO circuit. The circuit differs from the circuit shown in fig. 1 in that: the circuit is added with a second-stage amplifier 103, and a feedback voltage V FB And a reference voltage V REF Respectively connected to the inverting input terminal and the non-inverting input terminal of the first stage differential amplifier 102, and the rest is the same as in fig. 1.
In the feedback loop shown in fig. 2, there are two low frequency poles, one at the output of the LDO (denoted P1), which is bounded by C of the output capacitor 106 OUT (usually 0.1 uF-10 uF) and the impedance of the LDO output end; the other is located at the gate of the power transistor 104 (denoted as P2), which is formed by the gate capacitance of the power transistor 104 and the output impedance of the second stage amplifier 103. In addition, there are two higher frequency poles in the feedback loop shown in fig. 2, which are located at the inverting input terminal (denoted as P3) of the first stage differential amplifier 102 and the output terminal (denoted as P4) of the first stage differential amplifier 102. The presence of the four poles (P1, P2, P3, P4) makes the feedback loop a potentially unstable system.
To ensure stable operation of the LDO, a compensation method used in the circuit shown in FIG. 2 is advantageousBy equivalent series resistance R of the output capacitor 106 ESR And output capacitor C OUT Generating a low frequency zero point Z ESR The zero is used for offsetting the low-frequency pole P2, the other low-frequency pole P1 is used as a main pole of the loop, and the other two poles (P3 and P4) are arranged outside the unit gain bandwidth (UGF), so that the phase margin of the loop is ensured to be more than 45 degrees.
Fig. 3 shows a third typical LDO circuit. Compared to the circuit shown in fig. 2, the circuit adds a capacitive feedback module 208, and furthermore uses C of the output capacitor 106 OUT Having a very small R ESR The rest is the same as fig. 2. The basic principle is to loop through the introduction of the capacitive feedback block 208Generating a zero point Z in the left half-plane C Using Z C Instead of the low-frequency zero Z in fig. 2 ESR . This circuit presents the same four poles as in fig. 2, namely two low frequency poles P1, P2 and two higher frequency poles P3, P4. One commonly used compensation method is to use zero point Z C The low frequency pole P2 is cancelled, while the low frequency pole P1 acts as the dominant pole of the loop, and the remaining two higher frequency poles (P3 and P4) are placed outside the UGF.
The disadvantages of the three circuits described above (and others that require P3 or P3 and P4 to be placed outside the UGF) are:
1. the UGF of the LDO feedback loop is low due to the limitation to the location of the poles P3 and P4, especially the location of P4. The lower UGF not only causes the loop to slow in response speed, but also limits the DC gain of the loop. If the loop gain of the LDO is low, the output voltage accuracy is also reduced accordingly.
2. Due to the limitations of working conditions, manufacturing process variations, model accuracy and the like, the positions of the poles P3 and P4 cannot be accurately calculated during circuit design, which increases the difficulty of frequency compensation. To ensure stable operation of the designed circuit, the performance of the LDO is usually sacrificed.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the low dropout regulator circuit overcomes the defects of the prior art, improves the stability of an LDO feedback loop by utilizing an amplifier built-in compensation network, expands the UGF of the loop, and increases the phase margin and DC and low-frequency gain of the loop.
The technical solution of the invention is as follows: utilize the built-in compensation network of amplifier to improve linear stabiliser of low dropout of performance, contain voltage reference circuit, first level difference amplifier and power tube, the reference voltage that voltage reference circuit produced is connected to first level difference amplifier's reverse input end, first level difference amplifier's output end is connected to the grid end of power tube, the voltage output end of stabiliser is regarded as to the drain terminal of power tube, and the voltage of voltage output end is connected to first level difference amplifier's syntropy input directly or after partial pressure sampling, its characterized in that: the compensation network is arranged in the first-stage differential amplifier, and can add a zero pole pair which has zero frequency lower than pole frequency and can be accurately determined in a transfer function of a feedback loop of the voltage stabilizer under the conditions of not changing a static working point of the first-stage differential amplifier and not increasing static current, so as to enhance the stability of the feedback loop, expand the unit gain bandwidth of the loop and increase the phase margin, DC (direct current) and low-frequency gain of the loop.
The compensation network is composed of a resistor and a capacitor.
The compensation network is positioned in an active load connected in a diode mode in the first-stage differential amplifier, two ends of the resistor are respectively connected to a grid end and a drain end of the active load, one end of the capacitor is connected to the grid end of the active load, and the other end of the capacitor is grounded or fixed in potential.
One circuit connection mode of the built-in compensation network of the first-stage differential amplifier is as follows: transistors M1, M2, M3 and M4 form a first-stage differential amplifier, the transistors M1 and M2 are differential input pair transistors of the first-stage differential amplifier, and the transistors M3 and M4 are current mirror loads of the first-stage differential amplifier; a bias current source is adopted to provide bias current for the first-stage differential amplifier, one end of the bias current source is connected to power voltage, and the other end of the bias current source is connected to the source ends of the transistors M1 and M2; the grid end of the transistor M1 is the same-direction input end of the first-stage differential amplifier, and the drain end of the transistor M1 is connected with the drain end of the transistor M3, the grid end of the transistor M4 and one end of the resistor; the grid end of the transistor M2 is the reverse input end of the first-stage differential amplifier, and the drain end of the transistor M2 is the output end of the first-stage differential amplifier and is connected with the drain end of the transistor M4; one end of the resistor is connected with the grid end of the transistor M4, and the other end of the resistor is connected with the grid end of the transistor M3 and one end of the capacitor; one end of the capacitor is connected with the grid end of the M3, and the other end of the capacitor is grounded or fixed in potential; the source terminals of transistors M3 and M4 are grounded.
Utilize amplifier built-in compensation network to improve linear stabiliser of low dropout of performance, contain voltage reference circuit, first order differential amplifier and power tube, the reference voltage that voltage reference circuit produced is connected to the syntropy input or the reverse input of first order differential amplifier, the voltage output end of power tube as the stabiliser, and the voltage of voltage output end is connected to another input that does not link to each other with voltage reference circuit of first order differential amplifier directly or after dividing the voltage sampling, its characterized in that: at least one gain stage or buffer stage amplifier is arranged between the output end of the first stage differential amplifier and the grid end of the power tube, and a compensation network is arranged in at least one stage of amplifier in the gain stage or buffer stage amplifier and the first stage differential amplifier, and the compensation network can add one or more zero pole pairs with zero frequency lower than pole frequency and capable of being accurately determined in a transfer function of a feedback loop of the voltage stabilizer under the conditions of not changing a static working point of the amplifier and not increasing static current so as to enhance the stability of the feedback loop, expand the unit gain bandwidth of the loop and increase the phase margin, DC and low-frequency gain of the loop.
The compensation network is composed of a resistor and a capacitor.
When the first-stage differential amplifier is internally provided with a compensation network, the compensation network is positioned in an active load connected in a diode mode in the first-stage differential amplifier, wherein two ends of a resistor are respectively connected to a grid end and a drain end of the active load, one end of a capacitor is connected to the grid end of the active load, and the other end of the capacitor is grounded or fixed in potential.
When the gain stage or the buffer stage amplifier is internally provided with a compensation network, the compensation network is positioned inside an active load connected in a diode mode in the gain stage or the buffer stage amplifier, wherein two ends of a resistor are respectively connected to a grid end and a drain end of the active load, one end of a capacitor is connected to the grid end of the active load, and the other end of the capacitor is connected to a ground potential or a fixed potential.
One circuit connection mode of the first-stage differential amplifier built-in compensation network is as follows: transistors M1, M2, M3 and M4 form a first-stage differential amplifier, the transistors M1 and M2 are differential input pair transistors of the first-stage differential amplifier, and the transistors M3 and M4 are current mirror loads of the first-stage differential amplifier; a bias current source is adopted to provide bias current for the first-stage differential amplifier, one end of the bias current source is connected to a power supply voltage, and the other end of the bias current source is connected to the source ends of the M1 and the M2; the grid end of the transistor M1 is the homodromous input end of the first-stage differential amplifier, and the drain end of the transistor M1 is connected with the drain end of the transistor M3, the grid end of the transistor M4 and one end of the resistor; the grid end of the transistor M2 is the reverse input end of the first-stage differential amplifier, and the drain end of the transistor M2 is the output end of the first-stage differential amplifier and is connected with the drain end of the transistor M4; one end of the resistor is connected with the grid end of the transistor M4, and the other end of the resistor is connected with the grid end of the transistor M3 and one end of the capacitor; one end of the capacitor is connected with the grid end of the transistor M3, and the other end of the capacitor is grounded or fixed in potential; the source terminals of transistors M3 and M4 are grounded.
One circuit connection mode of the built-in compensation network of the gain stage amplifier or the buffer stage amplifier is as follows: the gain stage or buffer stage amplifier is formed by transistors M5, M6, M7, M8, M9, M10 and M11, the grid ends of the transistors M5 and M10 are connected to form the signal input end of the gain stage or buffer stage amplifier, and the drain ends of the transistors M10 and M11 are connected to form the signal output end of the gain stage or buffer stage amplifier; the drain end of the transistor M5 is connected with the drain end of the transistor M7, the grid end of the transistor M8 and one end of the resistor, and the source end of the transistor M5 is grounded; the grid end of the transistor M6 is connected with a fixed bias potential, the source end of the transistor M6 is grounded, and the drain end of the transistor M6 is connected with the drain end of the transistor M8, the drain end of the transistor M9 and the grid end of the transistor M11; the grid end of the transistor M7 is connected with one end of the resistor and one end of the capacitor, and the source end of the transistor M7 is connected with the power supply potential; one end of the resistor is connected with the grid end of the transistor M8, and the other end of the resistor is simultaneously connected with the grid end of the transistor M7 and one end of the capacitor; one end of the capacitor is connected with the grid end of the transistor M7, and the other end of the capacitor is connected with a power supply potential or a fixed potential; the source end of the transistor M8 is connected with the power supply potential; the grid end of the transistor M9 is connected with the grid end of the transistor M11, and the source end of the transistor M9 is connected with the power supply potential; the source end of the transistor M10 is grounded; the source terminal of the transistor M11 is connected to the power supply potential.
Compared with the prior art, the invention has the advantages that: the low dropout linear regulator with the performance improved by utilizing the amplifier built-in compensation network is based on a conventional amplifier circuit, the compensation network is arranged in the amplifier, one or more zero pole pairs with zero frequency lower than pole frequency can be generated under the condition of not changing the static working point of the amplifier and not increasing the static current, the zero pole pairs can be accurately determined, the stability of a feedback loop of the low dropout linear regulator is enhanced, the UGF of the loop is expanded, the phase margin and the DC and low frequency gain of the loop are increased, and the performance of the LDO is improved.
Drawings
FIG. 1 is a schematic block diagram of a first typical LDO of the prior art;
FIG. 2 is a schematic block diagram of a second exemplary LDO of the prior art;
FIG. 3 is a schematic block diagram of a third exemplary LDO of the prior art;
FIG. 4 is a schematic block diagram of a first exemplary LDO of the present invention;
FIG. 5 is a schematic block diagram of a second exemplary LDO of the present invention;
FIG. 6 is a schematic block diagram of a third exemplary LDO of the present invention;
FIG. 7 is a first implementation circuit of the compensation network built in the first stage differential amplifier in the schematic block diagram of the exemplary LDO shown in FIGS. 4, 5, and 6 according to the present invention;
FIG. 8 is a second implementation circuit of the compensation network built in the first stage differential amplifier in the schematic block diagrams of the typical LDO shown in FIGS. 4, 5, and 6 according to the present invention;
FIG. 9 is a third circuit for implementing the compensation network built in the first stage differential amplifier in the schematic block diagrams of the LDO of FIGS. 4, 5, and 6 according to the present invention;
FIG. 10 is a schematic diagram of a fourth implementation of the compensation network built in the first stage differential amplifier in the LDO of the exemplary LDO of FIGS. 4, 5, and 6 according to the present invention;
FIG. 11 is a first circuit for implementing a compensation network built in the second stage amplifier of the LDO schematic block diagrams of FIGS. 5 and 6 according to the present invention;
FIG. 12 is a second implementation circuit of the compensating network built in the second stage amplifier in the schematic block diagrams of the exemplary LDO shown in FIGS. 5 and 6 according to the present invention;
FIG. 13 is a third circuit for implementing a compensation network built in the second stage amplifier of the LDO schematic block diagrams of FIGS. 5 and 6 according to the present invention;
FIG. 14 is a fourth implementation circuit of the built-in compensation network of the second stage amplifier in the schematic block diagram of the LDO of FIGS. 5 and 6 according to the present invention;
FIG. 15 is a circuit for implementing the LDO of FIG. 1;
FIG. 16 is a circuit for implementing the LDO schematic block diagram of FIG. 4 according to the present invention;
FIG. 17 is a circuit for implementing the LDO of FIG. 2;
FIG. 18 is a circuit diagram of an implementation of the LDO of FIG. 5 with a compensation network built in the first stage differential amplifier;
FIG. 19 is a circuit diagram of an implementation of the LDO of FIG. 5 with a compensation network built in only the second stage amplifier according to the present invention;
FIG. 20 is a schematic diagram of an implementation circuit of the first stage differential amplifier and the second stage amplifier of the LDO of FIG. 5 with a compensation network built therein;
FIG. 21 is a schematic diagram comparing the loop gain of the circuit of FIG. 17 with the circuit of FIG. 18 according to the present invention;
FIG. 22 is a schematic diagram comparing the loop phase shift of the circuit of FIG. 17 with the circuit of FIG. 18 according to the present invention.
Detailed Description
When the feedback loop has only one stage of amplifier, as shown in fig. 4, fig. 4 differs from the circuit shown in fig. 1 in that: the conventional first stage differential amplifier 102 is replaced with a first stage differential amplifier 302 with a first compensation network 309 built in. The first stage differential amplifier 302 has two main functions: first, get V REF And V FB Amplifying the error signal and adjusting the working state of the power tube 104; second, the first compensation network 309 can add a pole-zero pair with a lower zero frequency than the pole frequency in the transfer function of the feedback loop, which can be used to cancel the higher frequency parasitic pole in the loop (e.g., the first stage differential amplifier 302)Parasitic pole P3) of the same-direction input end, thereby enhancing the stability of the LDO loop.
When the feedback loop has two stages of amplifiers, as shown in fig. 5, fig. 5 differs from the circuit shown in fig. 2 in that: the conventional first stage differential amplifier 102 is replaced with a first stage differential amplifier 302 incorporating a first compensation network 309 and the conventional second stage amplifier 103 is replaced with a second stage amplifier 303 incorporating a second compensation network 310. The first stage differential amplifier 302 has two main functions: first, get V REF And V FB Amplifying the error signal and outputting to the second stageAn input of amplifier 303; second, the built-in first compensation network 309 can add a zero-pole pair with a zero frequency lower than a pole frequency in the transfer function of the feedback loop, and the zero-pole pair is used for frequency compensation of the LDO. The second stage amplifier 303 also has two functions: firstly, receiving an error signal output by the first stage differential amplifier 302, and generating a control signal at an output end to adjust the working state of the power tube 104; second, the built-in second compensation network 310 can add a zero-pole pair with a zero frequency lower than the pole frequency in the transfer function of the feedback loop, and the zero-pole pair is also used for the frequency compensation of the LDO.
One compensation method for the LDO shown in fig. 5 is: c of the output capacitor 106 OUT And its equivalent series resistance R ESR Generated low frequency zero point Z ESR The low-frequency pole P2 at the grid of the power tube is counteracted, and the low-frequency pole P1 at the output end of the LDO serves as the main pole of the loop. Due to the addition of the first compensation network 309 and the second compensation network 310, two pole-zero pairs are added to the transfer function of the feedback loop, and these two pole-zero pairs can be used to cancel the phase shift caused by the parasitic poles in the loop (e.g., the parasitic pole P3 at the inverting input terminal of the first stage differential amplifier 302 and the parasitic pole P4 at the output terminal of the first stage differential amplifier 302), so as to enhance the stability of the loop. It should be noted that, according to the requirement of the actual LDO circuit, the first compensation network 309 and the second compensation network 310 may be used simultaneously, or only one of them may be used.
Fig. 6 shows a schematic block diagram of a third exemplary LDO of the present invention. The circuit shown in fig. 6 differs from that shown in fig. 3 in that: the conventional first stage differential amplifier 102 is replaced with a first stage differential amplifier 302 incorporating a first compensation network 309 and the conventional second stage amplifier 103 is replaced with a second stage amplifier 303 incorporating a second compensation network 310. Similar to the corresponding circuit in fig. 5, the first stage differential amplifier 302 and the second stage amplifier 303 in fig. 6 have the same effect of amplifying signals and producing a zero pole pair. One compensation method of the circuit is as follows: capacitive feedback module 208 generates in a loopZero point Z of C Offset in power tube gridThe low frequency pole P2 is located, and the other low frequency pole P1 (located at the output of the LDO) is the dominant pole of the loop. The zero pole pair generated by the first stage differential amplifier 302 and the second stage amplifier 303 is used to cancel the phase shift generated by the higher frequency parasitic pole in the loop, thereby enhancing the stability of the system. It should also be noted that, according to the requirement of the actual LDO circuit, the first compensation network 309 and the second compensation network 310 may be used simultaneously, or only one of them may be used.
Fig. 7 and 8 show two specific implementation circuits of the first stage differential amplifier 302 with the first compensation network 309 built in. The differential input pair transistors M1 and M2 of the two circuits are PMOS transistors, transistors M3 and M4 form a current mirror load, the current source 311 provides bias current for the amplifier 302, and the capacitor C and the resistor R form a compensation network, which is embedded in the amplifier 302. In fig. 7, two ends of the resistor R are respectively connected to the gate terminals of the transistors M3 and M4, one end of the capacitor C is connected to the resistor R, and the other end is connected to Ground (GND); in fig. 8, two ends of the resistor R are connected to the gates of the transistors M3 and M4, respectively, and one end of the capacitor C is connected to the resistor R and the other end is connected to the power supply Voltage (VDD).
Fig. 9 and 10 show two other implementation circuits of the first stage differential amplifier 302 with the first compensation network 309 built in. The differential input pair transistors M1 and M2 of the two circuits are NMOS transistors, the transistors M3 and M4 form a current mirror load, the current source 311 provides bias current for the amplifier 302, and the capacitor C and the resistor R form a compensation network embedded in the amplifier 302. In fig. 9, two ends of a resistor R are respectively connected to gate terminals of transistors M3 and M4, one end of a capacitor C is connected to the resistor R, and the other end is Grounded (GND); in fig. 10, the two ends of the resistor R are connected to the gates of the transistors M3 and M4, respectively, and one end of the capacitor C is connected to the resistor R and the other end is connected to the power supply Voltage (VDD).
In the four circuits shown in fig. 7 to 10, the gate terminal 312 of M1 is the non-inverting input terminal of the first-stage differential amplifier 302, the gate terminal 313 of M2 is the inverting input terminal of the first-stage differential amplifier 302, and the node 314 is the output terminal of the first-stage differential amplifier 302. In the four connection relationships shown in fig. 7 to 10, one end of the capacitor C is connected to the resistor R, and the other end is connected to the power supply Voltage (VDD) or the ground potential (GND). In fact, the end of the capacitor C connected to VDD or GND can also be connected to other fixed potential according to the actual circuit design condition.
It should be noted that the capacitor C mentioned in the present invention may be any type of capacitor that can be implemented by an integrated circuit manufacturing process, such as a MOS capacitor, a poly-poly capacitor, a metal capacitor, etc.; the resistor R may be any type of resistor that can be implemented by an integrated circuit manufacturing process, such as a diffused resistor, a sandwiched resistor, a thin film resistor, a poly resistor, a resistor formed by a MOS transistor operating in a linear region, and the like.
Fig. 11-14 show four implementations of the second stage amplifier 303 with the second compensation network 310 built in, node 322 being the input of the amplifier 303, node 324 being the output of the amplifier 303, and node 323 being connected to a fixed bias voltage. Transistors M5-M11 form a conventional push-pull amplifier stage, while resistor R and capacitor C form a built-in second compensation network 310 of amplifier 303. The introduction of the second compensation network 310 may introduce a pair of poles and zeros in the transfer function from the input 322 to the output 324 of the second stage amplifier 303, with the frequencies of the poles and zeros being lower than the frequencies of the poles. In the two connection relationships shown in fig. 11 and 12, one end of the capacitor C is connected to the resistor R, and the other end is connected to the power supply Voltage (VDD). In fact, according to the actual circuit design condition, the end of the capacitor C connected to VDD can also be connected to GND or other fixed potential; similarly, in the two connection relationships shown in fig. 13 and 14, the end of the capacitor C connected to GND can also be connected to VDD or other fixed potential.
It should be noted that although the first compensation network 309 and the second compensation network 310 are added, the first stage differential amplifier 302 and the second stage differential amplifier 303 can be any conventional amplifier known to those skilled in the art, and are not limited to the circuit configurations illustrated in fig. 7 to 14.
Fig. 15 shows a specific implementation circuit of the schematic block diagram of the first conventional exemplary LDO shown in fig. 1. The circuit has two low-frequency poles (a pole P1 at the output end of the LDO and a pole P2 at the grid of the power tube 104), a higher-frequency pole (a pole P3 at the same-direction input end of the first-stage differential amplifier 102) and a low-frequency zero Z ESR The expressions are respectively:
wherein R is LT Is the equivalent output impedance, C, of the LDO output p1 ，R o1 Lumped parasitic capacitance and output impedance, C, respectively, at the output of the first stage differential amplifier 102 p3 Is the output end (V) of the voltage division sampling network 105 FB At) is determined. One compensation method used by the circuit of fig. 15 is to use P1 as the dominant pole of the loop and use zero Z ESR The pole P2 is cancelled, ensuring that the UGF of the loop is less than the frequency of P3 at design time.
FIG. 17 shows an implementation circuit of the exemplary LDO of FIG. 2. Transistors M1-M4 and biasThe current source lbias constitutes a first stage differential amplifier 102 and the transistors M5-M8 constitute a second stage amplifier 103. The circuit has two low-frequency poles (a pole P1 at the output end of the LDO and a pole P2 at the grid of the power tube 104) and two higher-frequency poles (poles P3 and P4 at the reverse input end and the output end of the first-stage differential amplifier 102) and a low-frequency zero Z ESR The expressions are respectively:
、
、
、
、
wherein R is LT Is the equivalent output impedance, C, of the LDO output p1 ，C p2 ，R o1 ，R o2 Lumped parasitic capacitance and output impedance, C, at the output of the first stage differential amplifier 102 and the second stage amplifier 103, respectively p3 Is the output end V of the partial pressure sampling network 105 FB The lumped parasitic capacitance of (c). One compensation method employed by the circuit of fig. 17 is: p1 is used as the main pole of the loop and the zero point Z is used ESR The pole P2 is cancelled, which ensures that the UGF of the loop is less than the frequencies of P3 and P4 at design time. Typically, the frequency of P4 is lower than the frequency of P3, so the UGF and gain of the loop are limited primarily to the frequency of P4.
FIG. 16 shows an implementation circuit of the first exemplary LDO schematic block diagram of the present invention shown in FIG. 4. This circuit is identical to the circuit of fig. 15 except that it has three poles (P1, P2, P3) and one zero (Z) ESR ) In addition, a zero pole pair (zero point Z) introduced by the amplifier 302 with the first compensation network 309 built-in is also included C And pole P C )。Z C 、P C Are respectively:
wherein, g m3 Is the transconductance of transistor M3 in the first stage differential amplifier 302. One compensation method used by the circuit of fig. 16 is to use P1 as the dominant pole of the loop and use zero Z ESR Pole P2 is cancelled, using zero Z generated by the first compensation network 309 C Offsetting the pole P3, and ensuring that the UGF of the loop is less than P in design c Of (c) is detected. ByAt P C Is higher than the frequency of P3, the UGF and gain of the loop can be significantly improved.
Fig. 18 shows an implementation circuit of the second exemplary LDO of fig. 5 when only the first stage differential amplifier 302 has the first compensation network 309 built therein. The circuit of FIG. 18 except that it has three poles (P1, P2, P3) and one zero (Z) as in the circuit of FIG. 17 ESR ) In addition, the zero pole pair (zero point Z) introduced by the first-stage differential amplifier 302 with the built-in first compensation network 309 is also included CAnd pole P C ) In addition, the pole at the output of the amplifier 102 in fig. 2 becomes P4' due to the introduction of the first compensation network 309. Z is a linear or branched member C 、P C And P4' are respectively:
wherein, g m3 Is the transconductance, R, of transistor M3 in the first stage differential amplifier 302 oM2 Is the output impedance of the drain terminal of the transistor M2. One compensation method employed by the circuit of fig. 18 is: p1 is used as the main pole of the loop, and zero point Z is used ESR Counteracting the pole P2, with the zero Z generated by the first compensation network 309 C Cancel pole P4', design to ensure the UGF of the loop is less than P3 and P C Of (c) is detected. Due to P3 and P C Is typically much higher than the frequency of P4', the UGF and gain of the loop can be significantly improved.
Fig. 19 shows an implementation circuit of the second exemplary LDO of the present invention in which only the second stage amplifier 303 has the second compensation network 310 built therein. In fig. 19, the second stage amplifier 303 includes transistors M5 to M11, and a resistor R and a capacitor C form a second compensation network 310. The second compensation network 310 can introduce a zero pole pair, which can be used to improve the phase margin and system stability of the LDO feedback loop.
Fig. 20 shows an implementation circuit of the second exemplary LDO of the present invention, in which the first stage differential amplifier 302 has a first compensation network 309, and the second stage amplifier 303 has a second compensation network 310. This circuit has the same zero pole pair (zero point Z) as the circuit of fig. 18 introduced by the first stage differential amplifier 302 with the first compensation network 309 built in (zero point Z) C And pole P C ). In addition, another zero pole pair exists in fig. 20 due to the introduction of the second compensation network 310. Thus, the circuit shown in fig. 20 has two zero pole pairs in the loop due to the presence of the first 309 and second 310 compensation networks. The two zero pole pairs can be used for improving the phase margin of the LDO feedback loop and the stability of the system.
It should be noted that the compensation method given above is only one of many possible compensation methods. In fact, depending on different circuit designs and application conditions, the pole-zero pairs generated by the first compensation network 309 and the second compensation network 310 can also be used to offset the phase shift introduced by other poles in the loop, or to place the pole-zero pairs at a specific frequency, so as to improve the phase margin of the loop and improve the performance of the LDO.
To further illustrate the effect of the compensation network of the present invention on the stability of the LDO loop, the first compensation network 309 is taken as an example for description. Fig. 21 and 22 are schematic diagrams showing the loop gain and the loop phase shift of the circuits shown in fig. 17 and 18 when the load current is 150 mA. It should be noted that, in the simulation process, except for the addition of the first compensation network 309 (where the resistor R is 2Mohms and the capacitor C is 0.5 pF), other parameters of the circuit in fig. 18 are identical to the corresponding parameters of the circuit in fig. 17. In fig. 21 and 22, curves 1 and 2 are amplitude-frequency response and phase-frequency response characteristic curves of the circuit shown in fig. 17, respectively, and curves 3 and 4 are amplitude-frequency response and phase-frequency response characteristic curves of the circuit shown in fig. 18, respectively. The UGF for the circuit shown in fig. 17 is 2.5mhz and the phase shift at UGF is 145 degrees (phase margin is 35 degrees), corresponding to point a on curve 2 in fig. 22; the UGF of the circuit shown in fig. 18 is 3.9mhz and the phase shift at the UGF is 127 degrees (52 degrees with a phase margin), corresponding to point B on curve 4 in fig. 22. It can be seen that the introduction of the first compensation network 309 can effectively increase UGF (increased by 1.4MHz in this example) and phase margin (increased by 17 degrees in this example) of the LDO loop, thereby increasing loop stability and improving system performance. From another perspective, curve 2 has a phase shift of 145 degrees at a frequency of 2.5MHz (as shown at point A), and curve 4 has a phase shift of 6.3MHz (as shown at point C). This comparison shows that if the circuit of fig. 17 and the circuit of fig. 18 have the same phase margin (e.g., 35 degrees, which corresponds to a phase shift of 145 degrees), the UGF of the latter is higher, and the DC and low frequency loop gains are also higher. Under the condition that other conditions are the same, the higher the UGF of the LDO is, the faster the response speed is; the higher the loop gain, the higher its output voltage accuracy. Therefore, the introduction of the first compensation network 309 speeds up the response speed of the LDO system, and improves the output voltage accuracy of the LDO.
When the feedback loop has more than two stages of amplifiers, the principle of improving the loop performance by adopting the amplifier built-in compensation network is the same as that when the feedback loop has two stages of amplifiers, and the details are not repeated here.
It should be noted that, although the specific LDO circuits are described in the embodiments of the present invention, the description of the specific LDO circuits is only for illustrating the present invention. Various equivalent changes and modifications can be made to the examples of the present invention without departing from the principles of the invention, but modifications thereof will fall within the scope of the claims of the present invention. The invention is thus broad.
Claims (10)
1. A low dropout linear regulator utilizing an amplifier built-in compensation network to improve performance comprises a voltage reference circuit (101), a first-stage differential amplifier (302) and a power tube (104), wherein reference voltage generated by the voltage reference circuit (101) is connected to the inverting input end of the first-stage differential amplifier (302), the output end of the first-stage differential amplifier (302) is connected to the grid end of the power tube (104), the drain end of the power tube (104) is used as the voltage output end of the regulator, and the voltage of the voltage output end is directly or after partial pressure sampling, connected to the homodromous input end of the first-stage differential amplifier (302),
the method is characterized in that: the first-stage differential amplifier (302) is internally provided with a compensation network (309), and the compensation network (309) can add a zero-pole pair which has zero frequency lower than pole frequency and can be accurately determined in a transfer function of a feedback loop of the voltage stabilizer under the conditions of not changing a static working point of the first-stage differential amplifier (302) and not increasing static current, so as to enhance the stability of the feedback loop, expand the unit gain bandwidth of the loop and increase the phase margin, DC and low-frequency gain of the loop.
2. The low dropout linear regulator for improving performance using an amplifier built-in compensation network as claimed in claim 1, wherein: the compensation network (309) is composed of a resistor and a capacitor.
3. The low dropout regulator according to claim 1 or 2, wherein the low dropout regulator comprises: the compensation network (309) is positioned in an active load connected in a diode mode in the first-stage differential amplifier (302), wherein two ends of the resistor are respectively connected to a grid end and a drain end of the active load, one end of the capacitor is connected to the grid end of the active load, and the other end of the capacitor is grounded or fixed in potential.
4. The low dropout regulator according to claim 1 or 2, wherein the low dropout regulator comprises: one circuit connection mode of the built-in compensation network (309) of the first-stage differential amplifier (302) is as follows: the transistors M1, M2, M3 and M4 form a first-stage differential amplifier (302), the transistors M1 and M2 are differential input pair transistors of the first-stage differential amplifier (302), and the transistors M3 and M4 are current mirror loads of the first-stage differential amplifier (302); a bias current source is adopted to provide bias current for a first-stage differential amplifier (302), one end of the bias current source is connected to power voltage, and the other end of the bias current source is connected to the source ends of transistors M1 and M2; the grid end of the transistor M1 is the homodromous input end of the first-stage differential amplifier (302), and the drain end of the transistor M1 is connected with the drain end of the transistor M3, the grid end of the transistor M4 and one end of the resistor; the grid end of the transistor M2 is the inverting input end of the first-stage differential amplifier (302), and the drain end of the transistor M2 is the output end of the first-stage differential amplifier (302) and is connected with the drain end of the transistor M4; one end of the resistor is connected with the grid end of the transistor M4, and the other end of the resistor is connected with the grid end of the transistor M3 and one end of the capacitor; one end of the capacitor is connected with the grid end of the M3, and the other end of the capacitor is grounded or fixed in potential; the source terminals of the transistors M3 and M4 are grounded.
5. A low dropout linear regulator which utilizes an amplifier built-in compensation network to improve the performance comprises a voltage reference circuit (101), a first-stage differential amplifier (302) and a power tube (104), wherein reference voltage generated by the voltage reference circuit (101) is connected to the same-direction input end or the reverse-direction input end of the first-stage differential amplifier (302), the drain end of the power tube (104) is used as the voltage output end of the regulator, and the voltage of the voltage output end is directly or after partial pressure sampling, connected to the other input end of the first-stage differential amplifier (302) which is not connected with the voltage reference circuit,
the method is characterized in that: at least one gain stage or buffer stage amplifier is further arranged between the output end of the first stage differential amplifier (302) and the grid end of the power tube (104), and in the gain stage or buffer stage amplifier and the first stage differential amplifier (302), at least one amplifier is internally provided with a compensation network, and the compensation network can add one or more zero pole pairs which have zero frequency lower than pole frequency and can be accurately determined in a transfer function of a feedback loop of the voltage stabilizer under the conditions of not changing a static working point of the amplifier and not increasing static current so as to enhance the stability of the feedback loop, expand the unit gain bandwidth of the loop and increase the phase margin and DC and low frequency gain of the loop.
6. The LDO with performance enhancement using an amplifier built-in compensation network as claimed in claim 5, wherein: the compensation network is composed of a resistor and a capacitor.
7. The low dropout regulator according to claim 5 or 6, wherein the low dropout regulator comprises: when the first-stage differential amplifier (302) is internally provided with a compensation network, the compensation network is positioned in an active load connected in a diode mode in the first-stage differential amplifier (302), wherein two ends of a resistor are respectively connected to a grid end and a drain end of the active load, one end of a capacitor is connected to the grid end of the active load, and the other end of the capacitor is grounded or fixed in potential.
8. The low dropout regulator according to claim 5 or 6, wherein the low dropout regulator comprises: when the gain stage or the buffer stage amplifier is internally provided with a compensation network, the compensation network is positioned in an active load connected in a diode mode in the gain stage or the buffer stage amplifier, wherein two ends of a resistor are respectively connected to a grid end and a drain end of the active load, one end of a capacitor is connected to the grid end of the active load, and the other end of the capacitor is connected to a ground potential or a fixed potential.
9. The low dropout regulator according to claim 5 or 6, wherein the low dropout regulator comprises: one circuit connection mode of the built-in compensation network of the first-stage differential amplifier (302) is as follows: the transistors M1, M2, M3 and M4 form a first-stage differential amplifier (302), the transistors M1 and M2 are differential input pair transistors of the first-stage differential amplifier (302), and the transistors M3 and M4 are current mirror loads of the first-stage differential amplifier (302); a bias current source is adopted to provide bias current for the first-stage differential amplifier (302), one end of the bias current source is connected to a power supply voltage, and the other end of the bias current source is connected to the source ends of the M1 and the M2; the grid end of the transistor M1 is the same-direction input end of the first-stage differential amplifier (302), and the drain end of the transistor M1 is connected with the drain end of the transistor M3, the grid end of the transistor M4 and one end of the resistor; the grid end of the transistor M2 is the inverted input end of the first-stage differential amplifier (302), and the drain end of the transistor M2 is the output end of the first-stage differential amplifier (302) and is connected with the drain end of the transistor M4; one end of the resistor is connected with the grid end of the transistor M4, and the other end of the resistor is connected with the grid end of the transistor M3 and one end of the capacitor; one end of the capacitor is connected with the grid end of the transistor M3, and the other end of the capacitor is grounded or fixed in potential; the source terminals of transistors M3 and M4 are connected to ground.
10. The low dropout regulator according to claim 5 or 6, wherein the low dropout regulator comprises: one circuit connection mode of the built-in compensation network of the gain stage amplifier or the buffer stage amplifier is as follows: the transistors M5, M6, M7, M8, M9, M10 and M11 form a gain stage or a buffer stage amplifier, the grid ends of the transistors M5 and M10 are connected to form a signal input end of the gain stage or the buffer stage amplifier, and the drain ends of the transistors M10 and M11 are connected to form a signal output end of the gain stage or the buffer stage amplifier; the drain end of the transistor M5 is connected with the drain end of the transistor M7, the gate end of the transistor M8 and one end of the resistor, and the source end of the transistor M5 is grounded; the grid end of the transistor M6 is connected with a fixed bias potential, the source end of the transistor M6 is grounded, and the drain end of the transistor M6 is connected with the drain end of the transistor M8, the drain end of the transistor M9 and the grid end of the transistor M11; the grid end of the transistor M7 is connected with one end of the resistor and one end of the capacitor, and the source end of the transistor M7 is connected with the power supply potential; one end of the resistor is connected with the grid end of the transistor M8, and the other end of the resistor is simultaneously connected with the grid end of the transistor M7 and one end of the capacitor; one end of the capacitor is connected with the grid end of the transistor M7, and the other end of the capacitor is connected with a power supply potential or a fixed potential; the source end of the transistor M8 is connected with the power supply potential; the grid end of the transistor M9 is connected with the grid end of the transistor M11, and the source end of the transistor M9 is connected with a power supply potential; the source end of the transistor M10 is grounded; the source terminal of the transistor M11 is connected to the power supply potential.
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