CN105676932A - Off-chip capacitor LDO circuit based on self-adaptive power tube technology - Google Patents

Abstract

The invention discloses an off-chip capacitor LDO circuit based on the self-adaptive power tube technology.The circuit comprises a control voltage generation unit, a first-stage amplifier, a second-stage amplifier, a frequency compensation unit, a main power tube and an auxiliary power tube.The control voltage generation unit is used for generating control voltage Vctrl; the first input end of the first-stage amplifier is electrically connected with the output end of an LDO, the second input end of the first-stage amplifier is connected with the output end of the control voltage generation unit, the output end of the first-stage amplifier is electrically connected with the input end of the second-stage amplifier, the first end of the frequency compensation unit and the grid electrode of the auxiliary power tube respectively, the grid electrode of the main power tube is electrically connected with the output end of the second-stage amplifier, the main power tube and the source electrode of the auxiliary power tube are connected with a power source, the drain electrodes of the main and auxiliary power tubes and the second end of the frequency compensation unit are electrically connected with the output end of the LDO, and the main power tube is automatically turned on or off according to the load.The off-chip capacitor LDO circuit has the advantages of being low in working voltage, low in no-load current, high in loop gain and wide in output drive range.

Description

A kind of based on adaptive power Manifold technology without the outer electric capacity LDO circuit of sheet

Technical field

The present invention relates to LDO circuit field, more specifically, it relates to a kind of based on adaptive power Manifold technology without the outer electric capacity LDO circuit of sheet.

Background technology

Along with popularizing of the handheld device such as panel computer, smart mobile phone, people are more and more higher to the requirement of service time of battery length, and quiescent current and low input and output voltage difference seem particularly important. Low pressure difference linear voltage regulator (LDO) has low speed paper tape reader static power disspation, lower noise, and circuit structure is relatively simple, and the advantages such as peripheral component is few, and circuit scale is little, thus can be widely used in portable type electronic product equipment.

The circuit structure of traditional LDO as shown in Figure 1, need to additionally increase the outer electric capacity of a sheet at output terminal, and the value of its electric capacity reaches μ F level. The defect that the outer electric capacity of sheet also has comparison serious, its size is very big, cannot be integrated at LDO chip internal, cannot adapt to the development trend of portable type electronic product miniaturization. As shown in Figure 2, present stage, without the bulky capacitor of the outer capacitive based LDO structure of sheet owing to saving outside sheet, structure is simple, becomes the focus of research.

Compare traditional LDO, it is different without the outer main limit of capacitor type LDO of sheet and stability situation: the main limit of traditional LDO is positioned at the output terminal having huge electric capacity, and without the main limit of the outer capacitor type LDO of sheet generally at the grid of power tube; Due to the difference of their main limits and non-master pole location, the situation that each auto-stability is the severeest is also different, the worst situation of traditional LDO is when heavy load, because big load, output impedance reduces, and main limit moves toward the direction of high frequency, and the long-pending GBW of gain bandwidth also increases thereupon, and non-master limit is constant, so phase place nargin diminishes.Without the sheet situation that capacitor type LDO is worst outward but in contrast, time it occurs in underloading or zero load, during underloading, output impedance becomes big, and non-master limit moves to low frequency, also moves to GBW direction exactly, causes phase place nargin to diminish. Therefore, for without the outer capacitor type LDO of sheet, we need to study new compensation scheme to ensure the work of loop stability. Current compensation scheme has minimum load current requirement more, is difficult to stablize when zero load, it is therefore desirable to the wide compensation scheme exporting driving scope of research.

Summary of the invention

The present invention is at least one defect overcome described in above-mentioned prior art, a kind of based on adaptive power Manifold technology without the outer electric capacity LDO circuit of sheet, there is low-work voltage, low no-load electric current, high loop gain, the wide advantage exporting driving scope.

For solving the problems of the technologies described above, the technical scheme of the present invention is as follows:

A kind of based on adaptive power Manifold technology without the outer electric capacity LDO circuit of sheet, by LDO output terminal output voltage, described LDO circuit comprises control voltage generation unit, first step amplifier, second stage amplifier, frequency compensation unit, main power tube and secondary power tube, described control voltage generation unit is for generation of control voltage Vctrl and is exported by control voltage output terminal, first input terminus of described first step amplifier is electrically connected with LDO output terminal, 2nd input terminus is connected with the output terminal of control voltage generation unit, the output terminal of first step amplifier respectively with the input terminus of second stage amplifier, the grid electrical connection of the first end of frequency compensation unit and secondary power tube, the grid of main power tube is electrically connected with second stage amplifier out, the source electrode of main power tube and secondary power tube connects power supply, main power tube is electrically connected with LDO output terminal with the secondary drain electrode of power tube and the 2nd end of frequency compensation unit, main power tube opens or closes automatically according to load size.

In the preferred scheme of one, described control voltage generation unit comprises PMOS MA1, MA2, MA5, MA6 and NMOS tube MA3, MA4, MB3, MB4, and electric capacity Ca, described MA1 and MA2 connects with current-mirror structure, the i.e. drain electrode of MA2, the grid of grid and MA1 connects, the source electrode of MA2 and MA1 connects power supply, the drain electrode of MA3 is connected with the drain electrode of MA1, the grid of MA3 meets reference voltage V ref, the drain electrode of MA4 is connected with the drain electrode of MA2, the grid of MA4 is connected with the drain electrode of MA5, the source electrode of MA3 and MA4 is connected with the drain electrode of MB3, the source ground of MB3 and MB4, the grid of MB3 and MB4 connect after as the first bias current sources and output offset voltage Nbias, the grid of MA6, drain electrode is connected with the drain electrode of MB4, as the control voltage output terminal of control voltage generation unit, the drain electrode of MA5 is connected with the source electrode of MA6, the grid of MA5 is connected with the drain electrode of MA1, the source electrode of MA5 connects power supply, the drain electrode of the one termination MA3 of electric capacity Ca, the drain electrode of another termination MA5.

In the preferred scheme of one, described first step amplifier comprises PMOS M1 and MB2, NMOS tube M2 and MB1; The source electrode of described M1 is connected with LDO output terminal as the first input terminus, M1 grid is as the control voltage output terminal of the 2nd input termination control voltage generation unit, M2 source electrode is connected with M1 drain electrode, M2 grid meets biased voltage Vbias, MB1 drain electrode is connected with M1 drain electrode, MB1 source ground, MB1 grid meets biased voltage Nbias, MB2 drain electrode drain with M2 be connected and as the output terminal of first step amplifier, MB2 source electrode connects power supply, MB2 grid meets biased voltage Pbias, MB1 and MB2 all as bias current sources.The collapsible grid level amplifier altogether of M1 and M2 composition, as first step amplifier.

In the preferred scheme of one, described second stage amplifier comprises PMOS M3, M7 and M8, NMOS tube M4, M5 and M6; Described M3 grid is connected with the output terminal of first step amplifier, and M3 source electrode connects power supply, and M3 drain electrode is connected with M4 drain electrode, M4 and M5 connects with current-mirror structure, i.e. M4 drain electrode, grid are connected with M5 grid, the source ground of M4 and M5, and M6 grid is connected with M1 drain electrode, M6 source ground, M6 drain electrode is connected with M7 drain electrode, M7 and M8 connects with current-mirror structure, i.e. M7 drain electrode, grid are connected with M8 grid, the source electrode of M7 and M8 connects power supply, M8 drain electrode with M5 drain be connected and as second stage amplifier out.

M3, M4 and M5 form a positive gaining amplifier, and M6, M7 and M8 form a feedforward passage, can improve phase place nargin; M5 and M8 forms a push pull output stage, can strengthen Slew Rate, it is achieved to the grid capacitance fast charging and discharging of main power tube, strengthens the load transient response of LDO.

In the preferred scheme of one, described frequency compensation unit comprises miller compensation electric capacity Cm and M2, the Cm noted earlier first termination M2 source electrode, and the 2nd termination LDO output terminal, Cm and M2 forms folding-compensation structure. M2 works to cut off the passage that feedovers from first step amplifier to LDO output terminal, and contrast tradition miller compensation, folding-compensation eliminates Right-half-plant zero, and realizes higher electric current-bandwidth efficiency.

The breadth-length ratio of main power tube MP2 is tens times of secondary power tube MP1, when circuit working, according to load current size, main power tube MP2 can automatically close or open, correspondingly, LDO is operated in two-stage amplifier and three grades of amplifier states respectively, thus is convenient to the stability that LDO keeps loop when different loads.

Compared with prior art, the useful effect of technical solution of the present invention is: the present invention provide a kind of based on adaptive power Manifold technology without the outer electric capacity LDO circuit of sheet, comprise control voltage generation unit, first step amplifier, second stage amplifier, frequency compensation unit, main power tube and secondary power tube, described control voltage generation unit is for generation of control voltage Vctrl and is exported by control voltage output terminal, first input terminus of described first step amplifier is electrically connected with LDO output terminal, 2nd input terminus is connected with the output terminal of control voltage generation unit, the output terminal of first step amplifier respectively with the input terminus of second stage amplifier, the grid electrical connection of the first end of frequency compensation unit and secondary power tube, the grid of main power tube is electrically connected with second stage amplifier out, the source electrode of main power tube and secondary power tube connects power supply, main power tube is electrically connected with LDO output terminal with the secondary drain electrode of power tube and the 2nd end of frequency compensation unit, main power tube opens or closes automatically according to load size. the structure of polystage amplifier, it is achieved that the high gain of loop, therefore the line regulation of LDO and load regulation performance are also very significantly improved. the present invention has low-work voltage, low no-load electric current, high loop gain, the wide advantage exporting driving scope.

Accompanying drawing explanation

Fig. 1 is the structural representation of traditional low pressure difference linear voltage regulator.

Fig. 2 is the structural representation without the outer capacitor type low pressure difference linear voltage regulator of sheet.

Fig. 3 is LDO circuit structural representation of the present invention.

Fig. 4 is that control voltage of the present invention produces circuit.

Fig. 5 is LDO main body circuit of the present invention.

Fig. 6 is the small-signal model under LDO of the present invention is in two-stage amplifier state.

Fig. 7 is the small-signal model under LDO of the present invention is in three grades of amplifier states.

Embodiment

Accompanying drawing, only for exemplary illustration, can not be interpreted as the restriction to this patent; To those skilled in the art, some known features and illustrate and may omit and be appreciated that in accompanying drawing.

Below in conjunction with drawings and Examples, the technical scheme of the present invention is described further.

Embodiment 1

As shown in Figure 3, a kind of based on adaptive power Manifold technology without the outer electric capacity LDO circuit of sheet, by LDO output terminal output voltage, described LDO circuit comprises control voltage generation unit, first step amplifier, second stage amplifier, frequency compensation unit, main power tube and secondary power tube, described control voltage generation unit is for generation of control voltage Vctrl and is exported by control voltage output terminal, first input terminus of described first step amplifier is electrically connected with LDO output terminal, 2nd input terminus is connected with the output terminal of control voltage generation unit, the output terminal of first step amplifier respectively with the input terminus of second stage amplifier, the grid electrical connection of the first end of frequency compensation unit and secondary power tube, the grid of main power tube is electrically connected with second stage amplifier out, the source electrode of main power tube and secondary power tube connects power supply, main power tube is electrically connected with LDO output terminal with the secondary drain electrode of power tube and the 2nd end of frequency compensation unit, main power tube opens or closes automatically according to load size.

I_LFor LDO load, its one end ground connection, another termination LDO output terminal, C_ppWith I_LParallel connection, C_ppFor walking the stray capacitance of line, generally in pF rank, IL and C_ppIn parallel.

As shown in Figure 3, in specific implementation process, described control voltage generation unit comprises PMOS MA1, MA2, MA5, MA6 and NMOS tube MA3, MA4, MB3, MB4, and electric capacity Ca, described MA1 and MA2 connects with current-mirror structure, the i.e. drain electrode of MA2, the grid of grid and MA1 connects, the source electrode of MA2 and MA1 connects power supply, the drain electrode of MA3 is connected with the drain electrode of MA1, the grid of MA3 meets reference voltage V ref, the drain electrode of MA4 is connected with the drain electrode of MA2, the grid of MA4 is connected with the drain electrode of MA5, the source electrode of MA3 and MA4 is connected with the drain electrode of MB3, the source ground of MB3 and MB4, the grid of MB3 and MB4 connect after as the first bias current sources and output offset voltage Nbias, the grid of MA6, drain electrode is connected with the drain electrode of MB4, as the control voltage output terminal of control voltage generation unit, the drain electrode of MA5 is connected with the source electrode of MA6, the grid of MA5 is connected with the drain electrode of MA1, the source electrode of MA5 connects power supply, the drain electrode of the one termination MA3 of electric capacity Ca, the drain electrode of another termination MA5.

Control voltage generation unit main body is the amplifier of a unity gain, V_refIt is a votage reference source unrelated with temperature and voltage of supply, V_SGA6For the source gate voltage of MA6, by the known V of circuit connecting relation_ctrl=V_ref-V_SGA6。

As shown in Figure 5, in specific implementation process, described first step amplifier comprises PMOS M1 and MB2, NMOS tube M2 and MB1; The source electrode of described M1 is connected with LDO output terminal as the first input terminus, M1 grid is as the control voltage output terminal of the 2nd input termination control voltage generation unit, M2 source electrode is connected with M1 drain electrode, M2 grid meets biased voltage Vbias, MB1 drain electrode is connected with M1 drain electrode, MB1 source ground, MB1 grid meets biased voltage Nbias, MB2 drain electrode drain with M2 be connected and as the output terminal of first step amplifier, MB2 source electrode connects power supply, MB2 grid meets biased voltage Pbias, MB1 and MB2 all as bias current sources.The collapsible grid level amplifier altogether of M1 and M2 composition, as first step amplifier.

By circuit connecting relation it will be seen that the output V of LDO output terminal_out=V_ctrl+V_SG1, V_SG1For the source gate voltage of M1, the bias current of adjustment M1 and MA6 and breadth-length ratio so that V_SG1=V_SGA6, thus have V_out=V_ref。

In specific implementation process, described second stage amplifier comprises PMOS M3, M7 and M8, NMOS tube M4, M5 and M6; Described M3 grid is connected with the output terminal of first step amplifier, and M3 source electrode connects power supply, and M3 drain electrode is connected with M4 drain electrode, M4 and M5 connects with current-mirror structure, i.e. M4 drain electrode, grid are connected with M5 grid, the source ground of M4 and M5, and M6 grid is connected with M1 drain electrode, M6 source ground, M6 drain electrode is connected with M7 drain electrode, M7 and M8 connects with current-mirror structure, i.e. M7 drain electrode, grid are connected with M8 grid, the source electrode of M7 and M8 connects power supply, M8 drain electrode with M5 drain be connected and as second stage amplifier out.

M3, M4 and M5 form a positive gaining amplifier, and M6, M7 and M8 form a feedforward passage, can improve phase place nargin; M5 and M8 forms a push pull output stage, can strengthen Slew Rate, it is achieved to the grid capacitance fast charging and discharging of main power tube, strengthens the load transient response of LDO.

In specific implementation process, described frequency compensation unit comprises miller compensation electric capacity Cm and M2, the Cm noted earlier first termination M2 source electrode, and the 2nd termination LDO output terminal, Cm and M2 forms folding-compensation structure. M2 works to cut off the passage that feedovers from first step amplifier to LDO output terminal, and contrast tradition miller compensation, folding-compensation eliminates Right-half-plant zero, and realizes higher electric current-bandwidth efficiency.

As shown in Figure 5, described main power tube MP2 grid connects second stage amplifier out, and source electrode connects power supply, and drain electrode connects LDO output terminal. Stating secondary power tube MP1 grid and connect first step amplifier out, source electrode connects power supply, and drain electrode connects LDO output terminal.

The breadth-length ratio of main power tube MP2 is tens times of secondary power tube MP1, and time unloaded, main power tube MP2 is in shutoff state, and nearly all load current is all provide by secondary power tube MP1, the source gate voltage V of MP1_SGP1Less, M3 is in sub-threshold region, and the electric current flowing through M3-M5 is very little, and M8 is forced to be operated in dark linear section, V₃It is driven high close to VDD, so main power tube MP2 turns off, therefore, as load current I_L<I_on(I_onLoad current threshold for definition) time, LDO can regard two-stage amplifier structure as, only consumes very little power. Along with load current increases gradually, V_SGP1Increasing gradually, the electric current flowing through M3-M5 also increases gradually, V₃Reduce gradually, work as I_L>I_onTime, M8 departs from linear section, begins operating in saturation region, and second stage amplifier and main power tube MP2 start to activate, and now LDO turns into three grades of amplifier architectures, and loop gain also starts to increase.

The structure of polystage amplifier, it is achieved that the high gain of loop, therefore the line regulation of LDO and load regulation performance are also very significantly improved.

As shown in Figure 6 and Figure 7, be respectively LDO of the present invention be in two-stage and three grades of amplifier states under small-signal model, wherein each V_iEquivalent output resistance and the shunt capacitance of (i=1,2,3, lower same) are denoted as R respectively_iAnd C_i, have R₁=1/g_m2,R₂≈r_oB2,R₃=r_o5‖r_o8, wherein r_oiIt is M_iSmall-signal output resistance, R_O2=r_oMP1‖r_load, R_O3=r_oMP1‖r_oMP2‖r_load, r_oMP1,r_oMP2And r_loadIt is MP respectively₁,MP₂Small-signal output resistance, pull-up resistor.

Work as I_L<I_on, LDO can regard two-stage amplifier structure as, now the resistance R of output terminal_O2=r_oMP1‖r_load, owing to load current is very little, so R_O2Very big.Transport function is:

$L_2\left(s\right)=\frac{A_{dc}(1+s\frac{C_m}{g_{m2}})}{(1+\frac{s}{p_{-3dB}})(1+s\frac{C_O{C}_2}{C_m{g}_{MP1}}+s^2\frac{C_O{C}_2}{g_{m2}{g}_{MP1}})}---\left(1\right)$

Wherein A_dcIt is low frequency gain, p_-3dBIt is main limit,

A_dc=-g_m1g_MP1R₂R_O2(2)

$p_{-3dB}=-\frac{1}{C_m{g}_{MP1}{R}_2{R}_{O2}}---\left(3\right)$

GBW is

$GBW=\frac{g_{m1}}{C_m}---\left(4\right)$

Secondary limit and zero point are

$p_2=-\frac{C_m{g}_{MP1}}{C_O{C}_2}---\left(5\right)$

$p_3=-\frac{g_{m2}}{c_m}---\left(6\right)$

$z_1=-\frac{g_{m2}}{C_m}---\left(7\right)$

By (3)-(7) it will be seen that system only has z₁A Left half-plane zero point, and and p₃Disappearing mutually, main limit is unique limit in GBW, so loop stability is primarily of p₂Determine, p₂With g_MP1It is directly proportional, also namely it is directly proportional to the square root of load current, so, the worst situation of stability is when zero load, as long as stability when therefore ensureing zero load, along with load current increases, p₂Moving to higher frequency, system stability is more good.

Work as I_L>I_onTime, LDO can regard three grades of amplifier architectures as, and now the resistance of output terminal is R_O3=r_oMP1‖r_oMP2‖r_load, owing to load current is relatively big, r_loadLess, so R_O3Less. Transport function is:

$L_3\left(s\right)=\frac{A_{dc}(1+s\frac{C_m}{g_{m2}})(1+s\frac{C_3{g}_{MP1}}{g_{m3}{g}_{MP2}})}{(1+\frac{s}{p_{-3dB}})(1+s\frac{C_2{g}_{m6}{g}_{MP2}+C_3{g}_{m2}{g}_{MP1}}{g_{m2}{g}_{m3}{g}_{MP2}}+s^2\frac{C_2{C}_3}{g_{m2}{g}_{m3}{g}_{MP2}{R}_{O3}})(1+{\mathrm{sC}}_O{R}_{O3})}---\left(8\right)$

A_dcIt is low frequency gain, p_-3dBIt is main limit,

A_dc=-g_m1g_m3g_MP2R₂R₃R_O3(9)

$p_{-3dB}=-\frac{1}{C_m{g}_{m3}{g}_{MP2}{R}_2{R}_3{R}_{O3}}---\left(10\right)$

GBW is

$GBW=\frac{g_{m1}}{C_m}---\left(11\right)$

Secondary limit and Q coefficient are

$\left|p_{2,3}\right|=\sqrt{\frac{g_{m2}{g}_{m3}{g}_{MP2}{R}_{O3}}{C_2{C}_3}}---\left(12\right)$

$Q=\frac{1}{C_2{g}_{m6}{g}_{MP2}+C_3{g}_{m2}{g}_{MP1}}\sqrt{\frac{C_2{C}_3{g}_{m2}{g}_{m3}{g}_{MP2}}{R_{O3}}}---\left(13\right)$

By (12) (13) it will be seen that | p_2,3| molecule is very big, so being easy to adjust to high frequency, and Q and output resistance R_O3It is inversely proportional to, when fully loaded R_O3Minimum, Q is maximum. In order to reduce Q value, thus avoid the impact at point peak, the g when designing_m6, g_MP1Bigger value should be got.

$p_4=-\frac{1}{C_O{R}_{O3}}---\left(14\right)$

p₄Depend on output capacitance and resistance, and output resistance is inversely proportional to outward current, along with electric current increases, p₄Move to higher frequency.

$z_1=-\frac{g_{m2}}{C_m}---\left(15\right)$

$z_2=-\frac{g_{m3}{g}_{MP2}}{C_3{g}_{MP1}}---\left(16\right)$

When designing, g_m2Get and compare g_m1Bigger value so that z₁It is in the position slightly bigger than GBW, it is to increase phase place nargin. z₂In very high frequency, its impact can be ignored.

By analyzing above it will be seen that when the worst situation of LDO stability occurs in minimum load current and overall loading electric capacity, so LDO is stable within the scope of zero load to relatively heavy load.

Above-described embodiments of the present invention, do not form limiting the scope of the present invention. Any amendment, equivalent replacement and improvement etc. done within the spiritual principles of the present invention, all should be included within the claims of the present invention.

Claims (5)

1. one kind based on adaptive power Manifold technology without the outer electric capacity LDO circuit of sheet, by LDO output terminal output voltage, it is characterized in that, described LDO circuit comprises control voltage generation unit, first step amplifier, second stage amplifier, frequency compensation unit, main power tube and secondary power tube, described control voltage generation unit is for generation of control voltage Vctrl and is exported by control voltage output terminal, first input terminus of described first step amplifier is electrically connected with LDO output terminal, 2nd input terminus is connected with the output terminal of control voltage generation unit, the output terminal of first step amplifier respectively with the input terminus of second stage amplifier, the grid electrical connection of the first end of frequency compensation unit and secondary power tube, the grid of main power tube is electrically connected with second stage amplifier out, the source electrode of main power tube and secondary power tube connects power supply, main power tube is electrically connected with LDO output terminal with the secondary drain electrode of power tube and the 2nd end of frequency compensation unit, main power tube opens or closes automatically according to load size.

2. according to claim 1 based on adaptive power Manifold technology without the outer electric capacity LDO circuit of sheet, it is characterised in that, described control voltage generation unit comprises PMOS MA1, MA2, MA5, MA6 and NMOS tube MA3, MA4, MB3, MB4, and electric capacity Ca, described MA1 and MA2 connects with current-mirror structure, the i.e. drain electrode of MA2, the grid of grid and MA1 connects, the source electrode of MA2 and MA1 connects power supply, the drain electrode of MA3 is connected with the drain electrode of MA1, the grid of MA3 meets reference voltage V ref, the drain electrode of MA4 is connected with the drain electrode of MA2, the grid of MA4 is connected with the drain electrode of MA5, the source electrode of MA3 and MA4 is connected with the drain electrode of MB3, the source ground of MB3 and MB4, the grid of MB3 and MB4 connect after as the first bias current sources and output offset voltage Nbias, the grid of MA6, drain electrode is connected with the drain electrode of MB4, as the control voltage output terminal of control voltage generation unit, the drain electrode of MA5 is connected with the source electrode of MA6, the grid of MA5 is connected with the drain electrode of MA1, the source electrode of MA5 connects power supply,The drain electrode of the one termination MA3 of electric capacity Ca, the drain electrode of another termination MA5.

3. according to claim 2 based on adaptive power Manifold technology without the outer electric capacity LDO circuit of sheet, it is characterised in that, described first step amplifier comprises PMOS M1 and MB2, NMOS tube M2 and MB1; The source electrode of described M1 is connected with LDO output terminal as the first input terminus, M1 grid is as the control voltage output terminal of the 2nd input termination control voltage generation unit, M2 source electrode is connected with M1 drain electrode, M2 grid meets biased voltage Vbias, MB1 drain electrode is connected with M1 drain electrode, MB1 source ground, MB1 grid meets biased voltage Nbias, MB2 drain electrode drain with M2 be connected and as the output terminal of first step amplifier, MB2 source electrode connects power supply, MB2 grid meets biased voltage Pbias, MB1 and MB2 all as bias current sources.

4. according to claim 3 based on adaptive power Manifold technology without the outer electric capacity LDO circuit of sheet, it is characterised in that, described second stage amplifier comprises PMOS M3, M7 and M8, NMOS tube M4, M5 and M6; Described M3 grid is connected with the output terminal of first step amplifier, and M3 source electrode connects power supply, and M3 drain electrode is connected with M4 drain electrode, M4 and M5 connects with current-mirror structure, i.e. M4 drain electrode, grid are connected with M5 grid, the source ground of M4 and M5, and M6 grid is connected with M1 drain electrode, M6 source ground, M6 drain electrode is connected with M7 drain electrode, M7 and M8 connects with current-mirror structure, i.e. M7 drain electrode, grid are connected with M8 grid, the source electrode of M7 and M8 connects power supply, M8 drain electrode with M5 drain be connected and as second stage amplifier out.

5. according to claim 3 based on adaptive power Manifold technology without the outer electric capacity LDO circuit of sheet, it is characterized in that, described frequency compensation unit comprises miller compensation electric capacity Cm and described M2, the Cm first termination M2 source electrode, 2nd termination LDO output terminal, plays frequency compensation effect.