CN213634248U

CN213634248U - Enhancement type buffer suitable for LDO circuit and LDO circuit thereof

Info

Publication number: CN213634248U
Application number: CN202120018476.3U
Authority: CN
Inventors: 张顺; 王自鑫; 姚剑锋; 袁凤江; 胡炳翔; 杨锐佳
Original assignee: FOSHAN BLUE ROCKET ELECTRONICS CO LTD
Current assignee: FOSHAN BLUE ROCKET ELECTRONICS CO LTD
Priority date: 2021-01-04
Filing date: 2021-01-04
Publication date: 2021-07-06
Anticipated expiration: 2031-01-04

Abstract

The utility model belongs to the power supply circuit field, especially an enhancement mode buffer and LDO circuit suitable for LDO circuit, including first MOS pipe M1, second MOS pipe M2, third MOS pipe M3, fourth MOS pipe M4, fifth MOS pipe M5, sixth MOS pipe M6, first current source I1, second current source I2, third current source I3 and fourth current source I4; an input end VIN1 of the buffer is a gate of the first MOS transistor M1, an output end VOUT1 of the buffer is a source of the first MOS transistor M1, and the source of the first MOS transistor M1 is connected to the drain of the first current source I1, the drain of the third MOS transistor M3, and the drain of the second MOS transistor M2, respectively. The utility model discloses output impedance is little to the amplifier tube size is also little, has not only strengthened LDO's transient response, saves space moreover.

Description

Enhancement type buffer suitable for LDO circuit and LDO circuit thereof

Technical Field

The utility model belongs to the power supply circuit field, especially an enhancement mode buffer and LDO circuit suitable for LDO circuit.

Background

The existing electronic products generally have the characteristics of high speed, high performance, high reliability and the like, and the power management chip is taken as a core component in the electronic equipment and is responsible for the conversion, detection and transmission of electric energy and other related important responsibilities of power management, and the quality of the performance of the power management chip has direct influence on the performance of the whole machine; a Low drop out Regulator (LDO) circuit is one of power management chips, and is increasingly widely used in portable consumer electronics products due to its small area and simple application; the main role of the LDO is to provide accurate, stable, low-ripple, low-output-noise dc voltage to the load, and the input and output voltage drops can be very small, usually only a few hundred millivolts, or even lower. Referring to fig. 1a, the classical structure of the LDO mainly includes several modules, namely, a reference voltage circuit VREF, an error amplifier circuit EA, a power tube MP, a feedback loop composed of a sampling resistor R1 and a sampling resistor R2, and a load capacitor C1. However, in order to make the LDO respond to load changes quickly, the capacitance of the load capacitor C1 is often selected to be larger to freewheel the load, so as to avoid too large overcharge and undershoot voltages, the larger capacitance of C1 may generate a low frequency pole at the output end, and the high output impedance of the error amplifier EA and the power transistor MP may also generate a low frequency pole, so that the LDO has stability problems.

Referring to fig. 1b, it is common to add a buffer between the error amplifier EA and the power transistor MP, so that the pole of the gate of the power transistor can be placed outside the unity gain bandwidth, but when the large-area power transistor MP is selected to output a large load current (e.g. above 50 mA), the gate capacitance is larger due to the large-area power transistor MP, and it is necessary to design a circuit with a large gate capacitanceA buffer of lower output impedance; conventional buffers are typically simple followers with an output impedance of

Wherein g is_mIs the transconductance of the source follower amplifier tube,

μ is the carrier mobility, C_oxIs the gate oxide capacitance per unit area, W/L is the width-to-length ratio W/L, V of the amplifier tube_ovIs an overdrive voltage due to μ and C_oxThe process parameters are not adjustable, V_ovThe amplifier can only be realized by increasing W/L in order to reduce output impedance, which is determined by factors such as dynamic range of the circuit, and the like, so that the size of the amplifier tube is large, and the development trend of integration is not facilitated.

Disclosure of Invention

In order to overcome the defects of the prior art, the utility model provides an enhancement mode buffer and LDO circuit suitable for LDO circuit, output impedance is little to the amplifier tube size is also little, has not only strengthened LDO's transient response, saves space moreover. The utility model discloses the technical problem that solve is realized through following technical scheme:

an enhancement type buffer suitable for an LDO circuit comprises a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a first current source I1, a second current source I2, a third current source I3 and a fourth current source I4; an input end VIN1 of the buffer is a gate of a first MOS transistor M1, an output end VOUT1 of the buffer is a source of the first MOS transistor M1, the source of the first MOS transistor M1 is connected with a first current source I1, a drain of a third MOS transistor M3 and a drain of a second MOS transistor M2, respectively, and the drain of the first MOS transistor M1 is connected with a second current source I2, a gate of the second MOS transistor M2 and a source of a fourth MOS transistor M4, respectively;

the source electrode of the second MOS tube M2 is grounded; the grid electrode of the third MOS transistor M3 is respectively connected with the third current source I3, the drain electrode of the fourth MOS transistor M4 and the grid electrode of the fifth MOS transistor M5, and the source electrode of the third MOS transistor M3 is connected with the input voltage VIN; the gate of the fourth MOS transistor M4 is connected to the gate of the sixth MOS transistor M6; the drain of the fifth MOS transistor M5 is connected to the drain of the sixth MOS transistor M6, and the source of the fifth MOS transistor M5 is connected to the input voltage VIN; the source of the sixth MOS transistor M6 is connected to the fourth current source I4; the other terminal of the first current source I1 is connected to the input voltage VIN, the other terminal of the third current source I3 is connected to the input voltage VIN, the other terminal of the second current source I2 is grounded, and the other terminal of the fourth current source I4 is grounded.

Furthermore, the first MOS transistor M1, the third MOS transistor M3, and the fifth MOS transistor M5 are P-type MOS transistors.

Furthermore, the second MOS transistor M2, the fourth MOS transistor M4, and the sixth MOS transistor M6 are N-type MOS transistors.

Further, the first current source I1, the second current source I2, the third current source I3 and the fourth current source I4 are current mirrors.

In particular, the first MOS transistor M1 and the second MOS transistor M2 form a shunt feedback loop, and the third MOS transistor M3, the fourth MOS transistor M4 and the first MOS transistor M1 form a parallel feedback loop.

In particular, the fifth MOS transistor M5, the sixth MOS transistor M6, and the fourth current source I4 provide a bias voltage for the gate of the fourth MOS transistor M4.

The utility model provides a LDO circuit suitable for enhancement mode buffer of LDO circuit, includes error amplifier, first resistance R1, second resistance R2, load capacitance, power tube MP and enhancement mode buffer, and the output of error amplifier is connected with enhancement mode buffer's input VIN1, and power tube MP's drain electrode is connected with enhancement mode buffer's output VOUT 1.

The utility model discloses output impedance is little to the amplifier tube size is also little, has not only strengthened LDO's transient response, saves space moreover.

Drawings

FIG. 1 is a schematic circuit diagram of a prior art;

FIG. 2 is a schematic circuit diagram of the present invention;

fig. 3 is a circuit diagram of the utility model discloses be applied to the LDO circuit.

Detailed Description

Fig. 2 is a schematic circuit diagram of the present invention, as shown in fig. 2, an enhanced buffer suitable for an LDO circuit, including a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a first current source I1, a second current source I2, a third current source I3, and a fourth current source I4; an input end VIN1 of the buffer is a gate of a first MOS transistor M1, an output end VOUT1 of the buffer is a source of the first MOS transistor M1, the source of the first MOS transistor M1 is connected to a drain of the first current source I1, a drain of the third MOS transistor M3 and a drain of the second MOS transistor M2, and the drain of the first MOS transistor M1 is connected to a gate of the second current source I2, a gate of the second MOS transistor M2 and a source of the fourth MOS transistor M4.

The first MOS transistor M1, the third MOS transistor M3 and the fifth MOS transistor M5 are P-type MOS transistors, and the second MOS transistor M2, the fourth MOS transistor M4 and the sixth MOS transistor M6 are N-type MOS transistors; the specific structures of the first current source I1, the second current source I2, the third current source I3 and the fourth current source I4 are not limited, and the first current source I1, the second current source I2, the third current source I3 and the fourth current source I4 in this embodiment are current mirrors.

The first MOS transistor M1 and the second MOS transistor M2 form a shunt feedback loop, the third MOS transistor M3, the fourth MOS transistor M4 and the first MOS transistor M1 form a parallel feedback loop, and the fifth MOS transistor M5, the sixth MOS transistor M6 and the fourth current source I4 provide bias voltage for the gate of the fourth MOS transistor M4.

When the current of the first MOS transistor M1 increases, the gate voltage of the second MOS transistor M2 also increases, so that the buffer output voltage decreases, and when the buffer output voltage decreases, the source-gate voltage of the first MOS transistor M1 decreasesThe voltage is also reduced, so that the current of the first MOS transistor M1 is reduced, and a negative feedback function is realized; the fifth MOS transistor M5, the sixth MOS transistor M6, and the fourth current source I4 provide a bias voltage for the gate of the fourth MOS transistor M4, and at this time, the third MOS transistor M3, the fourth MOS transistor M4, and the first MOS transistor M1 also form a parallel feedback loop; the two negative feedback loops effectively reduce the output impedance of the whole buffer, and the equivalent output impedance R of the circuit can be obtained by analyzing the small signals of the circuit_o＝1/(1/r_o2+1/r_o3+g_m2(1+g_m1r_o1)+g_m3(1+g_m1r_o1)(1+g_m4r_o4))≈1/(g_m1r_o1(g_m2+g_m3)+g_m3g_m4r_o4(1+g_m1r_o1) Obviously, relative to the source follower of the prior art: (

Wherein g is_mTransconductance of the source follower amplifier tube) can only be increased by increasing g of the amplifier tube_mObtain low output impedance, the utility model discloses can be through adjusting transconductance g that first MOS pipe M1, second MOS pipe M2, third MOS pipe M3, fourth MOS pipe M4 correspond_m1，g_m2，g_m3，g_m4Lower output impedance is obtained, and low output impedance can be obtained without large transconductance, so that the LDO circuit is better driven.

Fig. 3 is the utility model discloses be applied to the circuit diagram of LDO circuit, as shown in fig. 3, a LDO circuit suitable for enhancement mode buffer of LDO circuit, including error amplifier, first resistance R1, second resistance R2, load capacitance, power tube MP and enhancement mode buffer, error amplifier's output and enhancement mode buffer's input VIN1 are connected, power tube MP's drain electrode is connected with enhancement mode buffer's output VOUT1, the amplifier tube's of LDO circuit size is little, the integration of the circuit of being convenient for.

In a word, the utility model discloses output impedance is little to the amplifier tube size is also little, has not only strengthened LDO's transient response, saves space moreover.

Claims

1. An enhancement type buffer suitable for an LDO circuit is characterized by comprising a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a first current source I1, a second current source I2, a third current source I3 and a fourth current source I4; an input end VIN1 of the buffer is a gate of a first MOS transistor M1, an output end VOUT1 of the buffer is a source of the first MOS transistor M1, the source of the first MOS transistor M1 is connected to a drain of a first current source I1, a drain of a third MOS transistor M3 and a drain of a second MOS transistor M2, and the drain of the first MOS transistor M1 is connected to a drain of a second current source I2, a gate of the second MOS transistor M2 and a source of a fourth MOS transistor M4;

the source electrode of the second MOS tube M2 is grounded; the grid electrode of the third MOS transistor M3 is respectively connected with a third current source I3, the drain electrode of the fourth MOS transistor M4 and the grid electrode of the fifth MOS transistor M5, and the source electrode of the third MOS transistor M3 is connected with the input voltage VIN; the gate of the fourth MOS transistor M4 is connected with the gate of a sixth MOS transistor M6; the drain electrode of the fifth MOS transistor M5 is connected with the drain electrode of the sixth MOS transistor M6, and the source electrode of the fifth MOS transistor M5 is connected with the input voltage VIN; the source of the sixth MOS transistor M6 is connected to the fourth current source I4;

the other end of the first current source I1 is connected to the input voltage VIN, the other end of the third current source I3 is connected to the input voltage VIN, the other end of the second current source I2 is grounded, and the other end of the fourth current source I4 is grounded.

2. The enhanced buffer suitable for an LDO circuit as claimed in claim 1, wherein said first MOS transistor M1, third MOS transistor M3, and fifth MOS transistor M5 are P-type MOS transistors.

3. The enhanced buffer of claim 1, wherein the second MOS transistor M2, the fourth MOS transistor M4, and the sixth MOS transistor M6 are N-type MOS transistors.

4. The enhanced buffer for an LDO circuit of claim 1, wherein said first current source I1, second current source I2, third current source I3 and fourth current source I4 are current mirrors.

5. The enhanced buffer for an LDO circuit as claimed in claim 1, wherein the first MOS transistor M1 and the second MOS transistor M2 form a shunt feedback loop, and the third MOS transistor M3, the fourth MOS transistor M4 and the first MOS transistor M1 form a parallel feedback loop.

6. The enhanced buffer of claim 1, wherein the fifth MOS transistor M5, the sixth MOS transistor M6, and the fourth current source I4 provide a bias voltage for the gate of the fourth MOS transistor M4.

7. An LDO circuit suitable for an enhancement buffer of an LDO circuit as claimed in any of claims 1-6, comprising an error amplifier, a first resistor R1, a second resistor R2, a load capacitor, a power tube MP and said enhancement buffer, wherein the output terminal of said error amplifier is connected to the input terminal VIN1 of the enhancement buffer, and the drain terminal of said power tube MP is connected to the output terminal VOUT1 of the enhancement buffer.