CN116860052A - Negative feedback voltage stabilizing circuit and front-end voltage stabilizing circuit - Google Patents
Negative feedback voltage stabilizing circuit and front-end voltage stabilizing circuit Download PDFInfo
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- CN116860052A CN116860052A CN202310562557.3A CN202310562557A CN116860052A CN 116860052 A CN116860052 A CN 116860052A CN 202310562557 A CN202310562557 A CN 202310562557A CN 116860052 A CN116860052 A CN 116860052A
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
The application discloses a negative feedback voltage stabilizing circuit and a front-end voltage stabilizing circuit, wherein the negative feedback voltage stabilizing circuit comprises: the first resistor and the second resistor are connected in series, one end of the first resistor and one end of the second resistor are connected with the source electrode of the junction field effect transistor, and the other end of the second resistor is grounded; the base electrode of the first triode is connected between the first resistor and the second resistor, and the collector electrode of the first triode is connected with the source electrode of the junction field effect transistor; the base electrodes of the second triode and the third triode are connected with each other, the collector electrodes of the second triode and the third triode are connected with the emitting electrode of the first triode, and the emitting electrodes of the second triode and the third triode are grounded; the base electrode of the third triode is also connected with the collector electrode of the third triode; the grid electrode of the first NMOS transistor is connected with the collector electrode of the second triode, and the drain electrode of the first NMOS transistor is connected with the grid electrode of the junction field effect transistor and then connected with the source electrode of the junction field effect transistor through a third resistor. The circuit can realize the voltage stabilization of the output voltage under the condition of large-range change of the input voltage, and has a simple structure.
Description
Technical Field
The application relates to the technical field of analog integrated circuits, in particular to a negative feedback voltage stabilizing circuit and a front-end voltage stabilizing circuit.
Background
Smart power integrated circuits tend to have a wide input range, typically power supply inputs can vary from a few volts to tens of volts. For example: the LED driver chip needs high and low voltage power rails, the motor driver chip needs to operate in a voltage variation range of tens of volts, the car battery management chip needs to detect voltage fluctuations in a very large range, etc. While the logic circuit modules in the chip need to operate in a stable low voltage environment of a few volts. In a common voltage stabilizing and reducing scheme, a DC-DC can introduce larger ripple voltage, and a circuit is also complicated; LDOs are often used to generate new power rails on-chip due to their simple circuit structure and stable output voltage. In addition, almost all chips need bandgap reference circuits, and most of the existing bandgap reference circuits are designed in a low-voltage environment to avoid using high-voltage devices with uniformity and larger layout area to ensure high precision of reference voltages. Therefore, the front-end voltage stabilizing circuit is indispensable in the high-voltage chip, the circuit is often positioned between a power supply and a circuit of the power supply to be supplied, the functions of pre-reducing the excessive power supply voltage, reducing the power supply noise interference, improving the power supply stability and the like can be realized, and the output voltage can be used as the working power supply of the power supply module in the chip.
Because logic modules and other analog modules in the high voltage chip have high stability requirements for their own operating voltages, it is necessary to change widely varying supply voltages to stable low voltages. The traditional solution is to use a zener diode as a core device of the front-end voltage stabilizing circuit, and generally, the voltage stabilizing value of the zener diode is directly used as the output voltage of the front-end voltage reducing circuit, so that a high-voltage bias circuit is needed to provide working current for the zener diode, but in order to reduce the power consumption of the bias circuit, a megaohm-level resistor is often used, so that the area of a layout is increased, and the cost is increased. In addition, the voltage stabilizing value of the voltage stabilizing diode is often fixed, and the voltage stabilizing value is seriously affected by temperature. The voltage stabilizing diodes with different temperature coefficients are often used in series when the voltage stabilizing diodes are required to realize stable voltage reduction in a wide temperature range, but the stability and the adjustability of the output voltage are difficult to be considered when the temperature stability and the power supply voltage are widely changed, and the working state of a circuit module working under the voltage is influenced.
Therefore, the voltage stabilizing circuit which has smaller layout area, lower cost and higher stability and adjustability in a wide temperature range is provided, and the problem to be solved is urgent.
Disclosure of Invention
Therefore, in order to solve the above problems in the prior art, the present application provides a negative feedback voltage stabilizing circuit and a front end voltage stabilizing circuit.
According to a first aspect, the present application provides a negative feedback voltage stabilizing circuit, coupled between a gate and a source of a junction field effect transistor, wherein a drain of the junction field effect transistor is a power input terminal, and a source is an output terminal; the negative feedback voltage stabilizing circuit comprises:
the first resistor and the second resistor are connected in series, one end of the first resistor and one end of the second resistor are connected with the source electrode of the junction field effect transistor, and the other end of the second resistor is grounded;
the base electrode of the first triode is connected between the first resistor and the second resistor, and the collector electrode of the first triode is connected with the source electrode of the junction field effect transistor;
the base electrodes of the second triode and the third triode are connected with each other, the emitting electrodes of the second triode and the third triode are grounded, and the collecting electrodes of the second triode and the third triode are connected with the emitting electrodes of the first triode; the base electrode of the third triode is also connected with the collector electrode of the third triode;
the grid electrode of the first NMOS transistor is connected with the collector electrode of the second triode, and the drain electrode of the first NMOS transistor is connected with the grid electrode of the junction field effect transistor and then connected with the source electrode of the junction field effect transistor through a third resistor.
In an alternative embodiment, the negative feedback voltage regulator circuit further comprises:
the fourth resistor is connected between the collector electrode of the second triode and the emitter electrode of the first triode; the grid electrode of the first NMOS tube is connected between the collector electrode of the second triode and the fourth resistor;
and the fifth resistor is connected between the collector electrode of the third triode and the emitter electrode of the first triode.
In an alternative embodiment, the negative feedback voltage regulator circuit further comprises:
and the sixth resistor is connected with the emitter of the second triode.
According to a second aspect, the present application also provides a front-end voltage stabilizing circuit, comprising:
the negative feedback voltage regulator circuit according to any one of the embodiments of the first aspect;
the band gap reference circuit comprises a current source, a seventh resistor, a second NMOS tube and a third NMOS tube, wherein a first input end and a second input end of the current source are connected with the output end of the negative feedback voltage stabilizing circuit; the drain electrode of the second NMOS tube is connected with the first output end of the current source, and the source electrode is grounded; one end of the seventh resistor is connected with the second output end of the current source and the grid electrode of the third NMOS tube, and the other end of the seventh resistor is connected with the grid electrode of the second NMOS tube and the drain electrode of the third NMOS tube; the source electrode of the third NMOS tube is grounded; the second output terminal of the current source outputs a bandgap reference voltage.
In an alternative embodiment, the current source comprises:
the grid electrodes of the first PMOS tube are also connected to the drain electrode of the first PMOS tube;
the drain electrodes of the fourth NMOS tube and the fifth NMOS tube are respectively connected with the drain electrodes of the first PMOS tube and the second PMOS tube, the grid electrodes of the fourth NMOS tube and the fifth NMOS tube are mutually connected, and the grid electrode of the fifth NMOS tube is also connected to the drain electrode of the fifth NMOS tube; the sources of the two are respectively a first output end and a second output end of the current source;
the bandgap reference circuit further includes:
the sources of the third PMOS tube and the fourth PMOS tube are connected with the output end of the negative feedback voltage stabilizing circuit; the grid electrode of the third PMOS tube is connected between the drain electrode of the first PMOS tube and the drain electrode of the fourth NMOS tube; the grid electrode of the fourth PMOS tube is connected with the drain electrode of the third PMOS tube, and the drain electrode is connected between the drain electrode of the second PMOS tube and the drain electrode of the fifth NMOS tube.
In an alternative embodiment, the bandgap reference circuit further comprises:
one end of the first capacitor is connected with the grid electrode of the fourth PMOS tube, and the other end of the first capacitor is grounded.
In an alternative embodiment, the front-end voltage regulator circuit further includes:
the linear voltage stabilizing circuit comprises an operational amplifier, a fifth PMOS tube, an eighth resistor and a ninth resistor; the inverting input end of the operational amplifier is connected with the second output end of the current source, and the output end of the operational amplifier is connected with the grid electrode of the fifth PMOS tube; the source electrode of the fifth PMOS tube is connected with the output end of the negative feedback voltage stabilizing circuit, and the drain electrode of the fifth PMOS tube is sequentially connected with the eighth resistor and the ninth resistor and then grounded; the non-inverting input end of the operational amplifier is connected between the eighth resistor and the ninth resistor;
and outputting linear voltage between the drain electrode of the fifth PMOS tube and the eighth resistor.
In an alternative embodiment, the linear voltage stabilizing circuit further comprises:
one end of the second capacitor is connected with the output end of the operational amplifier and the grid electrode of the fifth PMOS tube, and the other end of the second capacitor is connected with the drain electrode of the fifth PMOS tube and the eighth resistor; and outputting linear voltage between the drain electrode of the fifth PMOS tube and the second capacitor.
The technical scheme provided by the application has the following advantages:
1. according to the negative feedback voltage stabilizing circuit provided by the application, through the arrangement of the first resistor, the second resistor, the first triode, the second triode and the third triode, negative feedback is formed between the grid electrode and the source electrode of the junction field effect transistor, so that when the source electrode output potential of the junction field effect transistor rises due to the influence of external factors, the grid end potential is reversely changed to be reduced, the grid source voltage of the junction field effect transistor is reduced, the drain source voltage is increased, and finally, the rising source electrode output potential is pulled down again due to the influence of the external factors, so that voltage stabilization is realized; meanwhile, by arranging a first NMOS tube with a drain electrode connected with a grid electrode and a source electrode (the connection between the drain electrode and the source electrode is indirect connection through a third resistor), the junction field effect transistor works in a constant current area, and when Ids and VGS are determined, the potential of the grid electrode is constant due to the limitation of the first NMOS tube, so that the potential of a source end is constant; finally, the negative feedback voltage stabilizing circuit effectively realizes the output voltage stabilization under a larger range of input power supply with a simpler circuit structure.
2. According to the front-end voltage stabilizing circuit provided by the application, the current source with the clamping effect and almost equal output potential of the first output end and the second output end is arranged, and the second NMOS tube, the third NMOS tube and the seventh resistor are arranged between the first output end and the second output end of the current source, so that the current on the seventh resistor is a positive temperature current with the ratio of the difference between the gate source voltages of the second NMOS tube and the third NMOS tube and the R7 resistance value, namely, even if the voltage on the seventh resistor is a positive temperature voltage and the gate source voltage of the third NMOS tube is a negative temperature voltage, the front-end voltage stabilizing circuit can output the band gap reference voltage which does not change along with the change of the temperature and the output voltage of the negative feedback voltage stabilizing circuit, and the voltage output stability is higher.
3. The front-end voltage stabilizing circuit provided by the application improves the power supply rejection ratio of the whole circuit by arranging the linear voltage stabilizing circuit, and further improves the voltage stabilizing effect of the whole circuit.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a negative feedback voltage stabilizing circuit provided in embodiment 1 of the present application;
fig. 2 is a schematic structural diagram of another negative feedback voltage stabilizing circuit according to embodiment 1 of the present application;
fig. 3 is a schematic diagram of a front-end voltage stabilizing circuit according to embodiment 2 of the present application;
fig. 4 is a schematic diagram of another front-end voltage stabilizing circuit according to embodiment 2 of the present application.
Detailed Description
The following description of the embodiments of the present application will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the application are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be noted that the azimuth or positional relationship indicated by the terms "upper", "lower", etc. are based on the azimuth or positional relationship shown in the drawings, and are merely for convenience of describing the present application and simplifying the description, and are not indicative or implying that the apparatus or element in question must have a specific azimuth, be constructed and operated in a specific azimuth, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Example 1
Fig. 1 shows a schematic structural diagram of a negative feedback voltage stabilizing circuit in an implementation manner of this embodiment, specifically, as shown in fig. 1, the negative feedback voltage stabilizing circuit is disposed between a gate and a source of a junction field effect transistor (fig. 1 shows that the junction field effect transistor is an N-channel junction field effect transistor, NJFET, for example), so as to stabilize a low voltage output (i.e., VO1 in fig. 1, which is a relatively stable value, such as 5V) by using a power supply voltage (i.e., VIN in fig. 1, which may have a relatively large fluctuation range, such as 8V to 45V) input to a voltage input terminal connected to a drain of the junction field effect transistor.
Specifically, as shown in fig. 1, the negative feedback voltage stabilizing circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a first triode Q1, a second triode Q2, a third triode Q3, and a first NMOS MN1, where one end of the first resistor R1 and one end of the second resistor R2 are connected in series, and the other end of the first resistor R1 and the second resistor R2 are connected with the source of the junction field effect transistor, and the other end of the first resistor R2 is grounded; the base electrode of the first triode Q1 is connected between the first resistor R1 and the second resistor R2, and the collector electrode is connected with the source electrode of the junction field effect transistor; the bases of the second triode Q2 and the third triode Q3 are connected with each other, the emitters are grounded, and the collectors are connected with the emitter of the first triode Q1; the base electrode of the third triode Q3 is also connected with the collector electrode of the third triode Q3; the gate of the first NMOS transistor MN1 is connected with the collector of the second triode Q2, and the drain is connected with the gate of the junction field effect transistor and then connected with the source of the junction field effect transistor through a third resistor R3.
In the negative feedback voltage stabilizing circuit of the present embodiment, when the input power voltage VIN starts to rise from 0, the output voltage VO1 does not establish a stable voltage, the first NMOS transistor MN1 is not turned on, and thus the gate-source voltage V of the junction field effect transistor NJFET GSNFET =0, the junction field effect transistor nffet is turned on and the circuit starts up normally; when the power supply voltage VIN rises, the output voltage VO1 correspondingly starts to rise, and the output voltage VO1 is sampled and acts on the base electrode of the first triode Q1 through the first resistor R1 and the second resistor R2; when the power voltage VIN rises to the point that the first transistor Q1, the second transistor Q2 and the third transistor Q3 are all turned on, the collector potential of the second transistor Q2 (i.e., the potential at the point B in fig. 1) starts to rise gradually to turn on the first NMOS transistor MN 1; the first NMOS transistor MN1 operating in the saturation or linear region has the gate potential (i.e., the potential at the point B in fig. 1) and the drain potential (i.e., the potential at the point C in fig. 1) thereof opposite in trend, so that negative feedback between the gate and the source of the junction field effect transistor nffet is achieved (the potential at the point B in fig. 1 corresponds to the source potential of the junction field effect transistor nffet, and the potential at the point C in fig. 1 corresponds to the gate potential of the junction field effect transistor nffet); when the junction field effect transistor NJFET operates in the constant current region, the drain current I of the junction field effect transistor NJFET ds Determining gate-source voltage V GSNFET With this determination, the first NMOS MN1 makes the gate potential of the jfet constant, so the source potential of the jfet is constant at |vgs|.
Meanwhile, negative feedback is performed between the grid electrode and the source electrode of the junction field effect transistor NJFET, so that: when the external factors cause the transfusionWhen the output voltage VO1 increases, the base potential of the first transistor Q1 (i.e., the potential at the point a in fig. 1) and the collector potential of the second transistor Q2 (i.e., the potential at the point B in fig. 1, i.e., the gate potential of the first NMOS transistor MN 1) increase, so that the drain potential of the first NMOS transistor MN1 (i.e., the potential at the point C in fig. 1) decreases, and the gate-source voltage V of the junction field effect transistor nffet GSNFET Lowering; that is, the gate-source voltage V of the junction field effect transistor NJFET during the rising of the output voltage VO1 by external factors GSNFET Reducing the drain-source voltage V DSNFET With a consequent increase, eventually causing its source potential (output voltage VO 1) to decrease.
Finally, when the output voltage VO1 of the circuit is influenced by external factors to change, the output voltage value can be relatively stable due to the negative feedback effect of the structure of the circuit.
In order to further improve the stability of the circuit, as shown in fig. 2, in an alternative implementation manner of this embodiment, the negative feedback voltage stabilizing circuit may further include a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6, where the fourth resistor R4 is connected between the collector of the second triode Q2 and the emitter of the first triode Q1 (in this case, the gate of the first NMOS transistor MN1 is connected between the collector of the second triode Q2 and the fourth resistor R4); the fifth resistor R5 is connected between the collector of the third triode Q3 and the emitter of the first triode Q1; one end of the sixth resistor R6 is connected with the emitter of the second triode Q2, and the other end of the sixth resistor R is grounded.
In summary, in the negative feedback voltage stabilizing circuit of the present embodiment, by setting the first resistor R1, the second resistor R2, the first triode Q1, the second triode Q2 and the third triode Q3, negative feedback is formed between the gate and the source of the junction field effect transistor, so that when the source output potential of the junction field effect transistor rises due to the influence of external factors, the gate-end potential is reversely changed to reduce, and further the gate-source voltage of the junction field effect transistor is reduced, the drain-source voltage is increased, and finally the source output potential rising due to the influence of external factors is pulled down again, thereby realizing voltage stabilization; meanwhile, by arranging the first NMOS transistor MN1 with the drain electrode connected with the grid electrode and the source electrode (the connection between the drain electrode and the source electrode is indirect connection through a third resistor R3), the junction field effect transistor works in a constant current area, and when Ids and VGS are determined, the junction field effect transistor is limited by the first NMOS transistor MN1 and the grid electrode potential is constant, so that the source end potential is constant; finally, the negative feedback voltage stabilizing circuit in the embodiment effectively realizes the output voltage stabilization under a larger range of input power supply with a simpler circuit structure.
Example 2
Fig. 3 shows a schematic structural diagram of a front-end voltage stabilizing circuit in one implementation manner of this embodiment, and as shown in fig. 3, the front-end voltage stabilizing circuit further includes a bandgap reference circuit on the basis of the negative feedback voltage stabilizing circuit in the above embodiment 1.
As shown in fig. 3, the bandgap reference circuit includes a current source, a seventh resistor R7, a second NMOS transistor MN2, and a third NMOS transistor MN3, where a first input terminal and a second input terminal of the current source are both connected to an output terminal VO1 of the negative feedback voltage stabilizing circuit; the drain electrode of the second NMOS tube MN2 is connected with the first output end of the current source, and the source electrode is grounded; one end of the seventh resistor R7 is connected with the second output end of the current source and the grid electrode of the third NMOS tube MN3, and the other end of the seventh resistor R7 is connected with the grid electrode of the second NMOS tube MN2 and the drain electrode of the third NMOS tube MN 3; the source electrode of the third NMOS tube MN3 is grounded; the second output of the current source (i.e., point F in fig. 3) outputs a bandgap reference voltage.
In the bandgap reference circuit of this embodiment, based on the shielding effect of the current source cascode structure, the first output terminal and the second output terminal thereof are clamped, and the potentials are almost equal, so that the current on the seventh resistor R7 is the ratio of the difference between the gate-source voltages of the second NMOS transistor MN2 and the third NMOS transistor MN3 to the resistance thereof, and is a positive temperature current, that is, the voltage on the seventh resistor R7 is a positive temperature voltage; the gate-source voltage of the third NMOS MN3 is a negative temperature voltage, so the bandgap reference voltage (i.e., the voltage at the point F in fig. 3) outputted by the bandgap reference circuit does not change with the temperature and VO1, and has high stability.
In an alternative specific embodiment, the current source may be a current source independent of a power supply voltage, specifically, as shown in fig. 3, the current source may include a first PMOS transistor MP1 and a second PMOS transistor MP2, a fourth NMOS transistor MN4 and a fifth NMOS transistor MN5, where sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are a first input terminal and a second input terminal of the current source respectively, gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected to each other, and the gate of the first PMOS transistor MP1 is also connected to its drain; the drains of the fourth NMOS tube MN4 and the fifth NMOS tube MN5 are respectively connected with the drains of the first PMOS tube MP1 and the second PMOS tube MP2, the gates of the fourth NMOS tube MN4 and the fifth NMOS tube MN5 are mutually connected, and the gate of the fifth NMOS tube MN5 is also connected to the drain of the fifth NMOS tube MN 5. At this time, as shown in fig. 3, the sources of the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 are the first output terminal and the second output terminal of the current source, respectively.
In order to improve the cascode shielding effect of the current source, as shown in fig. 4, in an alternative embodiment, the bandgap reference circuit may further include a third PMOS transistor MP3 and a fourth PMOS transistor MP4, sources of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected to the output terminal VO1 of the negative feedback voltage stabilizing circuit, a gate of the third PMOS transistor MP3 is connected between a drain of the first PMOS transistor MP1 and a drain of the fourth NMOS transistor MN4, a gate of the fourth PMOS transistor MP4 is connected to a drain of the third PMOS transistor MP3, and a drain of the fourth PMOS transistor MP4 is connected between a drain of the second PMOS transistor MP2 and a drain of the fifth NMOS transistor MN 5.
In order to provide stability of the bandgap reference circuit, as shown in fig. 4, in an alternative embodiment, the bandgap reference circuit may further include a first capacitor C1, where one end of the first capacitor C1 is connected to the gate of the fourth PMOS transistor MP4, and the other end is grounded.
In summary, in the front-end voltage stabilizing circuit of the present embodiment, by setting the current source having the clamping effect and the output potential of the first output end and the second output end being almost equal, and setting the second NMOS transistor MN2, the third NMOS transistor MN3 and the seventh resistor R7 between the first output end and the second output end of the current source, the current on the seventh resistor R7 is a positive temperature current of the ratio of the difference between the gate source voltages of the second NMOS transistor MN2 and the third NMOS transistor MN3 and the R7 resistance, that is, the voltage on the seventh resistor R7 is a positive temperature voltage, and the gate source voltage of the third NMOS transistor MN3 is a negative temperature voltage, therefore, the front-end voltage stabilizing circuit can output the bandgap reference voltage which does not change with the change of the temperature and the output voltage of the negative feedback voltage stabilizing circuit, and the voltage output stability is higher.
In order to improve the voltage stabilizing effect of the front-end voltage stabilizing circuit in this embodiment and improve the power supply rejection ratio of the output voltage of the front-end voltage stabilizing circuit, as shown in fig. 4, in an alternative implementation manner of this embodiment, the front-end voltage stabilizing circuit may further include a linear voltage stabilizing circuit, where the linear voltage stabilizing circuit includes an operational amplifier U1, a fifth PMOS transistor MP5, an eighth resistor R8, and a ninth resistor R9, where an inverting input terminal of the operational amplifier U1 is connected to a second output terminal of the current source, and an output terminal is connected to a gate of the fifth PMOS transistor MP 5; the source electrode of the fifth PMOS tube MP5 is connected with the output end VO1 of the negative feedback voltage stabilizing circuit, and the drain electrode is sequentially connected with the eighth resistor R8 and the ninth resistor R9 and then grounded; the non-inverting input terminal of the operational amplifier U1 is connected between the eighth resistor R8 and the ninth resistor R9. At this time, a linear voltage VOUT is output between the drain of the fifth PMOS transistor R9 and the eighth resistor R8.
The operational amplifier U1 in the present embodiment may be any existing operational amplifier such as a five-tube amplifier or a folded cascode operational amplifier, and is not limited herein.
In the linear voltage stabilizing circuit of the present embodiment, the output linear voltage vout=vf (1+r8/R9), where VF refers to the F-point voltage in fig. 4, that is, the bandgap reference voltage output by the bandgap reference circuit, has excellent temperature stability, and therefore VOUT also has excellent temperature stability.
The power supply rejection ratio (the power supply rejection ratio from VOUT to VO 1) of the linear voltage regulator circuit can be approximately expressed as:
psrr=20log (1/a+ (1+r8/R9)), where a refers to the open loop gain of the operational amplifier.
In order to improve the stability of the above-mentioned linear voltage stabilizing circuit, as shown in fig. 4, in an alternative embodiment, the linear voltage stabilizing circuit may further include a second capacitor C2, where one end of the second capacitor is connected to the output end of the operational amplifier U1 and the gate of the fifth PMOS transistor MP5, and the other end of the second capacitor is connected to the drain of the fifth PMOS transistor MP5 and the eighth resistor R8. At this time, the output port of the linear voltage is located between the drain of the fifth PMOS MP5 and the second capacitor C2.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While obvious variations or modifications are contemplated as falling within the scope of the present application.
Claims (8)
1. The negative feedback voltage stabilizing circuit is characterized by being coupled between a grid electrode and a source electrode of a junction field effect transistor, wherein the drain electrode of the junction field effect transistor is a power supply input end, and the source electrode is an output end; the negative feedback voltage stabilizing circuit comprises:
the first resistor and the second resistor are connected in series, one end of the first resistor and one end of the second resistor are connected with the source electrode of the junction field effect transistor, and the other end of the first resistor and the other end of the second resistor are grounded;
the base electrode of the first triode is connected between the first resistor and the second resistor, and the collector electrode of the first triode is connected with the source electrode of the junction field effect transistor;
the base electrodes of the second triode and the third triode are connected with each other, the emitting electrodes of the second triode and the third triode are grounded, and the collecting electrodes of the second triode and the third triode are connected with the emitting electrodes of the first triode; the base electrode of the third triode is also connected with the collector electrode of the third triode;
and the grid electrode of the first NMOS transistor is connected with the collector electrode of the second triode, and the drain electrode of the first NMOS transistor is connected with the grid electrode of the junction field effect transistor and then is connected with the source electrode of the junction field effect transistor through a third resistor.
2. The negative feedback voltage regulator circuit of claim 1, further comprising:
the fourth resistor is connected between the collector electrode of the second triode and the emitter electrode of the first triode; the grid electrode of the first NMOS tube is connected between the collector electrode of the second triode and the fourth resistor;
and the fifth resistor is connected between the collector electrode of the third triode and the emitter electrode of the first triode.
3. The negative feedback voltage-regulator circuit of claim 2, further comprising:
and the sixth resistor is connected with the emitter of the second triode.
4. A front-end voltage regulator circuit, comprising:
a negative feedback voltage regulator circuit as claimed in any one of claims 1 to 3;
the band gap reference circuit comprises a current source, a seventh resistor, a second NMOS tube and a third NMOS tube, wherein a first input end and a second input end of the current source are connected with the output end of the negative feedback voltage stabilizing circuit; the drain electrode of the second NMOS tube is connected with the first output end of the current source, and the source electrode is grounded; one end of the seventh resistor is connected with the second output end of the current source and the grid electrode of the third NMOS tube, and the other end of the seventh resistor is connected with the grid electrode of the second NMOS tube and the drain electrode of the third NMOS tube; the source electrode of the third NMOS tube is grounded; the second output end of the current source outputs a band gap reference voltage.
5. The front-end voltage regulator circuit of claim 4, wherein the current source comprises:
the source electrodes of the first PMOS tube and the second PMOS tube are the first input end and the second input end of the current source respectively, the grid electrodes of the first PMOS tube and the second PMOS tube are connected with each other, and the grid electrode of the first PMOS tube is also connected to the drain electrode of the first PMOS tube;
the drains of the fourth NMOS tube and the fifth NMOS tube are respectively connected with the drains of the first PMOS tube and the second PMOS tube, the grids of the fourth NMOS tube and the fifth NMOS tube are mutually connected, and the grid of the fifth NMOS tube is also connected to the drain of the fifth NMOS tube; the sources of the two are the first output end and the second output end of the current source respectively;
the bandgap reference circuit further includes:
the sources of the third PMOS tube and the fourth PMOS tube are connected with the output end of the negative feedback voltage stabilizing circuit; the grid electrode of the third PMOS tube is connected between the drain electrode of the first PMOS tube and the drain electrode of the fourth NMOS tube; the grid electrode of the fourth PMOS tube is connected with the drain electrode of the third PMOS tube, and the drain electrode is connected between the drain electrode of the second PMOS tube and the drain electrode of the fifth NMOS tube.
6. The front-end voltage regulator circuit of claim 5, wherein the bandgap reference circuit further comprises:
and one end of the first capacitor is connected with the grid electrode of the fourth PMOS tube, and the other end of the first capacitor is grounded.
7. The front-end voltage regulator circuit according to any one of claims 4 to 6, further comprising:
the linear voltage stabilizing circuit comprises an operational amplifier, a fifth PMOS tube, an eighth resistor and a ninth resistor; the inverting input end of the operational amplifier is connected with the second output end of the current source, and the output end of the operational amplifier is connected with the grid electrode of the fifth PMOS tube; the source electrode of the fifth PMOS tube is connected with the output end of the negative feedback voltage stabilizing circuit, and the drain electrode of the fifth PMOS tube is sequentially connected with the eighth resistor and the ninth resistor and then grounded; the non-inverting input end of the operational amplifier is connected between the eighth resistor and the ninth resistor;
and outputting linear voltage between the drain electrode of the fifth PMOS tube and the eighth resistor.
8. The front-end voltage regulator circuit of claim 7, wherein the linear voltage regulator circuit further comprises:
one end of the second capacitor is connected with the output end of the operational amplifier and the grid electrode of the fifth PMOS tube, and the other end of the second capacitor is connected with the drain electrode of the fifth PMOS tube and the eighth resistor; and outputting the linear voltage between the drain electrode of the fifth PMOS tube and the second capacitor.
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| CN202310562557.3A CN116860052A (en) | 2023-05-16 | 2023-05-16 | Negative feedback voltage stabilizing circuit and front-end voltage stabilizing circuit |
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| CN202310562557.3A CN116860052A (en) | 2023-05-16 | 2023-05-16 | Negative feedback voltage stabilizing circuit and front-end voltage stabilizing circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110069090A (en) * | 2018-01-23 | 2019-07-30 | 赛卓电子科技（上海）有限公司 | High pressure hall position sensor chip voltage regulator circuit |
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- 2023-05-16 CN CN202310562557.3A patent/CN116860052A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110069090A (en) * | 2018-01-23 | 2019-07-30 | 赛卓电子科技（上海）有限公司 | High pressure hall position sensor chip voltage regulator circuit |
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